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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 908 occurrences of 401 keywords
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Results
Found 1076 publication records. Showing 1076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
31 | Rafail Psiakis |
Performance Optimization Mechanisms for Fault-Resilient VLIW Processors. (Mécanismes d'optimisation des performances des processeurs VLIW à tolérance de fautes). ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2018 |
RDF |
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30 | Thorsten Jungeblut, Gregor Sievers, Mario Porrmann, Ulrich Rückert 0001 |
Design Space Exploration for Memory Subsystems of VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: Fifth International Conference on Networking, Architecture, and Storage, NAS 2010, Macau, China, July 15-17, 2010, pp. 377-385, 2010, IEEE Computer Society, 978-0-7695-4134-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CoreVA, Cache, Design Space Exploration, VLIW, Memory Subsystem |
30 | Dimitris Theodoropoulos, Alexandros Siskos, Dionisios N. Pnevmatikatos |
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 318-323, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Cryptography, VLIW, reconfigurable processors |
30 | Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck |
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(6), pp. 672-683, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RISC/CISC, low-power design, memory management, real-time and embedded systems, VLIW architectures, memory design |
30 | Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy |
VLIW: a case study of parallelism verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 779-782, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
parallelism, test generation, VLIW, functional verification, processor verification |
30 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon |
Exploiting data forwarding to reduce the power budget of VLIW embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 252-257, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
VLIW embedded architectures, low-power, pipeline processors, forwarding |
30 | David López 0001, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the International Conference on Parallel Processing 1999, ICPP 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 22-29, 1999, IEEE Computer Society, 0-7695-0350-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
ILP limits, multiply-add fused, performance/cost evaluation, software pipelining, VLIW architectures, numerical code |
30 | Zhao Wu, Wayne H. Wolf |
Trace-Driven Studies of VLIW Video Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: Proceedings of the Tenth Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA '98, Puerto Vallarta, Mexico, June 28 - July 2, 1998, pp. 289-297, 1998, ACM, 0-89791-989-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VSP, trace-driven scheduling, parallelism, parallel architecture, MPEG, VLIW, media processor, video applications |
30 | Soo-Mook Moon, Kemal Ebcioglu |
Performance Analysis of Tree VLIW Architecture for Exploiting Branch ILP in Non-Numerical Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 11th international conference on Supercomputing, ICS 1997, Vienna, Austria, July 7-11, 1997, pp. 301-308, 1997, ACM, 0-89791-902-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
branch code motion, generalized multiway braching, speculative code motion, tree VLIW architecture, conditional execution |
30 | B. Ramakrishna Rau |
Dynamically scheduled VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas, USA, November 1993, pp. 80-92, 1993, ACM / IEEE Computer Society, 0-8186-5280-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
multiple operation issue, scoreboarding, dynamic scheduling, out-of-order execution, VLIW processors |
30 | Soo-Mook Moon, Kemal Ebcioglu |
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, USA, November 1992, pp. 55-71, 1992, ACM / IEEE Computer Society, 0-8186-3175-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
compile-time parallelization, instruction-level parallelism, VLIW, superscalar |
27 | Xing Fang, Dong Wang, Shuming Chen |
SPVA: A novel digital signal processor architecture for Software Defined Radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: The 6th ACS/IEEE International Conference on Computer Systems and Applications, AICCSA 2008, Doha, Qatar, March 31 - April 4, 2008, pp. 856-859, 2008, IEEE Computer Society, 978-1-4244-1967-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim |
Temperature-Aware Compilation for VLIWProcessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 426-431, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Jürgen Schnerr, Oliver Bringmann 0001, Wolfgang Rosenstiel |
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 792-797, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Giovanni Agosta, Stefano Crespi-Reghizzi, Gerlando Falauto, Martino Sykora |
JIST: Just-in-Time Scheduling Translation for Parallel Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC/HeteroPar ![In: 3rd International Symposium on Parallel and Distributed Computing (ISPDC 2004), 3rd International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogenous Networks (HeteroPar 2004), 5-7 July 2004, Cork, Ireland, pp. 122-132, 2004, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Sunghyun Jee, Kannappan Palaniappan |
Compiler Processor Tradeoffs for DISVLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: International Symposium on Parallel Architectures, Algorithms and Networks, ISPAN 2002, May 22-24, 2002, Makati City, Metro Manila, Philippines, pp. 199-204, 2002, IEEE Computer Society, 0-7695-1579-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Balanced Scheduling, DISVLIW, Processor architecture, ILP |
27 | Mark Oskin, Justin Hensley, Diana Keen, Frederic T. Chong, Matthew K. Farrens, Aneet Chopra |
Exploiting ILP in Page-based Intelligent Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 208-218, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar |
System level design and debug of high-performance embedded media systems (tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 461, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP BibTeX RDF |
|
27 | Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel |
TriMedia CPU64 Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 586-592, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham |
Allocating Lifetimes to Queues in Software Pipelined Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings, pp. 1066-1073, 1997, Springer, 3-540-63440-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
27 | Joseph A. Fisher, Paolo Faraboschi, Giuseppe Desoli |
Custom-fit Processors: Letting Applications Define Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 324-335, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Robert Cohn, Thomas R. Gross, Monica Lam 0001, P. S. Tseng |
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 2-14, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
25 | Wen-Wen Hsieh, TingTing Hwang |
Thermal-aware post compilation for VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 606-611, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Shu Xiao 0001, Edmund Ming-Kit Lai |
A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(4), pp. 1698-1709, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Mattias V. Eriksson, Oskar Skoog, Christoph W. Kessler |
Optimal vs. heuristic integrated code generation for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Proceedings of the 11th International Workshop on Software and Compilers for Embedded Systems, Munich, Germany, March 13-14, 2008, pp. 11-20, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal |
Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 147-160, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli |
Heterogeneous Clustered VLIW Microarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Fifth International Symposium on Code Generation and Optimization (CGO 2007), 11-14 March 2007, San Jose, California, USA, pp. 354-366, 2007, IEEE Computer Society, 978-0-7695-2764-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo |
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 121-124, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Jie Guo 0007, Jun Liu, Björn Mennenga, Gerhard P. Fettweis |
A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007, pp. 346-352, 2007, IEEE Computer Society, 978-1-4244-1026-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda |
Power Reduction in VLIW Processor with Compiler Driven Bypass Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 233-238, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl |
Customizing the Datapath and ISA of Soft VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 276-290, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Thomas Schuster, D. N. Bruna, Bruno Bougard, Veerle Derudder, A. Hoffmann, Liesbet Van der Perre |
Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined Radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 351-356, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen |
Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Pablo Ituero, Marisa López-Vallejo |
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 291-296, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
Distributed Data Cache Designs for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(10), pp. 1227-1241, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
design styles, Single data stream architectures |
25 | Enric Gibert, Jaume Abella 0001, F. Jesús Sánchez, Xavier Vera, Antonio González 0001 |
Variable-Based Multi-module Data Caches for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 17-21 September 2005, St. Louis, MO, USA, pp. 207-217, 2005, IEEE Computer Society, 0-7695-2429-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Edward D. Moreno, Fábio Dacêncio Pereira, Rodolfo B. Chiaramonte |
A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 278, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Domenico Barretta, Gianluca Palermo, Mariagiovanna Sami, Roberto Zafalon |
Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 4-6 July 2005, Palermo, Italy, pp. 265-270, 2005, IEEE Computer Society, 0-7695-2255-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Yanjun Zhang, Hu He 0001, Yihe Sun |
A new register file access architecture for software pipelining in VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 627-630, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Cheng Peng, Zhengting He, Yvonne Cager |
An efficient motion-adaption de-interlacing technique on VLIW DSP architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AVSS ![In: Advanced Video and Signal Based Surveillance, 2005 IEEE International Conference on Video and Signal Based Surveillance (AVSS'05), 15-16 September 2005, Como, Italy., pp. 644-649, 2005, IEEE Computer Society, 0-7803-9385-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke |
Automated data cache placement for embedded VLIW ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 39-44, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cache, ASIP, cache optimization, embedded applications |
25 | Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai |
Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, USA, pp. 81-86, 2005, IEEE Computer Society, 0-7803-9347-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Moonseok Kang, Wonyong Sung |
Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1465-1468, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 32(6), pp. 447-474, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
register requirements, register file organization, clustered organization, Modulo scheduling, spill code |
25 | Nikos Pitsianis, Gerald G. Pechanek |
Indirect VLIW memory allocation for the ManArray multiprocessor DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 31(1), pp. 69-74, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Mark G. Arnold |
A VLIW Architecture for Logarithmic Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 294-303, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word, sum of products, pipeline, Logarithmic Number System |
25 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 193-203, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | James C. Dehnert |
The Transmeta Crusoe: VLIW Embedded in CISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 1, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins |
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 61-70, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Hierarchical Clustered Register File Organization for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 77, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Cornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich |
A High Performance VLIW Processor for Finite Field Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 189, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Davide Rizzo, Osvaldo Colavin |
A Video Compression Case Study on a Reconfigurable VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 540-546, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek |
Improving Code Efficiency for Reconfigurable VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Marco Garatti, Roberto Costa, Stefano Crespi-Reghizzi, Erven Rohou |
The Impact of Alias Analysis on VLIW Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, 4th International Symposium, ISHPC 2002, Kansai Science City, Japan, May 15-17, 2002, Proceedings, pp. 93-105, 2002, Springer, 3-540-43674-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Manvi Agarwal, S. K. Nandy 0001, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan |
Speculative Trace Scheduling in VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 408-413, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Danilo Pau |
SIMD Extension to VLIW Multicluster Processors for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 523-526, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki |
IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (3) ![In: Proceedings of the 2001 International Conference on Image Processing, ICIP 2001, Thessaloniki, Greece, October 7-10, 2001, pp. 294-297, 2001, IEEE, 0-7803-6725-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai |
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 102-113, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Andrea G. M. Cilio, Henk Corporaal |
Code Positioning for VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, 9th International Conference, HPCN Europe 2001, Amsterdam, The Netherlands, June 25-27, 2001, Proceedings, pp. 332-343, 2001, Springer, 3-540-42293-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami |
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 25-27 June 2001, Monterey, CA, USA, pp. 50-57, 2001, IEEE Computer Society, 0-7695-1206-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Chris Basoglu, Woobin Lee, John Setel O'Donnell |
The MAP1000A VLIW Mediaprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(2), pp. 48-59, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Jan Hoogerbrugge |
Dynamic Branch Prediction for a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 207-216, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | L. Louis Zhang, Qiang Wang, David M. Lewis |
Design of a VLIW Compute Accelerator on the Transmogrifier-2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 3-12, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Cagdas Akturan, Margarida F. Jacome |
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000., pp. 34-40, 2000, ACM / IEEE Computer Society, 0-7695-0765-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | F. Jesús Sánchez, Antonio González 0001 |
Instruction Scheduling for Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000., pp. 41-46, 2000, ACM / IEEE Computer Society, 0-7695-0765-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Satish Pillai, Margarida F. Jacome |
Symbolic Binding for Clustered VLIW ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 437-444, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | F. Jesús Sánchez, Antonio González 0001 |
The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the 2000 International Conference on Parallel Processing, ICPP 2000, Toronto, Canada, August 21-24, 2000, pp. 555-564, 2000, IEEE Computer Society, 0-7695-0768-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Paolo Faraboschi, Geoffrey Brown, Joseph A. Fisher, Giuseppe Desoli, Fred Homewood |
Lx: a technology platform for customizable VLIW embedded processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 203-213, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Eric Stotzer, Ernst L. Leiss |
Modulo Scheduling for the TMS320C6x VLIW DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Languages, Compilers, and Tools for Embedded Systems ![In: Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES'99), Atlanta, Georgia, USA, May 5, 1999, pp. 28-34, 1999, ACM, 1-58113-136-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Ronald D. Williams, Brian D. Kuebert |
Reconfigurable Pipelines in VLIW Execution Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 298-299, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
very long instruction word, pipelines, reconfigurable computing |
25 | Shail Aditya, B. Ramakrishna Rau, Vinod Kathail |
Automatic Architectural Synthesis of VLIW and EPIC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 12th International Symposium on System Synthesis, ISSS '99, Boca Raton, Florida, USA, November 1-4, 1999., pp. 107-113, 1999, ACM / IEEE Computer Society, 0-7695-0356-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Craig S. K. Clapp |
Optimizing a Fast Stream Cipher for VLIW, SIMD, and Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSE ![In: Fast Software Encryption, 4th International Workshop, FSE '97, Haifa, Israel, January 20-22, 1997, Proceedings, pp. 273-287, 1997, Springer, 3-540-63247-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Arthur Abnous, Nader Bagherzadeh |
Pipelining and Bypassing in a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(6), pp. 658-664, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
VLIWprocessor, very long instruction word, pipeline data hazards, performance evaluation, performance, parallel architectures, computer architecture, pipeline processing, pipeline structure, bypassing |
25 | Michel Auguin, Fernand Boéri, C. Carrière |
Automatic exploration of VLIW processor architectures from a designer's experience based specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Third International Workshop on Hardware/Software Codesign, CODES 1994, Grenoble, France, September 22-24, 1994, pp. 108-115, 1994, IEEE Computer Society, 0-8186-6315-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
25 | Bogong Su, Jian Wang 0046, Zhizhong Tang, Wei Zhao, Yimin Wu |
A software pipelining based VLIW architecture and optimizing compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 17-27, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
23 | Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala |
Programmable and Scalable Architecture for Graphics Processing Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 2-11, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
TTA, GPU, GPGPU, VLIW, OpenGL, GLSL, LLVM |
23 | Jonah Probell |
Architecture Considerations for Multi-Format Programmable Video Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 50(1), pp. 33-39, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
software programmable processor, hardwired processor, data tiling, SIMD, VLIW, processor architecture, multiprocessing |
23 | Tsung-Han Tsai 0001, Chun-Nan Liu |
A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(3), pp. 323-333, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Prefix grouping, VLIW DSP processor, Multimedia, Parallel processing, Huffman coding |
23 | Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna |
Joint Source-Channel Decoding ASIP Architecture for Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 98-108, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DSC, Sensor Networks, VLIW, ASIP, Turbo Codes, Joint Source-Channel Coding, Factor Graphs |
23 | Jer-Yu Hsu, Yan-Zu Wu, Xuan-Yi Lin, Yeh-Ching Chung |
SCRF - A Hybrid Register File Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 9th International Conference, PaCT 2007, Pereslavl-Zalessky, Russia, September 3-7, 2007, Proceedings, pp. 525-536, 2007, Springer, 978-3-540-73939-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cluster processor architecture, register architecture, register allocation algorithm, VLIW processor |
23 | Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. N. Srikant |
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 238-247, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
interconnect, energy modeling, energy-aware scheduling, clustered VLIW processors |
23 | Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter |
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 229-237, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
VLIW scheduling, code hoisting, predication |
23 | David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan |
Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 34(1), pp. 61-91, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Formal verification, DSP, embedded software, VLIW |
23 | Ivan D. Baev, Richard E. Hank, David H. Gross |
Prematerialization: reducing register pressure for free. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 285-294, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
rematerialization, register allocation, VLIW, Itanium, register pressure |
23 | Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini |
SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 167-172, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping |
23 | Matt T. Yourst, Kanad Ghose |
Incremental Commit Groups for Non-Atomic Trace Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 67-80, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
trace prediction, VLIW, commitment, binary translation |
23 | Andreas Hoffmann 0002, Frank Fiedler, Achim Nohl, Surender Parupalli |
A Methodology and Tooling Enabling Application Specific Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 399-404, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SIMD, VLIW, ASIP |
23 | Binu K. Mathew, Al Davis, Michael A. Parker |
A low power architecture for embedded perception. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 46-56, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
computer vision, embedded systems, speech recognition, perception, low power design, VLIW, stream processor |
23 | Hillery C. Hunter, Jaime H. Moreno |
A new look at exploiting data parallelism in embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 159-169, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
sub-word parallelism, architecture, embedded, DSP, telecommunications, SIMD, VLIW, processor, ILP, media, DLP, data-level parallelism |
23 | Esther Salamí, Jesús Corbal, Carlos Álvarez 0001, Mateo Valero |
Cost effective memory disambiguation for multimedia codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 117-126, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
multimedia, VLIW, run-time analysis, time-to-market, memory disambiguation |
23 | Srihari Cadambi, Chandra Mulpuri, Pranav Ashar |
A fast, inexpensive and scalable hardware acceleration technique for functional simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 570-575, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, hardware acceleration, VLIW, functional simulation |
23 | Josep Llosa, Eduard Ayguadé, Antonio González 0001, Mateo Valero, Jason Eckhardt |
Lifetime-Sensitive Modulo Scheduling in a Production Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(3), pp. 234-249, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
register requirements, software pipelining, VLIW, instruction scheduling, loop scheduling, Fine grain parallelism, superscalar architectures |
23 | Harald P. E. Vranken |
Debug Facilities in the TriMedia CPU64 Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 301-308, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
application debug, VLIW processor, design-for-debug |
23 | John Impagliazzo |
Teaching very large instruction word architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 4th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, ITiCSE 1999, Cracow, Poland, 27-30 June, 1999, pp. 208, 1999, ACM, 1-58113-087-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
architectures, VLIW |
23 | A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans |
TriMedia CPU64 Application Domain and Benchmark Suite. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 580-585, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
TriMedia, multi-media benchmark, design space exploration, embedded processors, VLIW processors, media processing |
23 | Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte |
Value Speculation Scheduling for High Performance Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 262-271, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VLIW instruction schedulings, instruction level parallelism, value prediction, value speculation |
23 | Soo-Mook Moon, Kemal Ebcioglu |
Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 19(6), pp. 853-898, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar |
23 | F. Jesús Sánchez, Antonio González 0001 |
Cache Sensitive Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 338-348, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
VLIW machines, Software pipelining, software prefetching, locality analysis |
23 | Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith |
MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 330-335, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
MediaBench, SPEC benchmark suite, benchmark suite, compilation technology, experimental measurement, general-purpose computing, general-purpose systems, inner-loops, optimization, multimedia systems, instruction-level parallelism, SIMD, VLIW, communications systems, embedded applications, microprocessor architectures |
23 | W. Lynn Gallagher, Chuan-lin Wu |
Evaluation of a memory hierarchy for the MTS multithreaded processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 11-13 December 1997, Seoul, Korea, Proceedings, pp. 346-351, 1997, IEEE Computer Society, 0-8186-8227-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache |
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