Search results for "VLIW"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Rafail Psiakis	Performance Optimization Mechanisms for Fault-Resilient VLIW Processors. (Mécanismes d'optimisation des performances des processeurs VLIW à tolérance de fautes).		2018	RDF
30	Thorsten Jungeblut, Gregor Sievers, Mario Porrmann, Ulrich Rückert 0001	Design Space Exploration for Memory Subsystems of VLIW Architectures.	NAS	2010	DBLP DOI BibTeX RDF	CoreVA, Cache, Design Space Exploration, VLIW, Memory Subsystem
30	Dimitris Theodoropoulos, Alexandros Siskos, Dionisios N. Pnevmatikatos	CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers.	ARC	2009	DBLP DOI BibTeX RDF	Cryptography, VLIW, reconfigurable processors
30	Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck	Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	RISC/CISC, low-power design, memory management, real-time and embedded systems, VLIW architectures, memory design
30	Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy	VLIW: a case study of parallelism verification.	DAC	2005	DBLP DOI BibTeX RDF	parallelism, test generation, VLIW, functional verification, processor verification
30	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon	Exploiting data forwarding to reduce the power budget of VLIW embedded processors.	DATE	2001	DBLP DOI BibTeX RDF	VLIW embedded architectures, low-power, pipeline processors, forwarding
30	David López 0001, Josep Llosa, Eduard Ayguadé, Mateo Valero	Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures.	ICPP	1999	DBLP DOI BibTeX RDF	ILP limits, multiply-add fused, performance/cost evaluation, software pipelining, VLIW architectures, numerical code
30	Zhao Wu, Wayne H. Wolf	Trace-Driven Studies of VLIW Video Signal Processors.	SPAA	1998	DBLP DOI BibTeX RDF	VSP, trace-driven scheduling, parallelism, parallel architecture, MPEG, VLIW, media processor, video applications
30	Soo-Mook Moon, Kemal Ebcioglu	Performance Analysis of Tree VLIW Architecture for Exploiting Branch ILP in Non-Numerical Code.	International Conference on Supercomputing	1997	DBLP DOI BibTeX RDF	branch code motion, generalized multiway braching, speculative code motion, tree VLIW architecture, conditional execution
30	B. Ramakrishna Rau	Dynamically scheduled VLIW processors.	MICRO	1993	DBLP DOI BibTeX RDF	multiple operation issue, scoreboarding, dynamic scheduling, out-of-order execution, VLIW processors
30	Soo-Mook Moon, Kemal Ebcioglu	An efficient resource-constrained global scheduling technique for superscalar and VLIW processors.	MICRO	1992	DBLP DOI BibTeX RDF	compile-time parallelization, instruction-level parallelism, VLIW, superscalar
27	Xing Fang, Dong Wang, Shuming Chen	SPVA: A novel digital signal processor architecture for Software Defined Radio.	AICCSA	2008	DBLP DOI BibTeX RDF
27	Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim	Temperature-Aware Compilation for VLIWProcessors.	RTCSA	2007	DBLP DOI BibTeX RDF
27	Jürgen Schnerr, Oliver Bringmann 0001, Wolfgang Rosenstiel	Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs.	DATE	2005	DBLP DOI BibTeX RDF
27	Giovanni Agosta, Stefano Crespi-Reghizzi, Gerlando Falauto, Martino Sykora	JIST: Just-in-Time Scheduling Translation for Parallel Processors.	ISPDC/HeteroPar	2004	DBLP DOI BibTeX RDF
27	Sunghyun Jee, Kannappan Palaniappan	Compiler Processor Tradeoffs for DISVLIW Architecture.	ISPAN	2002	DBLP DOI BibTeX RDF	Balanced Scheduling, DISVLIW, Processor architecture, ILP
27	Mark Oskin, Justin Hensley, Diana Keen, Frederic T. Chong, Matthew K. Farrens, Aneet Chopra	Exploiting ILP in Page-based Intelligent Memory.	MICRO	1999	DBLP DOI BibTeX RDF
27	Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar	System level design and debug of high-performance embedded media systems (tutorial).	ICCAD	1999	DBLP BibTeX RDF
27	Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel	TriMedia CPU64 Architecture.	ICCD	1999	DBLP DOI BibTeX RDF
27	Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham	Allocating Lifetimes to Queues in Software Pipelined Architectures.	Euro-Par	1997	DBLP DOI BibTeX RDF
27	Joseph A. Fisher, Paolo Faraboschi, Giuseppe Desoli	Custom-fit Processors: Letting Applications Define Architectures.	MICRO	1996	DBLP DOI BibTeX RDF
27	Robert Cohn, Thomas R. Gross, Monica Lam 0001, P. S. Tseng	Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor.	ASPLOS	1989	DBLP DOI BibTeX RDF
25	Wen-Wen Hsieh, TingTing Hwang	Thermal-aware post compilation for VLIW architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
25	Shu Xiao 0001, Edmund Ming-Kit Lai	A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
25	Mattias V. Eriksson, Oskar Skoog, Christoph W. Kessler	Optimal vs. heuristic integrated code generation for clustered VLIW architectures.	SCOPES	2008	DBLP DOI BibTeX RDF
25	Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal	Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.	HiPEAC	2008	DBLP DOI BibTeX RDF
25	Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli	Heterogeneous Clustered VLIW Microarchitectures.	CGO	2007	DBLP DOI BibTeX RDF
25	Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo	Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Jie Guo 0007, Jun Liu, Björn Mennenga, Gerhard P. Fettweis	A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation.	ASAP	2007	DBLP DOI BibTeX RDF
25	Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda	Power Reduction in VLIW Processor with Compiler Driven Bypass Network.	VLSI Design	2007	DBLP DOI BibTeX RDF
25	Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl	Customizing the Datapath and ISA of Soft VLIW Processors.	HiPEAC	2007	DBLP DOI BibTeX RDF
25	Thomas Schuster, D. N. Bruna, Bruno Bougard, Veerle Derudder, A. Hoffmann, Liesbet Van der Perre	Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined Radio.	SiPS	2006	DBLP DOI BibTeX RDF
25	Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen	Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Pablo Ituero, Marisa López-Vallejo	New Schemes in Clustered VLIW Processors Applied to Turbo Decoding.	ASAP	2006	DBLP DOI BibTeX RDF
25	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Distributed Data Cache Designs for Clustered VLIW Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	design styles, Single data stream architectures
25	Enric Gibert, Jaume Abella 0001, F. Jesús Sánchez, Xavier Vera, Antonio González 0001	Variable-Based Multi-module Data Caches for Clustered VLIW Processors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
25	Edward D. Moreno, Fábio Dacêncio Pereira, Rodolfo B. Chiaramonte	A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
25	Domenico Barretta, Gianluca Palermo, Mariagiovanna Sami, Roberto Zafalon	Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor.	CAMP	2005	DBLP DOI BibTeX RDF
25	Yanjun Zhang, Hu He 0001, Yihe Sun	A new register file access architecture for software pipelining in VLIW processors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
25	Cheng Peng, Zhengting He, Yvonne Cager	An efficient motion-adaption de-interlacing technique on VLIW DSP architecture.	AVSS	2005	DBLP DOI BibTeX RDF
25	Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke	Automated data cache placement for embedded VLIW ASIPs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	cache, ASIP, cache optimization, embedded applications
25	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.	ESTIMedia	2005	DBLP DOI BibTeX RDF
25	Moonseok Kang, Wonyong Sung	Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processor.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
25	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.	Int. J. Parallel Program.	2004	DBLP DOI BibTeX RDF	register requirements, register file organization, clustered organization, Modulo scheduling, spill code
25	Nikos Pitsianis, Gerald G. Pechanek	Indirect VLIW memory allocation for the ManArray multiprocessor DSP.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF
25	Mark G. Arnold	A VLIW Architecture for Logarithmic Arithmetic.	DSD	2003	DBLP DOI BibTeX RDF	Very Long Instruction Word, sum of products, pipeline, Logarithmic Number System
25	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache.	CGO	2003	DBLP DOI BibTeX RDF
25	James C. Dehnert	The Transmeta Crusoe: VLIW Embedded in CISC.	SCOPES	2003	DBLP DOI BibTeX RDF
25	Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins	ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.	FPL	2003	DBLP DOI BibTeX RDF
25	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Hierarchical Clustered Register File Organization for VLIW Processors.	IPDPS	2003	DBLP DOI BibTeX RDF
25	Cornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich	A High Performance VLIW Processor for Finite Field Arithmetic.	IPDPS	2003	DBLP DOI BibTeX RDF
25	Davide Rizzo, Osvaldo Colavin	A Video Compression Case Study on a Reconfigurable VLIW Architecture.	DATE	2002	DBLP DOI BibTeX RDF
25	Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek	Improving Code Efficiency for Reconfigurable VLIW Processors.	IPDPS	2002	DBLP DOI BibTeX RDF
25	Marco Garatti, Roberto Costa, Stefano Crespi-Reghizzi, Erven Rohou	The Impact of Alias Analysis on VLIW Scheduling.	ISHPC	2002	DBLP DOI BibTeX RDF
25	Manvi Agarwal, S. K. Nandy 0001, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan	Speculative Trace Scheduling in VLIW Processors.	ICCD	2002	DBLP DOI BibTeX RDF
25	Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Danilo Pau	SIMD Extension to VLIW Multicluster Processors for Embedded Applications.	ICCD	2002	DBLP DOI BibTeX RDF
25	Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki	IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements.	ICIP (3)	2001	DBLP DOI BibTeX RDF
25	Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai	Exploiting VLIW schedule slacks for dynamic and leakage energy reduction.	MICRO	2001	DBLP DOI BibTeX RDF
25	Andrea G. M. Cilio, Henk Corporaal	Code Positioning for VLIW Architectures.	HPCN	2001	DBLP DOI BibTeX RDF
25	Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami	Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
25	Chris Basoglu, Woobin Lee, John Setel O'Donnell	The MAP1000A VLIW Mediaprocessor.	IEEE Micro	2000	DBLP DOI BibTeX RDF
25	Jan Hoogerbrugge	Dynamic Branch Prediction for a VLIW Processor.	IEEE PACT	2000	DBLP DOI BibTeX RDF
25	L. Louis Zhang, Qiang Wang, David M. Lewis	Design of a VLIW Compute Accelerator on the Transmogrifier-2.	FCCM	2000	DBLP DOI BibTeX RDF
25	Cagdas Akturan, Margarida F. Jacome	FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors.	ISSS	2000	DBLP DOI BibTeX RDF
25	F. Jesús Sánchez, Antonio González 0001	Instruction Scheduling for Clustered VLIW Architectures.	ISSS	2000	DBLP DOI BibTeX RDF
25	Satish Pillai, Margarida F. Jacome	Symbolic Binding for Clustered VLIW ASIPs.	ICCD	2000	DBLP DOI BibTeX RDF
25	F. Jesús Sánchez, Antonio González 0001	The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures.	ICPP	2000	DBLP DOI BibTeX RDF
25	Paolo Faraboschi, Geoffrey Brown, Joseph A. Fisher, Giuseppe Desoli, Fred Homewood	Lx: a technology platform for customizable VLIW embedded processing.	ISCA	2000	DBLP DOI BibTeX RDF
25	Eric Stotzer, Ernst L. Leiss	Modulo Scheduling for the TMS320C6x VLIW DSP Architecture.	Workshop on Languages, Compilers, and Tools for Embedded Systems	1999	DBLP DOI BibTeX RDF
25	Ronald D. Williams, Brian D. Kuebert	Reconfigurable Pipelines in VLIW Execution Units.	FCCM	1999	DBLP DOI BibTeX RDF	very long instruction word, pipelines, reconfigurable computing
25	Shail Aditya, B. Ramakrishna Rau, Vinod Kathail	Automatic Architectural Synthesis of VLIW and EPIC Processors.	ISSS	1999	DBLP DOI BibTeX RDF
25	Craig S. K. Clapp	Optimizing a Fast Stream Cipher for VLIW, SIMD, and Superscalar Processors.	FSE	1997	DBLP DOI BibTeX RDF
25	Arthur Abnous, Nader Bagherzadeh	Pipelining and Bypassing in a VLIW Processor.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	VLIWprocessor, very long instruction word, pipeline data hazards, performance evaluation, performance, parallel architectures, computer architecture, pipeline processing, pipeline structure, bypassing
25	Michel Auguin, Fernand Boéri, C. Carrière	Automatic exploration of VLIW processor architectures from a designer's experience based specification.	CODES	1994	DBLP DOI BibTeX RDF
25	Bogong Su, Jian Wang 0046, Zhizhong Tang, Wei Zhao, Yimin Wu	A software pipelining based VLIW architecture and optimizing compiler.	MICRO	1990	DBLP BibTeX RDF
23	Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala	Programmable and Scalable Architecture for Graphics Processing Units.	SAMOS	2009	DBLP DOI BibTeX RDF	TTA, GPU, GPGPU, VLIW, OpenGL, GLSL, LLVM
23	Jonah Probell	Architecture Considerations for Multi-Format Programmable Video Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	software programmable processor, hardwired processor, data tiling, SIMD, VLIW, processor architecture, multiprocessing
23	Tsung-Han Tsai 0001, Chun-Nan Liu	A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	Prefix grouping, VLIW DSP processor, Multimedia, Parallel processing, Huffman coding
23	Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna	Joint Source-Channel Decoding ASIP Architecture for Sensor Networks.	ICESS	2007	DBLP DOI BibTeX RDF	DSC, Sensor Networks, VLIW, ASIP, Turbo Codes, Joint Source-Channel Coding, Factor Graphs
23	Jer-Yu Hsu, Yan-Zu Wu, Xuan-Yi Lin, Yeh-Ching Chung	SCRF - A Hybrid Register File Architecture.	PaCT	2007	DBLP DOI BibTeX RDF	cluster processor architecture, register architecture, register allocation algorithm, VLIW processor
23	Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. N. Srikant	INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations.	CASES	2007	DBLP DOI BibTeX RDF	interconnect, energy modeling, energy-aware scheduling, clustered VLIW processors
23	Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter	A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots.	CASES	2007	DBLP DOI BibTeX RDF	VLIW scheduling, code hoisting, predication
23	David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan	Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	Formal verification, DSP, embedded software, VLIW
23	Ivan D. Baev, Richard E. Hank, David H. Gross	Prematerialization: reducing register pressure for free.	PACT	2006	DBLP DOI BibTeX RDF	rematerialization, register allocation, VLIW, Itanium, register pressure
23	Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini	SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping
23	Matt T. Yourst, Kanad Ghose	Incremental Commit Groups for Non-Atomic Trace Processing.	MICRO	2005	DBLP DOI BibTeX RDF	trace prediction, VLIW, commitment, binary translation
23	Andreas Hoffmann 0002, Frank Fiedler, Achim Nohl, Surender Parupalli	A Methodology and Tooling Enabling Application Specific Processor Design.	VLSI Design	2005	DBLP DOI BibTeX RDF	SIMD, VLIW, ASIP
23	Binu K. Mathew, Al Davis, Michael A. Parker	A low power architecture for embedded perception.	CASES	2004	DBLP DOI BibTeX RDF	computer vision, embedded systems, speech recognition, perception, low power design, VLIW, stream processor
23	Hillery C. Hunter, Jaime H. Moreno	A new look at exploiting data parallelism in embedded systems.	CASES	2003	DBLP DOI BibTeX RDF	sub-word parallelism, architecture, embedded, DSP, telecommunications, SIMD, VLIW, processor, ILP, media, DLP, data-level parallelism
23	Esther Salamí, Jesús Corbal, Carlos Álvarez 0001, Mateo Valero	Cost effective memory disambiguation for multimedia codes.	CASES	2002	DBLP DOI BibTeX RDF	multimedia, VLIW, run-time analysis, time-to-market, memory disambiguation
23	Srihari Cadambi, Chandra Mulpuri, Pranav Ashar	A fast, inexpensive and scalable hardware acceleration technique for functional simulation.	DAC	2002	DBLP DOI BibTeX RDF	FPGA, hardware acceleration, VLIW, functional simulation
23	Josep Llosa, Eduard Ayguadé, Antonio González 0001, Mateo Valero, Jason Eckhardt	Lifetime-Sensitive Modulo Scheduling in a Production Environment.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	register requirements, software pipelining, VLIW, instruction scheduling, loop scheduling, Fine grain parallelism, superscalar architectures
23	Harald P. E. Vranken	Debug Facilities in the TriMedia CPU64 Architecture.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	application debug, VLIW processor, design-for-debug
23	John Impagliazzo	Teaching very large instruction word architectures.	ITiCSE	1999	DBLP DOI BibTeX RDF	architectures, VLIW
23	A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans	TriMedia CPU64 Application Domain and Benchmark Suite.	ICCD	1999	DBLP DOI BibTeX RDF	TriMedia, multi-media benchmark, design space exploration, embedded processors, VLIW processors, media processing
23	Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte	Value Speculation Scheduling for High Performance Processors.	ASPLOS	1998	DBLP DOI BibTeX RDF	VLIW instruction schedulings, instruction level parallelism, value prediction, value speculation
23	Soo-Mook Moon, Kemal Ebcioglu	Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar
23	F. Jesús Sánchez, Antonio González 0001	Cache Sensitive Modulo Scheduling.	MICRO	1997	DBLP DOI BibTeX RDF	VLIW machines, Software pipelining, software prefetching, locality analysis
23	Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith	MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems.	MICRO	1997	DBLP DOI BibTeX RDF	MediaBench, SPEC benchmark suite, benchmark suite, compilation technology, experimental measurement, general-purpose computing, general-purpose systems, inner-loops, optimization, multimedia systems, instruction-level parallelism, SIMD, VLIW, communications systems, embedded applications, microprocessor architectures
23	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor.	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache