Search results for "adders"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Kavish Seth, K. N. Viswajith, S. Srinivasan 0001, V. Kamakoti 0001	Ultra Folded High-Speed Architectures for Reed-Solomon Decoders.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Oscar Gustafsson, Kenny Johansson, Håkan Johansson, Lars Wanhammar	Implementation of Polyphase Decomposed FIR Filters for Interpolation and Decimation Using Multiple Constant Multiplication Techniques.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang	A review of 0.18-μm full adder performances for tree structured arithmetic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
18	Neil Burgess	New Models of Prefix Adder Topologies.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	prefix addition, absolute difference, VLSI, delay model, idempotency
18	Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar	Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.	PATMOS	2005	DBLP DOI BibTeX RDF
18	Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet	Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures.	IWANN	2005	DBLP DOI BibTeX RDF
18	Ji-Xue Xiao, Guang-Ju Chen, Yong-Le Xie	Arithmetic Test Strategy for FFT Processor.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
18	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Implementation of low-complexity FIR filters using serial arithmetic.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
18	Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan	A configurable dual moduli multi-operand modulo adder.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
18	Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro 0001, Sergio Bampi	An improved synthesis method for low power hardwired FIR filters.	SBCCI	2004	DBLP DOI BibTeX RDF	FPGA synthesis, parallel FIR filter, power-of-two, common subexpression elimination
18	Ge Yang 0004, Zhongda Wang, Sung-Mo Kang	Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
18	Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu	Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division
18	T. Sansaloni, Javier Valls, Keshab K. Parhi	Digit-Serial Complex-Number Multipliers on FPGAs.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding
18	Peter Celinski, Sorin Cotofana, Derek Abbott	A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder.	IWANN (2)	2003	DBLP DOI BibTeX RDF
18	Kay-Chuan Benny Tan, Tughrul Arslan	Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	Ya Jun Yu, Tapio Saramäki, Yong Ching Lim	An iterative method for optimizing FIR filters synthesized using the two-stage frequency-response masking technique.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
18	Shugang Wei, Kensuke Shimizu	Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang	A low-power adder operating on effective dynamic data ranges.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
18	George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis	Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations.	FPL	2002	DBLP DOI BibTeX RDF
18	Zhiyuan Yan, Dilip V. Sarwate	Systolic architectures for finite field inversion and division.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
18	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López	Low depth carry lookahead addition using charge recycling threshold logic.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
18	Shugang Wei, Shuangching Chen, Kensuke Shimizu	Fast modular multiplication using Booth recoding based on signed-digit number arithmetic.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
18	Suhwan Kim, Marios C. Papaefthymiou	True single-phase adiabatic circuitry.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
18	Ernest Jamro, Kazimierz Wiatr	Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution.	DSD	2001	DBLP DOI BibTeX RDF
18	Andrew Beaumont-Smith, Cheng-Chew Lim	Parallel Prefix Adder Design.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
18	Trevor W. Fox, Laurence E. Turner	The design of peak constrained least squares FIR filters with low complexity finite precision coefficients.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
18	Tapio Saramäki, Håkan Johansson	Optimization of FIR filters using the frequency-response masking approach.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
18	Henrik Ohlsson, Oscar Gustafsson, Lars Wanhammar	Arithmetic transformations for increased maximal sample rate of bit-parallel bireciprocal lattice wave digital filters.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
18	Johnny Holmberg, Lennart Harnefors, Krister Landernäs, Svante Signell	Computational properties of LDI/LDD lattice filters.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
18	Matthew M. Ziegler, Mircea Stan	Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
18	Li-Hsun Chen, Oscal T.-C. Chen	A low-complexity and high-speed Booth-algorithm FIR architecture.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
18	Parag K. Lala, Alvernon Walker	On-Line Error Detectable Carry-Free Adder Design.	DFT	2001	DBLP DOI BibTeX RDF	carry-free adder, signed binary digits, 1-out-of-3 code, on-line error detection
18	Albrecht P. Stroele, Steffen Tarnick	Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	code checkers, code word accumulators, code word generators, embedded checkers, cyclic arithmetic codes, low-cost arithmetic codes, built-in self-test, on-line test, totally self-checking checkers
18	Manish Goel, Naresh R. Shanbhag	Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
18	Wen-Shiaw Peng, Chen-Yi Lee	An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform.	ICIP (2)	1999	DBLP DOI BibTeX RDF
18	Khurram Muhammad, Kaushik Roy 0001	A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters.	ISSS	1999	DBLP DOI BibTeX RDF
18	Elena Dubrova	Evaluation of m-Valued Fixed Polarity Generalizations of Reed-Muller Canonical Form.	ISMVL	1999	DBLP DOI BibTeX RDF	Reed-Muller canonical form, fixed polarity, multiple-valued function
18	Miguel A. Sacristán, María Victoria Rodellar Biarge, Antonio Diaz, V. Garcia, Pedro Gómez 0001	A Reusable Inner Product Unit for DSP Applications.	EUROMICRO	1999	DBLP DOI BibTeX RDF
18	Stanislaw J. Piestrak	Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	counters of 1s, m-out-of-n (m/n) codes, concurrent error detection, on-line testing, self-checking circuit, unidirectional errors, parallel counters, unordered codes, self-testing checker
18	Suhwan Kim, Marios C. Papaefthymiou	True single-phase energy-recovering logic for low-power, high-speed VLSI.	ISLPED	1998	DBLP DOI BibTeX RDF
18	Gareth Keane, Jonathan R. Spanier, Roger F. Woods	The impact of data characteristics and hardware topology on hardware selection for low power DSP.	ISLPED	1998	DBLP DOI BibTeX RDF
18	Steffen Tarnick, Albrecht P. Stroele	Embedded self-testing checkers for low-cost arithmetic codes.	ITC	1998	DBLP DOI BibTeX RDF
18	Albrecht P. Stroele	BIST Pattern Generators Using Addition and Subtraction Operations.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	built-in self-test, adder, accumulator, pattern generator, subtracter
18	Gianluca Cena, Paolo Montuschi, Luigi Ciminiera, Andrea Sanna	A Q-Coder Algorithm with Carry Free Addition.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	image compression, arithmetic coding
18	Deepak Kapur, Mahadevan Subramaniam	Mechanizing Verification of Arithmetic Circuits: SRT Division.	FSTTCS	1997	DBLP DOI BibTeX RDF
18	Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin	Some Issues in Gray Code Addressing.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
18	Charles U. Martel, Vojin G. Oklobdzija, R. Ravi 0001, Paul F. Stelling	Design Strategies for Optimal Multiplier Circuits.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	Algorithms, Circuit design, Partial product reduction, Multiplier design
18	Luca Breveglieri, Luigi Dadda, Vincenzo Piuri	Column Compression Pipelined Multipliers.	ASAP	1995	DBLP DOI BibTeX RDF	pipelining, computer arithmetic, multipliers
18	Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi	A C-testable carry-free divider.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
18	Daniel Etiemble, Keivan Navi	Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
18	Rong Lin, Stephan Olariu	Computing the Inner Product on Reconfigurable Buses with Shift Switching.	CONPAR	1992	DBLP DOI BibTeX RDF
18	Andres R. Takach, Niraj K. Jha	Easily testable gate-level and DCVS multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
18	Mary Jane Irwin, Robert Michael Owens	A case for digit serial VLSI signal processors.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF
18	Jagan P. Agrawal, V. Umapathi Reddy	Log-sum multiplier.	AFIPS National Computer Conference	1976	DBLP DOI BibTeX RDF
16	Khadijeh Moeini Roodbali, Ebrahim Abiri, Kourosh Hassanli	Highly efficient low-area gate-diffusion-input-based approximate full adders for image processing computing.	J. Supercomput.	2024	DBLP DOI BibTeX RDF
16	Marcelo Tosini, Martín Vázquez 0001, Lucas Leiva	Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding.	J. Supercomput.	2024	DBLP DOI BibTeX RDF
16	Aiman Malik, Md. Shahbaz Hussain, Mohd. Hasan	Energy-Efficient Exact and Approximate CNTFET-Based Ternary Full Adders.	Circuits Syst. Signal Process.	2024	DBLP DOI BibTeX RDF
16	Parthiv Bhau, Vijay Savani	Design and Analysis of Low-Voltage and Low-Power 19T FinFET-TGDI-Based Hybrid Full Adders.	J. Circuits Syst. Comput.	2024	DBLP DOI BibTeX RDF
16	Maxime Remaud	Quantum Ripple-Carry Adders and Comparator.	CoRR	2024	DBLP DOI BibTeX RDF
16	Chandan Kumar Jha 0001, Sallar Ahmadi-Pour, Rolf Drechsler	Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic.	VLSID	2024	DBLP DOI BibTeX RDF
16	Vishesh Mishra, Sparsh Mittal, Nirbhay Mishra, Rekha Singhal	Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers.	VLSID	2024	DBLP DOI BibTeX RDF
16	Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri	Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits.	Frontiers Inf. Technol. Electron. Eng.	2023	DBLP DOI BibTeX RDF
16	R. Jothin, C. Vasanthanayaki, P. Sreelatha, M. Peer Mohamed	Comparison and extension of high performance adders for hybrid and error tolerant applications.	J. Ambient Intell. Humaniz. Comput.	2023	DBLP DOI BibTeX RDF
16	Morgana Macedo Azevedo da Rosa, Guilherme Paim, Patrícia Ücker Leleu da Costa, Eduardo Antonio Cesar da Costa, Rafael Iankowski Soares, Sergio Bampi	AxPPA: Approximate Parallel Prefix Adders.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Apostolos Stefanidis, Ioanna Zoumpoulidou, Dionysios Filippas, Giorgos Dimitrakopoulos, Georgios Ch. Sirakoulis	Synthesis of Approximate Parallel-Prefix Adders.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Hyoju Seo, Yongtae Kim	A Low Latency Approximate Adder Design Based on Dual Sub-Adders With Error Recovery.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
16	Kleanthis Papachatzopoulos, Vassilis Paliouras	Path-Based Delay Variation Models for Parallel-Prefix Adders.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
16	Tresa Joseph, T. S. Bindiya	Power and Delay-Efficient Matrix Vector Multiplier Units for the LSTM Networks Using Activity Span Reduction Technique and Recursive Adders.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
16	Anubhav Anand, Satyam Singh, Sandeep Dhariwal, Reeba Korah, Gaurav Kumar	Low Power Full Adders based on Proposed Hybrid and GDI Designs: A Novel Approach.	Int. J. Perform. Eng.	2023	DBLP DOI BibTeX RDF
16	Sarina Nemati, Mostafa Haghi Kashani, Reza Faghih Mirzaee	Comprehensive survey of ternary full adders: Statistics, corrections, and assessments.	IET Circuits Devices Syst.	2023	DBLP DOI BibTeX RDF
16	Nabiollah Shiri, Ayoub Sadeghi, Mahmood Rafiee	High-efficient and error-resilient gate diffusion input-based approximate full adders for complex multistage rapid structures.	Comput. Electr. Eng.	2023	DBLP DOI BibTeX RDF
16	Farshid Ahmadi, Mohammad R. Semati, Hassan Daryanavard, Atefeh Minaeifar	Energy-efficient approximate full adders for error-tolerant applications.	Comput. Electr. Eng.	2023	DBLP DOI BibTeX RDF
16	Muhammad Abdullah Hanif, Rehan Hafiz, Muhammad Shafique 0001	DAEM: A Data- and Application-Aware Error Analysis Methodology for Approximate Adders.	Inf.	2023	DBLP DOI BibTeX RDF
16	Martin Kumm, Anastasia Volkova, Silviu-Ioan Filip	Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
16	Ebrahim Farahmand, Ali Mahani 0001, Muhammad Abdullah Hanif, Muhammad Shafique 0001	Design and Analysis of High Performance Heterogeneous Block-based Approximate Adders.	ACM Trans. Embed. Comput. Syst.	2023	DBLP DOI BibTeX RDF
16	Farhad Ebrahimi-Azandaryani, Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram	Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
16	Jiawen Cheng, Yong Xiao, Yun Shao 0008, Guanghai Dong, Songlin Lyu, Wenjian Yu	Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
16	Mantas Mikaitis	Monotonicity of Multi-Term Floating-Point Adders.	CoRR	2023	DBLP DOI BibTeX RDF
16	Rajat Bhattacharjya, Biswadip Maity, Nikil D. Dutt	Locate: Low-Power Viterbi Decoder Exploration using Approximate Adders.	CoRR	2023	DBLP DOI BibTeX RDF
16	Seyed Erfan Fatemieh, Mohammad Reza Reshadinezhad, Nima TaheriNejad	Fast and Compact Serial IMPLY-Based Approximate Full Adders Applied in Image Processing.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2023	DBLP DOI BibTeX RDF
16	Hilal A. Bhat, Farooq Ahmad Khanday, Brajesh Kumar Kaushik	Optimized quantum implementation of novel controlled adders/subtractors.	Quantum Inf. Process.	2023	DBLP DOI BibTeX RDF
16	M. Priyadharshni, Kishore Sanapala, Polinpapilinho F. Katina, K. Prasanna Kumar	Image analysis in healthcare systems using approximate multi-bit adders.	Int. J. Syst. Syst. Eng.	2023	DBLP DOI BibTeX RDF
16	Prasanna Kumar K., M. Priyadharshni, Kishore Sanapala, Polinpapilinho F. Katina	Image analysis in healthcare systems using approximate multi-bit adders.	Int. J. Syst. Syst. Eng.	2023	DBLP DOI BibTeX RDF
16	Deepthi Amuru, Andleeb Zahra, Varnika Karakuram, Zia Abbas	Design of Approximate Full Adders for Error Resilient Applications.	ICCA	2023	DBLP DOI BibTeX RDF
16	Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler	Polynomial Formal Verification of Floating Point Adders.	DATE	2023	DBLP DOI BibTeX RDF
16	Timothy J. Baker, John P. Hayes	Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior.	DATE	2023	DBLP DOI BibTeX RDF
16	Bogdan Pasca 0001, Martin Langhammer	Extracting low-precision floating-point adders from embedded hard FP DSP Blocks on FPGAs.	ARITH	2023	DBLP DOI BibTeX RDF
16	Shadman Shahriar, A. B. M. Alim Al Islam	Extending Shor's Quantum Error Correction Circuits Using Quantum Adders.	GLOBECOM	2023	DBLP DOI BibTeX RDF
16	Moola Vamsi Krishna Reddy, Nusum Raja Sekhar Reddy, Pinnepalli Naveen Kumar, Ramireddy Praneeth Kumar Reddy, Sarada Musala, Avireni Srinivasulu	Modified Low Power High Speed Approximate Adders For Energy Efficient Arithmetic Applications.	ECAI	2023	DBLP DOI BibTeX RDF
16	Alexander Lehnert, Hans Rosenberger, Ralf R. Müller, Marc Reichenbach	More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding.	ARC	2023	DBLP DOI BibTeX RDF
16	Sercan Aygun, M. Hassan Najafi, Lida Kouhalvandi, Ece Olcay Günes	Multiplexer Optimization for Adders in Stochastic Computing.	NANOARCH	2023	DBLP DOI BibTeX RDF
16	Rounak Roy, Sudip Ghosh 0001, Hafizur Rahaman 0001	Implementation of Area Efficient Adders for Inexact Computing.	ISDCS	2023	DBLP DOI BibTeX RDF
16	Aibin Yan, Shaojie Wei, Zhixing Li, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen	Design of Low-Cost Approximate CMOS Full Adders.	ISCAS	2023	DBLP DOI BibTeX RDF
16	Mineo Kaneko	Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders.	ISCAS	2023	DBLP DOI BibTeX RDF
16	Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis	Detecting Hardware Faults in Approximate Adders via Minimum Redundancy.	IOLTS	2023	DBLP DOI BibTeX RDF
16	Bhaskar Gaur, Travis S. Humble, Himanshu Thapliyal	Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
16	Rajat Bhattacharjya, Biswadip Maity, Nikil D. Dutt	Locate: Low-Power Viterbi Decoder Exploration using Approximate Adders.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
16	Archie Mishra, Nanditha Rao	DSEAdd: FPGA based Design Space Exploration for Approximate Adders with Variable Bit-precision.	ISQED	2023	DBLP DOI BibTeX RDF
16	Hyoju Seo, Seokhyeon Lee, Yongtae Kim	Computation Exactness Exploration of Exact Quantum Adders in NISQ.	ISOCC	2023	DBLP DOI BibTeX RDF
16	P. Kishore, Nagalaxmi Thaduru, K. Kalyana Srinivas	Design of High Performance Adders Using Quantum Dot Cellular Automata (QCA).	ICCCNT	2023	DBLP DOI BibTeX RDF