Search results for "body-biasing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
14	Meikang Qiu, Laurence Tianruo Yang, Edwin Hsing-Mean Sha	Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC.	CSE (2)	2009	DBLP DOI BibTeX RDF
14	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware sleep transistor design for reliable power-gating.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reliability, sizing, sleep-transistor, nbti
14	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
14	Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy 0001	NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Analysis and minimization of practical energy in 45nm subthreshold logic circuits.	ICCD	2008	DBLP DOI BibTeX RDF
14	Swarup Bhunia, Kaushik Roy 0001	Low power design under parameter variations.	SoCC	2008	DBLP DOI BibTeX RDF
14	Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown	On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.	ISQED	2008	DBLP DOI BibTeX RDF
14	Po-Kuan Huang, Soheil Ghiasi	Efficient and scalable compiler-directed energy optimization for realtime applications.	DATE	2007	DBLP DOI BibTeX RDF
14	Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail	Modeling and Characterizing Power Variability in Multicore Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	mal-fabricated chip, VariPower, project power variability, microarchitectural block, power variability characterization, statistical analysis, multicore processor, multicore architecture, technology scaling, parameter variation, SPICE simulation
14	Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi	Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Akepati Sravan, Sujan Kundu, Ajit Pal	Low Power Sensor Node for a Wireless Sensor Network.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi	Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
14	Po-Kuan Huang, Soheil Ghiasi	Leakage-aware intraprogram voltage scaling for embedded processors.	DAC	2006	DBLP DOI BibTeX RDF
14	Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001	A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
14	M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang 0001, David H. Albonesi	Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance.	IEEE PACT	2005	DBLP DOI BibTeX RDF
14	Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi	Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints.	DATE	2005	DBLP DOI BibTeX RDF
14	Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles	Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction.	DSD	2005	DBLP DOI BibTeX RDF
14	Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy 0001	A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.	IOLTS	2005	DBLP DOI BibTeX RDF	Speed binning, delay measurement hardware, process variation
14	Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin	Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty.	VLSI Design	2005	DBLP DOI BibTeX RDF
14	Stefan Cserveny, Jean-Marc Masgonty, Christian Piguet	Noise Margin in Low Power SRAM Cells.	PATMOS	2004	DBLP DOI BibTeX RDF
14	Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez	Technology exploration for adaptive power and frequency scaling in 90nm CMOS.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive body bias, low power, CMOS, performance optimization, leakage, adaptive voltage scaling
14	Chris Hyung-Il Kim, Hendrawan Soeleman, Kaushik Roy 0001	Ultra-low-power DLMS adaptive filter for hearing aid applications.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
14	Chris H. Kim, Kaushik Roy 0001	Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors.	ISLPED	2002	DBLP DOI BibTeX RDF