Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Ralf Wimmer 0001, Karina Wimmer, Christoph Scholl 0001, Bernd Becker 0001 |
Analysis of Incomplete Circuits Using Dependency Quantified Boolean Formulas. |
Advanced Logic Synthesis |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Charles André, Julien DeAntoni, Frédéric Mallet, Robert de Simone |
The Time Model of Logical Clocks Available in the OMG MARTE Profile. |
Synthesis of Embedded Software |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Alexandre Cortier, Loïc Besnard, Jean-Paul Bodeveix, Jérémy Buisson, Fabien Dagnat, Mamoun Filali, Gérald Garcia, Julien Ouy, Marc Pantel, Ana-Elena Rugina, Martin Strecker, Jean-Pierre Talpin |
Synoptic: A Domain-Specific Modeling Language for Space On-board Application Software. |
Synthesis of Embedded Software |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Dumitru Potop-Butucaru, Robert de Simone, Yves Sorel |
From Synchronous Specifications to Statically Scheduled Hard Real-Time Implementations. |
Synthesis of Embedded Software |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Julien Boucaron, Anthony Coadou, Robert de Simone |
Formal Modeling of Embedded Systems with Explicit Schedules and Routes. |
Synthesis of Embedded Software |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Yann Glouche, Thierry Gautier, Paul Le Guernic, Jean-Pierre Talpin |
A Module Language for Typing SIGNAL Programs by Contracts. |
Synthesis of Embedded Software |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Stephen A. Edwards, Nalini Vasudevan |
Compiling SHIM. |
Synthesis of Embedded Software |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Loïc Besnard, Thierry Gautier, Paul Le Guernic, Jean-Pierre Talpin |
Compilation of Polychronous Data Flow Equations. |
Synthesis of Embedded Software |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Rastislav Bodík, Orna Kupferman, Douglas R. Smith, Eran Yahav (eds.) |
Software Synthesis, 06.12. - 11.12.2009 |
Software Synthesis |
2009 |
DBLP BibTeX RDF |
|
26 | Luc De Raedt, Thomas G. Dietterich, Lise Getoor, Kristian Kersting, Stephen H. Muggleton (eds.) |
Probabilistic, Logical and Relational Learning - A Further Synthesis, 15.04. - 20.04.2007 |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2008 |
DBLP BibTeX RDF |
|
26 | Taisuke Sato, Yoshitaka Kameya, Kenichi Kurihara |
Variational Bayes via Propositionalization. |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2007 |
DBLP BibTeX RDF |
|
26 | Nicolas Baskiotis, Michèle Sebag |
Structural Sampling for Statistical Software Testing. |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2007 |
DBLP BibTeX RDF |
|
26 | Pedro M. Domingos, Parag Singla |
Markov Logic in Infinite Domains. |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2007 |
DBLP BibTeX RDF |
|
26 | James Cussens |
Model equivalence of PRISM programs. |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2007 |
DBLP BibTeX RDF |
|
26 | Luke S. Zettlemoyer, Hanna M. Pasula, Leslie Pack Kaelbling |
Logical Particle Filtering. |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2007 |
DBLP BibTeX RDF |
|
26 | Sriraam Natarajan, Prasad Tadepalli, Alan Fern |
Exploiting prior knowledge in Intelligent Assistants - Combining relational models with hierarchies. |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2007 |
DBLP BibTeX RDF |
|
26 | Ashwin Deshpande, Brian Milch, Luke S. Zettlemoyer, Leslie Pack Kaelbling |
Learning Probabilistic Relational Dynamics for Multiple Tasks. |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2007 |
DBLP BibTeX RDF |
|
26 | Barbara Hammer, Alessio Micheli, Alessandro Sperduti |
A general framework for unsupervised preocessing of structured data. |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2007 |
DBLP BibTeX RDF |
|
26 | Peter A. Flach, Edson Takashi Matsubara |
On classification, ranking, and probability estimation. |
Probabilistic, Logical and Relational Learning - A Further Synthesis |
2007 |
DBLP BibTeX RDF |
|
26 | Henry A. Kautz, Wolfgang Thomas, Moshe Y. Vardi (eds.) |
Synthesis and Planning, 12.-17. June 2005 |
Synthesis and Planning |
2006 |
DBLP BibTeX RDF |
|
26 | David P. LaPotin, Charles J. Alpert, John Lillis (eds.) |
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002 |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP BibTeX RDF |
|
26 | Hai Zhou 0001 |
Clock schedule verification with crosstalk. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
verification, delay, coupling, clock schedule |
26 | Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga |
The statistical longest path problem and its application to delay analysis of logical circuits. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili |
Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
VLSI, clock distribution network, zero skew |
26 | Avi Efrati, Moshe Kleyner |
Timing analysis challenges for high speed CPUs at 90nm and below. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Himanshu Kaul, Dennis Sylvester, David T. Blaauw |
Active shielding of RLC global interconnects. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Sangyun Kim 0001, Sunan Tugsinavisut, Peter A. Beerel |
Reducing probabilistic timed petri nets for asynchronous architectural analysis. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Jun Chen 0008, Lei He 0001 |
Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
interconnect design |
26 | Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu 0001 |
Test structures for delay variability. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Min Zhao 0001, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal |
Worst case clock skew under power supply variations. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
clock skew, power supply noise, clock network |
26 | Kurt Keutzer, Michael Orshansky |
From blind certainty to informed uncertainty. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula |
Statistical timing analysis using bounds and selective enumeration. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Paul I. Pénzes, Mika Nyström, Alain J. Martin |
Transistor sizing of energy-delay--efficient circuits. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
energy-delay optimization, transistor sizing |
26 | Louis Scheffer |
Explicit computation of performance as a function of process variation. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
static timing, process variation, yield, statistical timing |
26 | Brian A. Floyd, Xiaoling Guo, James Caserta, Timothy O. Dickson, Chih-Ming Hung, Kihong Kim, Kenneth K. O |
Wireless interconnects for clock distribution. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
integrated antenna, wireless interconnect, wireless communication, interconnect, clock distribution, RF CMOS |
26 | Joni Dambre, Dirk Stroobandt, Jan Van Campenhout |
A probabilistic approach to clock cycle prediction. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
clock cycle prediction, performance modeling, interconnect prediction |
26 | Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
A library compatible driving point model for on-chip RLC interconnects. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Baris Taskin, Ivan S. Kourtev |
Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
optimization, linear programming, clock skew, cycle stealing |
26 | Bhavana Thudi, David T. Blaauw |
Efficient switching window computation for cross-talk noise. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula |
Statistical timing analysis using bounds and selective enumeration. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang |
Aggressive crunching of extracted RC netlists. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
RC reduction, TICER, crunching, node elimination, resistor shorting, time constants, interconnect modeling, elmore delay |
26 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan |
PERI: a technique for extending delay and slew metrics to ramp inputs. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
Elmore, slew, delay, interconnects, PDF, moments, median, skewness, standard deviation |
26 | Gabriele Saucier, Jacques Trilhe (eds.) |
Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992 |
Synthesis for Control Dominated Circuits |
1993 |
DBLP BibTeX RDF |
|
26 | Eric Gautrin, Laurent Perraudeau |
MADMACS: an environment for the layout of regular arrays. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | H. Zhang, Kunihiro Asada |
A general and efficient mask pattern generator for non-series-parallel CMOS transistor network. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | C. Safina, Régis Leveugle |
Clocking scheme selection for circuits made up of a controller and a datapath. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Jochen Beister, Ralf Wollowski |
Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required Behavior. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Evagelos Katsadas, Zohair Sahraoui, Maryse Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man |
Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Daniel Gajski, Nikil D. Dutt |
Benchmarking and the Art of Syntesis Tool Comparison. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | A. J. W. M. ten Berg |
Floorplan Optimized Topological Partitioning of Programmed Logic Arrays. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura |
Design of data-path module generators from algorithmic representations. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Antonio Martinez |
Timing Model Accuracy Issues and Automated Library Characterization. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Steve C.-Y. Huang, Wayne H. Wolf |
Timing-Driven State Assignment for Controller-Datapath Systems. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Régis Leveugle, C. Safina |
Generation of optimized datapaths: bit-slice versus standard cells. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Yang Wu, Ian Dorrington |
RTL OptimizA: From Control Data Flow Graph to Logic Circuit. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Lotfi Ben Ammar, Alain Greiner |
FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Francesco Curatelli, Daniele D. Caviglia, Marco Chirico, Giacomo M. Bisio |
Optimization strategies in symbolic compaction. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Amnon Baron Cohen, Michael Shechory |
Pathway: A datapath layout assembler. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | B. Conq, R. Etienne, T. Perez-Segovia |
Design Library Portability: A Case Study. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man |
Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers. |
Synthesis for Control Dominated Circuits |
1992 |
DBLP BibTeX RDF |
|
26 | Miriam Leeser, Geoffrey Brown (eds.) |
Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings |
Hardware Specification, Verification and Synthesis |
1990 |
DBLP DOI BibTeX RDF |
|
26 | Randal E. Bryant |
Verification of Synchronous Circuits by Symbolic Logic Simulation. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Christian Lengauer, Bikash Sabata, Farshid Arman |
A Mechanically Derived Systolic Implementation of Pyramid Initialization. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | David A. Basin, Peter Del Vecchio |
Verification Of Combinational Logic in Nuprl. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Brian T. Graham, Graham M. Birtwistle |
Formalising the Design of an SECD chip. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Paul Loewenstein |
Reasoning about State Machines in Higher-Order Logic. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | David L. Dill |
Complete Trace Structures. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Mark Bickford, Mandayam K. Srivas |
Verification of a Pipelined Microprocessor Using Clio. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Warren A. Hunt Jr., Bishop Brock |
The Verification of a Bit-slice ALU. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | George J. Milne |
Design for Verifiability. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Mary Sheeran |
Categories for the Working Hardware Designer. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Daniel Weise |
Constraints, Abstraction and Verification. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Jeffrey J. Joyce |
Totally Verified Systems: Linking Verified Software to Verified Hardware. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
machine-assisted theorem proving, safety-critical systems, higher-order logic, hardware verification, compiler correctness |
26 | Shiu-Kai Chin |
Combining Engineering Vigor with Mathematical Rigor. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Wolfgang Bibel, Klaus P. Jantke (eds.) |
Mathematical Methods of Specification and Synthesis of Software Systems '85, Proceedings of the International Spring School, Wendisch-Rietz, GDR, April 22-26, 1985 |
Mathematical Methods of Specification and Synthesis of Software Systems |
1986 |
DBLP DOI BibTeX RDF |
|
26 | Robert P. Daley |
Inductive inference hierarchies: probabilistic vs pluralistic strategies. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Zdzislaw Habasinski |
Decidability in Pratt's process logics. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Takeshi Shinohara |
Some problems on inductive inference from positive data. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Bernhard Thalheim |
Deductive normal forms of relations. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Enn Tyugu |
Language and example of knowledge-based programming. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Helena Rasiowa, Andrzej Skowron |
Approximation logic. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Sergei S. Goncharov, Dmitri Ivanovich Sviridenko |
Theoretical aspects of Sigma-programming. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Werner Dilger, Wolfgang Womann |
The METANET. A knowledge representation tool based on abstract data types. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Dieter Pötschke |
Formalizing analogical reasoning. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Jan A. Bergstra, Jan Willem Klop |
Verification of an alternating bit protocol by means of process algebra. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Christian Posthoff, Joachim Reiß |
The solution of discrete problems by means of ternary representation. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Tamás Gergely, Konstantin Vershinin |
Natural mathematical texts vs. programs. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Jolanta Cybulka, Jerzy Bartoszek |
The proof-checking component for the PLEATS programming system enabling specification of theories. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Marek Ejsmont |
One more property of array languages. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Péter Komjáth, Zsolt Mihály Szabó |
Orientation problems on sequences by recursive functions. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Thomas Zeugmann |
On recursive optimizers. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Jacques Loeckx |
The algorithmic specification method of abstract data types: an overview. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Wolfgang Bibel |
Predicative programming revisited. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Nicolas Bonneel, George Drettakis, Nicolas Tsingos, Isabelle Viaud-Delmon, Doug L. James |
Fast modal sounds with scalable frequency-domain synthesis. |
ACM Trans. Graph. |
2008 |
DBLP DOI BibTeX RDF |
modal synthesis, real-time audio rendering, physically based animation, sound synthesis |
26 | Sotiris Karabetsos, Pirros Tsiakoulis, Aimilios Chalamandaris, Spyros Raptis |
HMM-Based Speech Synthesis for the Greek Language. |
TSD |
2008 |
DBLP DOI BibTeX RDF |
Greek Language, Statistical Parametric Speech Synthesis, HMM, Hidden Markov Model, Speech Synthesis, Text to Speech |
26 | Dominik Bauer, Jim Kannampuzha, Bernd J. Kröger |
Articulatory Speech Re-synthesis: Profiting from Natural Acoustic Speech Data. |
COST 2102 Conference (Prague) |
2008 |
DBLP DOI BibTeX RDF |
articulatory speech synthesis, vocal tract action units, speech, articulation, re-synthesis |
26 | Paul Tarau, Brenda Luderman |
A Logic Programming Framework for Combinational Circuit Synthesis. |
ICLP |
2007 |
DBLP DOI BibTeX RDF |
logic programming and circuit design, combinatorial object generation, exact combinational circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count circuit synthesis |
26 | Zhigang Deng, Ulrich Neumann, John P. Lewis, Tae-Yong Kim 0002, Murtaza Bulut, Shrikanth S. Narayanan |
Expressive Facial Animation Synthesis by Learning Speech Coarticulation and Expression Spaces. |
IEEE Trans. Vis. Comput. Graph. |
2006 |
DBLP DOI BibTeX RDF |
expressive speech, animation synthesis, speech coarticulation, motion capture, texture synthesis, Facial animation, data-driven |
26 | Chittaranjan A. Mandal, R. M. Zimmer |
A Genetic Algorithm for the Synthesis of Structured Data Paths. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation |
26 | Harry Hengster, Bernd Becker 0001 |
Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability. |
FTCS |
1999 |
DBLP DOI BibTeX RDF |
EXOR-based Synthesis, Decision Diagrams, Synthesis for Testability, High Speed Circuits |