Search results for "delay-insensitive"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	John Bainbridge, Stephen B. Furber	Chain: A Delay-Insensitive Chip Area Interconnect.	IEEE Micro	2002	DBLP DOI BibTeX RDF
19	Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alex Yakovlev, Takashi Nanya	Design of Asynchronous Controllers with Delay Insensitive Interface.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
19	Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, M. Hagedorn, Dennis Ferguson	Delay-insensitive gate-level pipelining.	Integr.	2001	DBLP DOI BibTeX RDF
19	Oscar Garnica, Juan Lanchares, Román Hermida	A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits.	DATE	2001	DBLP DOI BibTeX RDF
19	Oscar Garnica, Juan Lanchares, Román Hermida	Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation.	ACSD	2001	DBLP DOI BibTeX RDF
19	Fu-Chiung Cheng, Shuen-Long Ho	Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data Transmission.	ICCD	2001	DBLP DOI BibTeX RDF
19	Alagan S. Anpalagan, Elvino S. Sousa	A combined rate/power/cell control scheme for delay insensitive applications in CDMA systems.	GLOBECOM	2000	DBLP DOI BibTeX RDF
19	Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee	The Design of Delay Insensitive Asynchronous 16-bit Microprocessor.	ASP-DAC	1999	DBLP DOI BibTeX RDF
19	Alessandro De Gloria, Paolo Palma, Mauro Olivieri	Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications.	EUROMICRO	1999	DBLP DOI BibTeX RDF
19	Wolfram Hardt, Bernd Kleinjohann	Flysig: Dataflow Oriented Delay-Insensitive Processor for Rapid Prototyping of Signal Processing	CoRR	1998	DBLP BibTeX RDF
19	Arthit Thongtak, Takashi Nanya	Stuck-at-fault testing for quasi-delay-insensitive logic circuits.	Syst. Comput. Jpn.	1998	DBLP DOI BibTeX RDF
19	Stanislaw J. Piestrak	Membership Test Logic for Delay-Insensitive Codes.	ASYNC	1998	DBLP DOI BibTeX RDF
19	Wolfram Hardt, Bernd Kleinjohann	FLYSIG: Dataflow Oriented Delay-Insensitive Processor for Rapid Prototyping of Signal Processing.	International Workshop on Rapid System Prototyping	1998	DBLP DOI BibTeX RDF
19	Anish Arora, Mohamed G. Gouda	Delay-insensitive stabilization.	WSS	1997	DBLP BibTeX RDF
19	Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya	TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model.	ICCD	1997	DBLP DOI BibTeX RDF
19	Fu-Chiung Cheng	Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits.	ICCD	1997	DBLP DOI BibTeX RDF
19	Hiroto Kagotani, Takashi Nanya	Performance enhancement of two-phase quasi-delay-insensitive circuits.	Syst. Comput. Jpn.	1996	DBLP DOI BibTeX RDF
19	Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo	Limitations of VLSI Implementation of Delay-Insensitive Codes.	FTCS	1996	DBLP DOI BibTeX RDF
19	Mario Blaum, Jehoshua Bruck	Delay-Insensitive Pipelined Communicatioon on Parallel Buses.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF
19	Hiroto Kagotani, Takashi Nanya	Synthesis of two-phase quasi-delay-insensitive circuits from dependency graphs.	Syst. Comput. Jpn.	1995	DBLP DOI BibTeX RDF
19	Stanislaw J. Piestrak, Takashi Nanya	Towards Totally Self-Checking Delay-Insensitive Systems.	FTCS	1995	DBLP DOI BibTeX RDF
19	David M. Goldschlag	Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits.	Formal Methods Syst. Des.	1994	DBLP DOI BibTeX RDF
19	Mario Blaum, Jehoshua Bruck	Coding for delay-insensitive communication with partial synchronization.	IEEE Trans. Inf. Theory	1994	DBLP DOI BibTeX RDF
19	Igor Benko, Jo C. Ebergen	Delay-insensitive solutions to the committee problem.	ASYNC	1994	DBLP DOI BibTeX RDF
19	Priyadarsan Patra, Donald S. Fussell	Efficient building blocks for delay insensitive circuits.	ASYNC	1994	DBLP DOI BibTeX RDF
19	Jens Sparsø, Jørgen Staunstrup	Delay-insensitive multi-ring structures.	Integr.	1993	DBLP DOI BibTeX RDF
19	Christian D. Nielsen, Alain J. Martin	Design of a delay-insensitive multiply-accumulate unit.	Integr.	1993	DBLP DOI BibTeX RDF
19	Jo C. Ebergen, Ad M. G. Peeters	Design and Analysis of Delay-Insensitive Modulo-N Counters.	Formal Methods Syst. Des.	1993	DBLP DOI BibTeX RDF
19	Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri	Delay insensitive micro-pipelined combinational logic.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
19	Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri	A delay insensitive approach to the VLSI design of a DRAM controller.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
19	Marly Roncken, Ronald Saeijs	Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
19	Mark B. Josephs, Jan Tijmen Udding	Implementing a Stack as a Delay-insensitive Circuit.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
19	Rix Groenboom, Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding	Normal Form in a Delay-Insensitive Algebra.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
19	Richard P. Paul, Thomas S. Lindsay, Craig Sayers	Time Delay Insensitive Teleoperation.	IROS	1992	DBLP DOI BibTeX RDF
19	Jens Sparsø, Jørgen Staunstrup, Michael Dantzer-Sørensen	Design of delay insensitive circuits using multi-ring structures.	EURO-DAC	1992	DBLP DOI BibTeX RDF
19	Jo C. Ebergen, Ad M. G. Peeters	Modulo-N Counters: Design and Analysis of Delay-Insensitive Circuits.	Designing Correct Circuits	1992	DBLP BibTeX RDF
19	Jo C. Ebergen	A Formal Approach to Designing Delay-Insensitive Circuits.	Distributed Comput.	1991	DBLP DOI BibTeX RDF
19	Henrik Hulgaard, Per H. Christensen, Jørgen Staunstrup	Synthesizing Delay Insensitive Circuits from Verified Programs.	Research Directions in High-Level Parallel Programming Languages	1991	DBLP DOI BibTeX RDF
19	Hon Fung Li, S. C. Leung, P. N. Lam	Synthesis of Delay-Insensitive Circuits by Refinements into Atomic Threads.	ICCD	1991	DBLP DOI BibTeX RDF
19	Mark B. Josephs, Jan Tijmen Udding	An Algebra for Delay-Insensitive Circuits.	CAV	1990	DBLP DOI BibTeX RDF
19	Mark B. Josephs, Jan Tijmen Udding	An Algebra for Delay-Insensitive Circuits.	CAV (DIMACS/AMS volume)	1990	DBLP DOI BibTeX RDF
19	Erik Brunvand, Robert F. Sproull	Translating concurrent programs into delay-insensitive circuits.	ICCAD	1989	DBLP DOI BibTeX RDF
19	Tom Verhoeff	Delay-Insensitive Codes - an Overview.	Distributed Comput.	1988	DBLP DOI BibTeX RDF
19	Fred U. Rosenberger, Charles E. Molnar, Thomas J. Chaney, Ting-Pien Fang	Q-Modules: Internally Clocked Delay-Insensitive Modules.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF
19	Kees van Berkel 0001, Ronald W. J. J. Saeijs	Compilation of communicating processes into delay-insensitive circuits.	ICCD	1988	DBLP DOI BibTeX RDF
19	Alain J. Martin	Compiling Communicating Processes Into Delay-Insensitive VLSI Circuits.	Distributed Comput.	1986	DBLP DOI BibTeX RDF
19	Jan Tijmen Udding	A Formal Model for Defining and Classifying Delay-Insensitive Circuits and Systems.	Distributed Comput.	1986	DBLP DOI BibTeX RDF
19	David L. Black 0001	On the Existence of Delay-Insensitive Fair Arbiters: Trace Theory and its Limitations.	Distributed Comput.	1986	DBLP DOI BibTeX RDF
17	Bao Liu 0001	Robust differential asynchronous nanoelectronic circuits.	ISQED	2009	DBLP DOI BibTeX RDF
17	Mihaela van der Schaar, Deepak S. Turaga	Cross-Layer Packetization and Retransmission Strategies for Delay-Sensitive Wireless Multimedia Transmission.	IEEE Trans. Multim.	2007	DBLP DOI BibTeX RDF
14	Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert Cauwenberghs	Adaptive delay compensation in multi-dithering adaptive control.	ISCAS	2008	DBLP DOI BibTeX RDF
14	David K. Probst, Hon Fung Li	Verifying Timed Behavior Automata with Nonbinary Delay Constraints.	CAV	1992	DBLP DOI BibTeX RDF
12	Iana Siomina, Stefan Wänstedt	The impact of QoS support on the end user satisfaction in LTE networks with mixed traffic.	PIMRC	2008	DBLP DOI BibTeX RDF
12	Joris Walraevens, Sabine Wittevrongel, Herwig Bruneel	Analysis of Priority Queues with Session-Based Arrival Streams.	ICN	2008	DBLP DOI BibTeX RDF
12	Ernest S. Lo, Peter W. C. Chan, Vincent K. N. Lau, Roger S. Cheng, Khaled Ben Letaief, Ross D. Murch, Wai Ho Mow	Adaptive Resource Allocation and Capacity Comparison of Downlink Multiuser MIMO-MC-CDMA and MIMO-OFDMA.	IEEE Trans. Wirel. Commun.	2007	DBLP DOI BibTeX RDF
12	Peter W. C. Chan, Ernest S. Lo, Vincent K. N. Lau, Roger S. Cheng, Khaled Ben Letaief, Ross D. Murch, Wai Ho Mow	Performance Comparison of Downlink Multiuser MIMO-OFDMA and MIMO-MC-CDMA with Transmit Side Information - Multi-Cell Analysis.	IEEE Trans. Wirel. Commun.	2007	DBLP DOI BibTeX RDF
12	Palanichamy Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, Chittaranjan R. Mandal	Asynchronous Design Methodology for an Efficient Implementation of Low power ALU.	APCCAS	2006	DBLP DOI BibTeX RDF
12	Frederic Worm, Patrick Thiran, Paolo Ienne	A Unified Coding Framework for Delay-Insensitivity.	ASYNC	2005	DBLP DOI BibTeX RDF
12	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders.	PATMOS	2003	DBLP DOI BibTeX RDF
12	Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese	PLFire: A Visualization Tool for Asynchronous Phased Logic Designs.	DATE	2003	DBLP DOI BibTeX RDF
12	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Automatic Generation of 1-of-M QDI Asynchronous Adders.	SBCCI	2003	DBLP DOI BibTeX RDF
12	Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel	An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
12	Charles E. Molnar, Ian W. Jones	Simple Circuits that Work for Complicated Reasons.	ASYNC	2000	DBLP DOI BibTeX RDF	MUTEX, Delay measurement technique, Latch control circuit, Charlie Box, Asynchronous, FIFO, Arbiter, Micropipeline
12	Willem C. Mallon, Jan Tijmen Udding, Tom Verhoeff	Analysis and Applications of the XDI model.	ASYNC	1999	DBLP DOI BibTeX RDF	Verification, Factorization, Derivation, Communicating Processes, Delay Insensitivity
12	Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev	What is the cost of delay insensitivity?	ICCAD	1999	DBLP DOI BibTeX RDF
10	Jun Wu, Yong-Bin Kim, Minsu Choi	Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	substitution box, substitution box (S-box), differential power/noise analysis, power/noise measurement, security, advanced encryption standard, advanced encryption standard, side-channel attacks (SCA), null convention logic
10	Werner Friesenbichler, Thomas Panhofer, Martin Delvai	A comprehensive approach for soft error tolerant Four State Logic.	DDECS	2009	DBLP DOI BibTeX RDF
10	Charlie Brej, Doug Edwards	Forward and backward guarding in early output logic.	DDECS	2009	DBLP DOI BibTeX RDF
10	Werner Friesenbichler, Thomas Panhofer, Martin Delvai	Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
10	Simon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovlev	Asynchronous transient resilient links for NoC.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	point to point link, reliability, network-on-chip, asynchronous, transient faults
10	Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu	Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	robust hardware, back-end design automation, power-constant architectures, DFY, side-channel attacks, DFM, mitigation
10	Thomas Panhofer, Martin Delvai	Self-Healing Circuits for Space-Applications.	FPL	2007	DBLP DOI BibTeX RDF
10	Mohammad Hossein Falaki	The Wi-Fi Roaming Game.	WINE	2007	DBLP DOI BibTeX RDF
10	Recep O. Ozdag, Peter A. Beerel	An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
10	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin	State-holding in Look-Up Tables: application to asynchronous logic.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
10	William B. Toms, David A. Edwards, Andrew Bardsley	Synthesising Heterogeneously Encoded Systems.	ASYNC	2006	DBLP DOI BibTeX RDF
10	Yu Zhou 0006, Danil Sokolov, Alexandre Yakovlev	Cost-aware synthesis of asynchronous circuits based on partial acknowledgement.	ICCAD	2006	DBLP DOI BibTeX RDF
10	Konrad J. Kulikowski, Alexander B. Smirnov, Alexander Taubin	Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks.	CHES	2006	DBLP DOI BibTeX RDF
10	Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin	An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.	ASYNC	2005	DBLP DOI BibTeX RDF
10	Wonjin Jang, Alain J. Martin	SEU-Tolerant QDI Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
10	Alexander B. Smirnov, Alexander Taubin, Ming Su, Mark G. Karpovsky	An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library.	ACSD	2005	DBLP DOI BibTeX RDF	asynchronous EDA, QDI, synthesis, ASIC, HDL
10	Yannick Monnet, Marc Renaudin, Régis Leveugle	Hardening Techniques against Transient Faults for Asynchronous Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
10	Fredrik Berggren, Riku Jäntti	Asymptotically fair transmission scheduling over fading channels.	IEEE Trans. Wirel. Commun.	2004	DBLP DOI BibTeX RDF
10	Mohammad K. Akbari, Ali Jahanian 0001, Mohsen Naderi, Bahman Javadi	Area Efficient, Low Power and Robust Design for Add-Compare-Select Units.	DSD	2004	DBLP DOI BibTeX RDF
10	David Fang, Rajit Manohar	Non-Uniform Access Asynchronous Register Files.	ASYNC	2004	DBLP DOI BibTeX RDF
10	Recep O. Ozdag, Peter A. Beerel	A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates.	ASYNC	2004	DBLP DOI BibTeX RDF
10	Mika Nyström, Elaine Ou, Alain J. Martin	An Eight-Bit Divider Implemented in Asynchronous Pulse Logic.	ASYNC	2004	DBLP DOI BibTeX RDF
10	Yannick Monnet, Marc Renaudin, Régis Leveugle	Asynchronous Circuits Sensitivity to Fault Injection.	IOLTS	2004	DBLP DOI BibTeX RDF
10	Satish K. Bandapati, Scott C. Smith, Minsu Choi	Design and Characterization of Null Convention Self-Timed Multipliers.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
10	Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari	An Asynchronous Viterbi Decoder for Low-Power Applications.	PATMOS	2003	DBLP DOI BibTeX RDF
10	Virantha N. Ekanayake, Rajit Manohar	Asynchronous DRAM Design and Synthesis.	ASYNC	2003	DBLP DOI BibTeX RDF
10	Kenneth S. Stevens	Energy and Performance Models for Clocked and Asynchronous Communication.	ASYNC	2003	DBLP DOI BibTeX RDF
10	Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani	An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow.	HICSS	2003	DBLP DOI BibTeX RDF
10	Oscar Garnica, Juan Lanchares, Román Hermida	A New Methodology to Design Low-Power Asynchronous Circuits.	PATMOS	2002	DBLP DOI BibTeX RDF
10	Mark B. Josephs, Dennis P. Furey	A Programming Approach to the Design of Asynchronous Logic Blocks.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
10	Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver	Generalized Early Evaluation in Self-Timed Circuits.	DATE	2002	DBLP DOI BibTeX RDF
10	Marcos Ferretti, Peter A. Beerel	Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding.	DATE	2002	DBLP DOI BibTeX RDF
10	Recep O. Ozdag, Peter A. Beerel	High-Speed QDI Asynchronous Pipelines.	ASYNC	2002	DBLP DOI BibTeX RDF	conditional split, conditional join, QDI, pipelines, asynchronous, dynamic logic, joins, non-linear, fine-grain, micropipelines, forks
10	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
10	Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand	Peephole optimization of asynchronous macromodule networks.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF