Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | John Bainbridge, Stephen B. Furber |
Chain: A Delay-Insensitive Chip Area Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 22(5), pp. 16-23, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alex Yakovlev, Takashi Nanya |
Design of Asynchronous Controllers with Delay Insensitive Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12), pp. 2577-2585, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
19 | Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, M. Hagedorn, Dennis Ferguson |
Delay-insensitive gate-level pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 30(2), pp. 103-131, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Oscar Garnica, Juan Lanchares, Román Hermida |
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 810, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Oscar Garnica, Juan Lanchares, Román Hermida |
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 2nd International Conference on Application of Concurrency to System Design (ACSD 2001), 25-30 June 2001, Newcastle upon Tyne, UK, pp. 167-178, 2001, IEEE Computer Society, 0-7695-1071-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Fu-Chiung Cheng, Shuen-Long Ho |
Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data Transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings, pp. 24-31, 2001, IEEE Computer Society, 0-7695-1200-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Alagan S. Anpalagan, Elvino S. Sousa |
A combined rate/power/cell control scheme for delay insensitive applications in CDMA systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GLOBECOM ![In: Proceedings of the Global Telecommunications Conference, 2000. GLOBECOM 2000, San Francisco, CA, USA, 27 November - 1 December 2000, pp. 256-260, 2000, IEEE, 0-7803-6451-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee |
The Design of Delay Insensitive Asynchronous 16-bit Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 33-36, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Alessandro De Gloria, Paolo Palma, Mauro Olivieri |
Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1244-1247, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Wolfram Hardt, Bernd Kleinjohann |
Flysig: Dataflow Oriented Delay-Insensitive Processor for Rapid Prototyping of Signal Processing ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR cs.AR/9810011, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP BibTeX RDF |
|
19 | Arthit Thongtak, Takashi Nanya |
Stuck-at-fault testing for quasi-delay-insensitive logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 29(2), pp. 19-27, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Stanislaw J. Piestrak |
Membership Test Logic for Delay-Insensitive Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 194-, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Wolfram Hardt, Bernd Kleinjohann |
FLYSIG: Dataflow Oriented Delay-Insensitive Processor for Rapid Prototyping of Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Workshop on Rapid System Prototyping ![In: Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), Leuven, Belgium, June 3-5, 1998, pp. 136-141, 1998, IEEE Computer Society, 0-8186-8479-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Anish Arora, Mohamed G. Gouda |
Delay-insensitive stabilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSS ![In: 3rd Workshop on Self-stabilizing Systems, Santa Barbara, California, USA, August, 1997, Proceedings, pp. 95-109, 1997, Carleton University Press, 0-88629-333-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP BibTeX RDF |
|
19 | Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya |
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997, pp. 288-294, 1997, IEEE Computer Society, 0-8186-8206-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Fu-Chiung Cheng |
Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997, pp. 301-306, 1997, IEEE Computer Society, 0-8186-8206-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Hiroto Kagotani, Takashi Nanya |
Performance enhancement of two-phase quasi-delay-insensitive circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 27(5), pp. 39-46, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo |
Limitations of VLSI Implementation of Delay-Insensitive Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-26, The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing, Sendai, Japan, June 25-27, 1996, pp. 208-217, 1996, IEEE Computer Society, 0-8186-7261-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Mario Blaum, Jehoshua Bruck |
Delay-Insensitive Pipelined Communicatioon on Parallel Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(5), pp. 660-668, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Hiroto Kagotani, Takashi Nanya |
Synthesis of two-phase quasi-delay-insensitive circuits from dependency graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 26(4), pp. 11-19, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Stanislaw J. Piestrak, Takashi Nanya |
Towards Totally Self-Checking Delay-Insensitive Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-25, The Twenty-Fifth International Symposium on Fault-Tolerant Computing, Pasadena, California, USA, June 27-30, 1995, pp. 228-237, 1995, IEEE Computer Society, 0-8186-7079-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | David M. Goldschlag |
Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 5(3), pp. 207-225, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Mario Blaum, Jehoshua Bruck |
Coding for delay-insensitive communication with partial synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 40(3), pp. 941-945, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Igor Benko, Jo C. Ebergen |
Delay-insensitive solutions to the committee problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1994, Salt Lake City, UT, USA, November 3-5, 1994, pp. 228-237, 1994, IEEE, 0-8186-6210-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Priyadarsan Patra, Donald S. Fussell |
Efficient building blocks for delay insensitive circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1994, Salt Lake City, UT, USA, November 3-5, 1994, pp. 196-205, 1994, IEEE, 0-8186-6210-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Jens Sparsø, Jørgen Staunstrup |
Delay-insensitive multi-ring structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 15(3), pp. 313-340, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Christian D. Nielsen, Alain J. Martin |
Design of a delay-insensitive multiply-accumulate unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 15(3), pp. 291-311, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Jo C. Ebergen, Ad M. G. Peeters |
Design and Analysis of Delay-Insensitive Modulo-N Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 3(3), pp. 211-232, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri |
Delay insensitive micro-pipelined combinational logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 36(5), pp. 225-241, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri |
A delay insensitive approach to the VLSI design of a DRAM controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 37(1-5), pp. 19-22, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Marly Roncken, Ronald Saeijs |
Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 13-27, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
19 | Mark B. Josephs, Jan Tijmen Udding |
Implementing a Stack as a Delay-insensitive Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 123-135, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
19 | Rix Groenboom, Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding |
Normal Form in a Delay-Insensitive Algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 57-70, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
19 | Richard P. Paul, Thomas S. Lindsay, Craig Sayers |
Time Delay Insensitive Teleoperation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 1992, Raleigh, NC, USA, 7-10 Jul 1992, pp. 247-254, 1992, IEEE, 0-7803-0737-2. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Jens Sparsø, Jørgen Staunstrup, Michael Dantzer-Sørensen |
Design of delay insensitive circuits using multi-ring structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992, pp. 15-20, 1992, IEEE Computer Society Press, 0-8186-2780-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Jo C. Ebergen, Ad M. G. Peeters |
Modulo-N Counters: Design and Analysis of Delay-Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Designing Correct Circuits ![In: Designing Correct Circuits, Proceedings of the Second IFIP WG10.2/WG10.5 Workshop on Designing Correct Circuits, Lyngby, Denmark, 6-8 January 1992, pp. 27-46, 1992, North-Holland, 0-444-89335-0. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
19 | Jo C. Ebergen |
A Formal Approach to Designing Delay-Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 5, pp. 107-119, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Henrik Hulgaard, Per H. Christensen, Jørgen Staunstrup |
Synthesizing Delay Insensitive Circuits from Verified Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Research Directions in High-Level Parallel Programming Languages ![In: Research Directions in High-Level Parallel Programming Languages, Mont Saint-Michel, France, June 17-19, 1991, Procedings, pp. 326-337, 1991, Springer, 3-540-55160-3. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Hon Fung Li, S. C. Leung, P. N. Lam |
Synthesis of Delay-Insensitive Circuits by Refinements into Atomic Threads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 180-186, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Mark B. Josephs, Jan Tijmen Udding |
An Algebra for Delay-Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 2nd International Workshop, CAV '90, New Brunswick, NJ, USA, June 18-21, 1990, Proceedings, pp. 343-352, 1990, Springer, 3-540-54477-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Mark B. Josephs, Jan Tijmen Udding |
An Algebra for Delay-Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV (DIMACS/AMS volume) ![In: Computer-Aided Verification, Proceedings of a DIMACS Workshop 1990, New Brunswick, New Jersey, USA, June 18-21, 1990, pp. 147-176, 1990, DIMACS/AMS, 978-0-8218-6594-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Erik Brunvand, Robert F. Sproull |
Translating concurrent programs into delay-insensitive circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers, pp. 262-265, 1989, IEEE Computer Society, 0-8186-1986-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | Tom Verhoeff |
Delay-Insensitive Codes - an Overview. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 3(1), pp. 1-8, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | Fred U. Rosenberger, Charles E. Molnar, Thomas J. Chaney, Ting-Pien Fang |
Q-Modules: Internally Clocked Delay-Insensitive Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(9), pp. 1005-1018, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | Kees van Berkel 0001, Ronald W. J. J. Saeijs |
Compilation of communicating processes into delay-insensitive circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 157-162, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | Alain J. Martin |
Compiling Communicating Processes Into Delay-Insensitive VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 1(4), pp. 226-234, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Jan Tijmen Udding |
A Formal Model for Defining and Classifying Delay-Insensitive Circuits and Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 1(4), pp. 197-204, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | David L. Black 0001 |
On the Existence of Delay-Insensitive Fair Arbiters: Trace Theory and its Limitations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 1(4), pp. 205-225, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
17 | Bao Liu 0001 |
Robust differential asynchronous nanoelectronic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 97-102, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Mihaela van der Schaar, Deepak S. Turaga |
Cross-Layer Packetization and Retransmission Strategies for Delay-Sensitive Wireless Multimedia Transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multim. ![In: IEEE Trans. Multim. 9(1), pp. 185-197, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert Cauwenberghs |
Adaptive delay compensation in multi-dithering adaptive control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2182-2185, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | David K. Probst, Hon Fung Li |
Verifying Timed Behavior Automata with Nonbinary Delay Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, Fourth International Workshop, CAV '92, Montreal, Canada, June 29 - July 1, 1992, Proceedings, pp. 123-136, 1992, Springer, 3-540-56496-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
12 | Iana Siomina, Stefan Wänstedt |
The impact of QoS support on the end user satisfaction in LTE networks with mixed traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PIMRC ![In: Proceedings of the IEEE 19th International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2008, 15-18 September 2008, Cannes, French Riviera, France, pp. 1-5, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Joris Walraevens, Sabine Wittevrongel, Herwig Bruneel |
Analysis of Priority Queues with Session-Based Arrival Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICN ![In: Seventh International Conference on Networking (ICN 2008), 13-18 April 2008, Cancun, Mexico, pp. 503-510, 2008, IEEE Computer Society, 978-0-7695-3106-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Ernest S. Lo, Peter W. C. Chan, Vincent K. N. Lau, Roger S. Cheng, Khaled Ben Letaief, Ross D. Murch, Wai Ho Mow |
Adaptive Resource Allocation and Capacity Comparison of Downlink Multiuser MIMO-MC-CDMA and MIMO-OFDMA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 6(3), pp. 1083-1093, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Peter W. C. Chan, Ernest S. Lo, Vincent K. N. Lau, Roger S. Cheng, Khaled Ben Letaief, Ross D. Murch, Wai Ho Mow |
Performance Comparison of Downlink Multiuser MIMO-OFDMA and MIMO-MC-CDMA with Transmit Side Information - Multi-Cell Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 6(6), pp. 2193-2203, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Palanichamy Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, Chittaranjan R. Mandal |
Asynchronous Design Methodology for an Efficient Implementation of Low power ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 590-593, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Frederic Worm, Patrick Thiran, Paolo Ienne |
A Unified Coding Framework for Delay-Insensitivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 201-211, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | João Leonardo Fragoso, Gilles Sicard, Marc Renaudin |
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 171-180, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese |
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11096-11097, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | João Leonardo Fragoso, Gilles Sicard, Marc Renaudin |
Automatic Generation of 1-of-M QDI Asynchronous Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 149-154, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel |
An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 361-364, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Charles E. Molnar, Ian W. Jones |
Simple Circuits that Work for Complicated Reasons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 138-149, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
MUTEX, Delay measurement technique, Latch control circuit, Charlie Box, Asynchronous, FIFO, Arbiter, Micropipeline |
12 | Willem C. Mallon, Jan Tijmen Udding, Tom Verhoeff |
Analysis and Applications of the XDI model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 19-22 April 1999, Barcelona, Spain, pp. 231-242, 1999, IEEE Computer Society, 0-7695-0031-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Verification, Factorization, Derivation, Communicating Processes, Delay Insensitivity |
12 | Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev |
What is the cost of delay insensitivity? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 316-323, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Jun Wu, Yong-Bin Kim, Minsu Choi |
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 459-464, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
substitution box, substitution box (S-box), differential power/noise analysis, power/noise measurement, security, advanced encryption standard, advanced encryption standard, side-channel attacks (SCA), null convention logic |
10 | Werner Friesenbichler, Thomas Panhofer, Martin Delvai |
A comprehensive approach for soft error tolerant Four State Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 214-217, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Charlie Brej, Doug Edwards |
Forward and backward guarding in early output logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 226-229, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Werner Friesenbichler, Thomas Panhofer, Martin Delvai |
Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 267-270, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Simon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovlev |
Asynchronous transient resilient links for NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 209-214, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
point to point link, reliability, network-on-chip, asynchronous, transient faults |
10 | Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu |
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(6), pp. 546-555, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
robust hardware, back-end design automation, power-constant architectures, DFY, side-channel attacks, DFM, mitigation |
10 | Thomas Panhofer, Martin Delvai |
Self-Healing Circuits for Space-Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 505-506, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Mohammad Hossein Falaki |
The Wi-Fi Roaming Game. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WINE ![In: Internet and Network Economics, Third International Workshop, WINE 2007, San Diego, CA, USA, December 12-14, 2007, Proceedings, pp. 412-418, 2007, Springer, 978-3-540-77104-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Recep O. Ozdag, Peter A. Beerel |
An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(9), pp. 975-985, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin |
State-holding in Look-Up Tables: application to asynchronous logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 12-17, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | William B. Toms, David A. Edwards, Andrew Bardsley |
Synthesising Heterogeneously Encoded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 138-149, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Yu Zhou 0006, Danil Sokolov, Alexandre Yakovlev |
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 158-163, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Konrad J. Kulikowski, Alexander B. Smirnov, Alexander Taubin |
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 399-413, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin |
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 54-63, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Wonjin Jang, Alain J. Martin |
SEU-Tolerant QDI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 156-165, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Alexander B. Smirnov, Alexander Taubin, Ming Su, Mark G. Karpovsky |
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 6-9 June 2005, St. Malo, France, pp. 68-76, 2005, IEEE Computer Society, 0-7695-2363-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous EDA, QDI, synthesis, ASIC, HDL |
10 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Hardening Techniques against Transient Faults for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 129-134, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Fredrik Berggren, Riku Jäntti |
Asymptotically fair transmission scheduling over fading channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 3(1), pp. 326-336, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Mohammad K. Akbari, Ali Jahanian 0001, Mohsen Naderi, Bahman Javadi |
Area Efficient, Low Power and Robust Design for Add-Compare-Select Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 611-614, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | David Fang, Rajit Manohar |
Non-Uniform Access Asynchronous Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 75-85, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Recep O. Ozdag, Peter A. Beerel |
A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 187-197, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Mika Nyström, Elaine Ou, Alain J. Martin |
An Eight-Bit Divider Implemented in Asynchronous Pulse Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 229-239, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Asynchronous Circuits Sensitivity to Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 121-128, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Satish K. Bandapati, Scott C. Smith, Minsu Choi |
Design and Characterization of Null Convention Self-Timed Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(6), pp. 26-36, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari |
An Asynchronous Viterbi Decoder for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 471-480, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Virantha N. Ekanayake, Rajit Manohar |
Asynchronous DRAM Design and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada, pp. 174-183, 2003, IEEE Computer Society, 0-7695-1898-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Kenneth S. Stevens |
Energy and Performance Models for Clocked and Asynchronous Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada, pp. 56-67, 2003, IEEE Computer Society, 0-7695-1898-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani |
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 36th Hawaii International Conference on System Sciences (HICSS-36 2003), CD-ROM / Abstracts Proceedings, January 6-9, 2003, Big Island, HI, USA, pp. 279, 2003, IEEE Computer Society, 0-7695-1874-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Oscar Garnica, Juan Lanchares, Román Hermida |
A New Methodology to Design Low-Power Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 108-117, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Mark B. Josephs, Dennis P. Furey |
A Programming Approach to the Design of Asynchronous Logic Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurrency and Hardware Design ![In: Concurrency and Hardware Design, Advances in Petri Nets, pp. 34-60, 2002, Springer, 3-540-00199-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver |
Generalized Early Evaluation in Self-Timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 255-259, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Marcos Ferretti, Peter A. Beerel |
Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1008-1015, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Recep O. Ozdag, Peter A. Beerel |
High-Speed QDI Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 13-22, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
conditional split, conditional join, QDI, pipelines, asynchronous, dynamic logic, joins, non-linear, fine-grain, micropipelines, forks |
10 | Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken |
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 73-, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing |
10 | Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand |
Peephole optimization of asynchronous macromodule networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(1), pp. 30-37, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|