Search results for "dfe"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Jay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, David Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang	A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
17	Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri	Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm.	ISCAS	2018	DBLP DOI BibTeX RDF
17	Chia-Tse Hung, Yu-Ping Huang, Wei-Zen Chen	A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking.	A-SSCC	2018	DBLP DOI BibTeX RDF
17	Naveed Iqbal 0001, Azzedine Zerguine	AFD-DFE Using Constraint-Based RLS and Phase Noise Compensation for Uplink SC-FDMA.	IEEE Trans. Veh. Technol.	2017	DBLP DOI BibTeX RDF
17	Hyun-Wook Lim, Sung-Won Choi, Jeong-Keun Ahn, Woong-Ki Min, Sang-Kyu Lee, Chang-Hoon Baek, Jae-Youl Lee, Gyoo-Cheol Hwang, Young-Hyun Jun, Bai-Sun Kong	A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
17	Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi	A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
17	Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim	A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
17	Nevin Alex Jacob, Bibhu Datta Sahoo 0002	Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE.	Circuits Syst. Signal Process.	2017	DBLP DOI BibTeX RDF
17	Xialin Jiang, Wei Su 0002, En Cheng	Combined Hybrid DFE and CCK Remodulator for Medium-Range Single-Carrier Underwater Acoustic Communications.	Wirel. Commun. Mob. Comput.	2017	DBLP DOI BibTeX RDF
17	Murchana Baruah, Aradhana Misra, Kandarpa Kumar Sarma	Split FTDNN-DFE Equalizer for Complex Non-linear Wireless Channels with NARMA Approximation.	J. Intell. Syst.	2017	DBLP DOI BibTeX RDF
17	Maedeh Fallahi, Abumoslem Jannesari	A Low-Power Three-Tap DFE with Switched Resistor Slicer and CTLE in 0.18μm CMOS Technology.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
17	Filipe Casal Ribeiro, Rui Dinis 0001, Francisco Cercas 0001, Adão Silva	Analytical BER Performance Evaluation in SISO and MIMO Environments with SC-FDE Modulations and IB-DFE Receivers.	Wirel. Pers. Commun.	2017	DBLP DOI BibTeX RDF
17	Hela Jedda, Leonardo Gomes Baltar, Oliver De Candido, Amine Mezghani, Josef A. Nossek	DFE/THP duality for FBMC with highly frequency selective channels.	CoRR	2017	DBLP BibTeX RDF
17	Kuan-Yu Chen, Wei-Yung Chen, Shen-Iuan Liu	A 0.31-pJ/bit 20-Gb/s DFE With 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
17	Yinhang Zhang, Qingsheng Hu, Yongzheng Zhan	A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology.	WWIC	2017	DBLP DOI BibTeX RDF
17	Philip J. Gerrish, Nick Hengartner	Inferring the Distribution of Fitness Effects (DFE) of Newly-Arising Mutations Using Samples Taken from Evolving Populations in Real Time.	AlCoB	2017	DBLP DOI BibTeX RDF
17	Xiuling Cao, Feng Tong, Weihua Jiang, Dongsheng Chen	Experimental evaluation of CE-DFE driven by NNCLMS algorithm for acoustic communication.	ICSPCC	2017	DBLP DOI BibTeX RDF
17	Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park	23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.	ISSCC	2017	DBLP DOI BibTeX RDF
17	Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi	6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.	ISSCC	2017	DBLP DOI BibTeX RDF
17	Rashmi Kamran, Nandish Bharat Thaker, Mehul Anghan, Nandakumar Nambath, Shalabh Gupta	Demonstration of a polarization diversity based SH-QPSK system with CMA-DFE equalizer.	WOCC	2017	DBLP DOI BibTeX RDF
17	Gyunam Jeon, Yong-Bin Kim	A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction.	ISCAS	2017	DBLP DOI BibTeX RDF
17	Gyunam Jeon, Yong-Bin Kim	Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate.	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
17	Minchang Kim, Jihwan Park, Joo-Hyung Chae, Hyeongjun Ko, Mino Kim, Suhwan Kim	An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface.	ISOCC	2017	DBLP DOI BibTeX RDF
17	Gyunam Jeon, Yong-Bin Kim	A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap.	ISOCC	2017	DBLP DOI BibTeX RDF
17	Daniel F. S. Fernandes, Francisco Cercas 0001, Rui Dinis 0001	Iterative Receiver Combining IB-DFE with MRC for Massive MIMO Schemes.	ANT/SEIT	2017	DBLP DOI BibTeX RDF
17	Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone	Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
17	Namik Kocaman, Tamer A. Ali 0001, Lakshmi P. Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang 0029, Afshin Momtaz	A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
17	Alireza Sharif Bakhtiar, Anthony Chan Carusone	A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
17	Yong-Hun Kim, Young-Ju Kim 0001, Taeho Lee 0001, Lee-Sup Kim	A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
17	Nevin Alex Jacob, Diego James, Bibhu Datta Sahoo 0002	Full-rate switched capacitor multi-tap DFE for long-tail post-cursor cancellation.	MWSCAS	2016	DBLP DOI BibTeX RDF
17	Chen Zhang, Gyunam Jeon, Yongsuk Choi, Yong-Bin Kim, Kyung Ki Kim	An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction.	NATW	2016	DBLP DOI BibTeX RDF
17	Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone	23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs.	ISSCC	2016	DBLP DOI BibTeX RDF
17	Mohammad Hekmat, Sanquan Song, Nancy Jaffari, Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong	23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays.	ISSCC	2016	DBLP DOI BibTeX RDF
17	Bharath Raghavan, Aida Varzaghani, Lakshmi P. Rao, Henry Park, Xiaochen Yang, Zhi Huang, Yu Chen, Rama Kattamuri, Chunhui Wu, Bo Zhang 0029, Jun Cao 0001, Afshin Momtaz, Namik Kocaman	A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
17	Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim	A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
17	Lennert Jacobs, Mamoun Guenach, Marc Moeneclaey	MIMO pre-equalization and DFE for high-speed off-chip communication.	SSD	2016	DBLP DOI BibTeX RDF
17	Pragya Maheshwari, Suhas Kaushik, Mahendra Sakare, Shalabh Gupta	A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE.	VLSID	2016	DBLP DOI BibTeX RDF
17	Naveed Iqbal 0001, Naofal Al-Dhahir, Azzedine Zerguine, Abdelmalek B. C. Zidouri	Adaptive Frequency-Domain RLS DFE for Uplink MIMO SC-FDMA.	IEEE Trans. Veh. Technol.	2015	DBLP DOI BibTeX RDF
17	Shayan Shahramian, Anthony Chan Carusone	A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
17	Zheng-Hao Hong, Yao-Chia Liu, Wei-Zen Chen	A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
17	Timothy O. Dickson, Yong Liu 0023, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman	A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
17	Shayan Shahramian, Anthony Chan Carusone	Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS".	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
17	Yong-Hun Kim, Young-Ju Kim 0001, Tae-Ho Lee 0001, Lee-Sup Kim	An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
17	Hwan-Jun Choi, Young-Hwan You, Hyoung-Kyu Song	Extended DFE Detection Scheme in MIMO-OFDM System.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2015	DBLP DOI BibTeX RDF
17	Wen Zhou, Shengli Zhang	The Decision Delay in Finite-Length MMSE-DFE Systems.	Wirel. Pers. Commun.	2015	DBLP DOI BibTeX RDF
17	Hua Wei, Yao Huang, Jiang Du 0005, Li Li	A Universal MMSE-DFE Equalizer with its Application to WLAN Receiver.	Wirel. Pers. Commun.	2015	DBLP DOI BibTeX RDF
17	Su Huang, Jun Wang 0003, Zhecheng An, Jintao Wang, Jian Song 0004	Iterative MMSE-DFE and Error Transfer for OFDM in Doubly Selective Channels.	IEEE Trans. Broadcast.	2015	DBLP DOI BibTeX RDF
17	Su Huang, Jun Wang 0003, Jintao Wang, Chao Zhang 0009, Jian Song 0004	Convergence of Frequency-Domain Iterative MF-DFE for Single-Carrier Modulation.	IEEE Trans. Commun.	2015	DBLP DOI BibTeX RDF
17	Maki Nanou, Andreas Emeretlis, Christina Tanya Politi, George Theodoridis, Kristina Georgoulakis, George-Othon Glentis	40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links.	ICTON	2015	DBLP DOI BibTeX RDF
17	Ismail Kaya, Emin Tugcu, Ali Özen, Andrew R. Nix	Fast Convergence Algorithm for Blind Channel Estimation and Equalization Using CMF-DFE.	VTC Spring	2015	DBLP DOI BibTeX RDF
17	Filipe Casal Ribeiro, Rui Dinis 0001, Francisco Cercas 0001, Adão Silva	On the Theoretical BER Performance of SC-FDE Schemes with IB-DFE Receivers.	VTC Spring	2015	DBLP DOI BibTeX RDF
17	Alaa H. Ahmed, Charalampos C. Tsimenidis, Jeffrey A. Neasham, Bayan S. Sharif	DFE for frequency selective PNC channels using AF.	WiMob	2015	DBLP DOI BibTeX RDF
17	Shuai Yuan 0005, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang 0001	A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS.	ESSCIRC	2015	DBLP DOI BibTeX RDF
17	Hazar Yueksel, Lukas Kull, Andreas Burg, Matthias Braendli, Peter Buchmann, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Danny Luu, Thomas Toifl	A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS.	ESSCIRC	2015	DBLP DOI BibTeX RDF
17	Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim	17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces.	ISSCC	2015	DBLP DOI BibTeX RDF
17	Takashi Kawamoto, Takayasu Norimatsu, Kenji Kogo, Fumio Yuki, Norio Nakajima, Masatoshi Tsuge, Tatsunori Usugi, Tomofumi Hokari, Hideki Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Jun Kumazawa, Hiroaki Kurahashi, Takashi Muto, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta	3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.	ISSCC	2015	DBLP DOI BibTeX RDF
17	Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu	10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver.	ISSCC	2015	DBLP DOI BibTeX RDF
17	Hyun-Wook Lim, Sung-Won Choi, Sang-Kyu Lee, Chang-Hoon Baek, Jae-Youl Lee, Gyoo-Cheol Hwang, Bai-Sun Kong, Young-Hyun Jun	10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface.	ISSCC	2015	DBLP DOI BibTeX RDF
17	Alireza Sharif Bakhtiar, Anthony Chan Carusone	A 19.6-Gbps CMOS optical receiver with local feedback IIR DFE.	VLSIC	2015	DBLP DOI BibTeX RDF
17	Tamer A. Ali 0001, Lakshmi P. Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang 0029, Afshin Momtaz, Namik Kocaman	A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS.	VLSIC	2015	DBLP DOI BibTeX RDF
17	Osama Elhadidy, Ashkan Roshan-Zamir, Hae-Woong Yang, Samuel Palermo	A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS.	VLSIC	2015	DBLP DOI BibTeX RDF
17	Roberto Magueta, Adão Silva, Rui Dinis 0001, Atílio Gameiro	IB-DFE based equalizer for constant envelop OFDM systems.	ConTEL	2015	DBLP DOI BibTeX RDF
17	Minseo Kim, Joonsung Bae, Unsoo Ha, Hoi-Jun Yoo	A 24-mW 28-Gb/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE.	ISCAS	2015	DBLP DOI BibTeX RDF
17	Ignatio Madanhire, Charles Mbohwa	Potential for improving performance through design for environment (DFE) in a ferrous foundry.	IEEM	2015	DBLP DOI BibTeX RDF
17	Shiunn-Jang Chern, Kelvin Kuang-Chi Lee, Yun-Kai Bai, Richard Hsin-Hsyong Yang	Semi-blind channel estimation scheme with Bayesian DFE for PRP-OFDM system.	ISPACS	2015	DBLP DOI BibTeX RDF
17	Khalid Mahmood, Syed Muhammad Asad, Azzedine Zerguine, Muhammad Moinuddin	MAI plus noise-constrained LMS-based algorithm for MIMO-CDMA DFE systems.	SSD	2015	DBLP DOI BibTeX RDF
17	Andreas Emeretlis, V. Kefelouras, George Theodoridis, Maki Nanou, Christina Tanya Politi, Kristina Georgoulakis, George-Othon Glentis	FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links.	EUSIPCO	2015	DBLP DOI BibTeX RDF
17	Hela Jedda, Leonardo Gomes Baltar, Oliver De Candido, Amine Mezghani, Josef A. Nossek	DFE/THP duality for FBMC with highly frequency selective channels.	EUSIPCO	2015	DBLP DOI BibTeX RDF
17	Ehsan Zhian Tabasy, Ayman Shafik, Keytaek Lee, Sebastian Hoyos, Samuel Palermo	A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
17	Pier Andrea Francese, Thomas Toifl, Peter Buchmann, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen	A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
17	Tawfiq Musah, James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Gokce Keskin, Sudip Shekhar, Joseph T. Kennedy, Shreyas Sen, Rajesh Inti, Mozhgan Mansuri, Michael Leddige, Bryce Horine, Clark Roberts, Randy Mooney, Bryan Casper	A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
17	Vishnu Balan, Olakanmi Oluwole, Gregory Kodani, Charlie Zhong, Ratnakar Dadi, Arif Amin, Ahmed Ragab, Ming-Ju Edward Lee	A 15-22 Gbps Serial Link in 28 nm CMOS With Direct DFE.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
17	Dumidu Wijayasekara, Ondrej Linda, Milos Manic, Craig Rieger	FN-DFE: Fuzzy-Neural Data Fusion Engine for Enhanced Resilient State-Awareness of Hybrid Energy Systems.	IEEE Trans. Cybern.	2014	DBLP DOI BibTeX RDF
17	Simon Järmyr, Björn E. Ottersten, Eduard A. Jorswieck	Statistical Framework for Optimization in the Multi-User MIMO Uplink With ZF-DFE.	IEEE Trans. Signal Process.	2014	DBLP DOI BibTeX RDF
17	Seok Kim, Eun-Young Jin, Kee-Won Kwon, Jintae Kim, Jung-Hoon Chun	A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
17	Baskaran Dhivagar, Kiran Kuchi, Krishnamurthy Giridhar	An Iterative DFE Receiver for MIMO SC-FDMA Uplink.	IEEE Commun. Lett.	2014	DBLP DOI BibTeX RDF
17	Ahmed Ismail, Sameh Ibrahim, Mohamed Dessouky	A 8 Gbps 0.67mW 1 tap current integrating DFE in 40nm CMOS.	MWSCAS	2014	DBLP DOI BibTeX RDF
17	Zilong Zhang, Xiaodong Xu 0004, Baisheng Du, Zhiyong Chen 0003	A Novel Precoder Design for MIMO Multicasting with MMSE-DFE Receivers.	VTC Fall	2014	DBLP DOI BibTeX RDF
17	Paulo Montezuma, Daniel Marques, Rui Dinis 0001	qLow complexity LDPC coded IB-DFE for multilevel modulations and coded OFDM: comparison and complexity trade-offs.	TEMU	2014	DBLP DOI BibTeX RDF
17	Naveed Iqbal 0001, Azzedine Zerguine, Naofal Al-Dhahir	RLS-based frequency-domain DFE for uplink SC-FDMA.	ACSSC	2014	DBLP DOI BibTeX RDF
17	Shayan Shahramian, Anthony Chan Carusone	A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
17	José Assunção, Adão Silva, Rui Dinis 0001, Atílio Gameiro	IB-DFE-based receivers for MC-CDMA systems with interference alignment.	ISCC	2014	DBLP DOI BibTeX RDF
17	S. N. Qader, Charalampos C. Tsimenidis, Martin Johnston, Bayan S. Sharif	Optimization of iterative DFE-IDMA detection for multipath fading channels.	WCNC	2014	DBLP DOI BibTeX RDF
17	Nevin Alex Jacob, Vikas Choudhary, Bibhudatta Sahoo 0002	A multi-pole single-tap IIR based DFE equalizer topology.	NEWCAS	2014	DBLP DOI BibTeX RDF
17	Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura	A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE.	CICC	2014	DBLP DOI BibTeX RDF
17	Timothy O. Dickson, Yong Liu 0023, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman	A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.	CICC	2014	DBLP DOI BibTeX RDF
17	B. Branco, Francisco Ganhão, Luis Irio, Luís Bernardo, Rui Dinis 0001, Rodolfo Oliveira, Pedro Amaral, Paulo Pinto	SC-FDE femtocell energy saving using IB-DFE Interference Cancellation techniques.	ICT	2014	DBLP DOI BibTeX RDF
17	James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Tawfiq Musah, Gökçe Keskin, Sudip Shekhar, Joseph T. Kennedy, Shreyas Sen, Rajesh Inti, Mozhgan Mansuri, Michael Leddige, Bryce Horine, Clark Roberts, Randy Mooney, Bryan Casper	26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS.	ISSCC	2014	DBLP DOI BibTeX RDF
17	Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura	A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.	VLSIC	2014	DBLP DOI BibTeX RDF
17	Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura	A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.	VLSIC	2014	DBLP DOI BibTeX RDF
17	Pervez M. Aziz, Hiroshi Kimura, Amaresh V. Malipatil, Shiva Kotagiri, Gordon Chan, Hairong Gao	Shift register multi-phase clock based downsampled floating tap DFE for serial links.	ISCAS	2014	DBLP DOI BibTeX RDF
17	Zheng-Hao Hong, Wei-Zen Chen	A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery.	A-SSCC	2014	DBLP DOI BibTeX RDF
17	Alicia Joao, José Assunção, Adão Silva, Rui Dinis 0001, Atílio Gameiro	IB-DFE SIC based receiver structure for IA-precoded MC-CDMA systems.	EUSIPCO	2014	DBLP BibTeX RDF
17	Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura	A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
17	Shih-Yuan Kao, Shen-Iuan Liu	A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
17	Ehsan Zhian Tabasy, Ayman Shafik, Shan Huang, Noah Hae-Woong Yang, Sebastian Hoyos, Samuel Palermo	A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
17	Tsutomu Takeya, Tadahiro Kuroda	Symbol-Rate Clock Recovery for Integrating DFE Receivers.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2013	DBLP DOI BibTeX RDF
17	Adão Silva, José Assunção, Rui Dinis 0001, Atílio Gameiro	Performance evaluation of IB-DFE-based strategies for SC-FDMA systems.	EURASIP J. Wirel. Commun. Netw.	2013	DBLP DOI BibTeX RDF
17	Amanda de Paula, Cristiano Panazio	Comparison of OFDM and SC-DFE Capacities Without Channel Knowledge at the Transmitter.	CoRR	2013	DBLP BibTeX RDF
17	Chih-Hao Liu, P. P. Vaidyanathan	MIMO Broadcast DFE Transceivers With QoS Constraints: Min-Power and Max-Rate Solutions.	IEEE Trans. Signal Process.	2013	DBLP DOI BibTeX RDF