Search results for "fat-tree"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Sajal K. Das 0001, Sabine R. Öhring, Maximilian Ibel	Communication aspects of fat-tree-based interconnection networks for multicomputers.	Robust Communication Networks: Interconnection and Survivability	1998	DBLP DOI BibTeX RDF
20	Young-Sik Kim, Oh-Young Kwon, Tack-Don Han, Youngsong Mun	Design and performance analysis of the Practical Fat Tree Network using a butterfly network.	J. Syst. Archit.	1997	DBLP BibTeX RDF
20	Kieran T. Herley, Andrea Pietracaprina, Geppino Pucci	Implementing Shared Memory on Mult-Dimensional Meshes and on the Fat-Tree (Extended Abstract).	ESA	1995	DBLP DOI BibTeX RDF
20	Tong J. Lee, Franklin T. Luk, Daniel Boley	Singular Value Decomposition on a 2-D Fat-Tree Architecture.	PPSC	1993	DBLP BibTeX RDF
19	Román García, Manuel P. Malumbres, Julio Pons Terol	Gigabit Ethernet Backbones with Active Loops.	ICPP	2001	DBLP DOI BibTeX RDF
17	Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez	Efficient tree topology for FPGA interconnect network.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	fpga, routing, interconnect, hierarchy, rent's rule
17	Vassilios V. Dimakopoulos, Nikitas J. Dimopoulos	Leaf Communications in Complete Trees.	Euro-Par, Vol. I	1996	DBLP DOI BibTeX RDF
15	Zheng Cao, Jianwei Xu, Mingyu Chen 0001, Gui Zheng, Huiwei Lv, Ninghui Sun	HPPNetSim: a parallel simulation of large-scale interconnection networks.	SpringSim	2009	DBLP DOI BibTeX RDF	conservative approach, large-scale interconnection network, super-linear speedup, parallel discrete event simulation
15	Oreste Villa, Gianluca Palermo, Cristina Silvano	Efficiency and scalability of barrier synchronization on NoC based many-core architectures.	CASES	2008	DBLP DOI BibTeX RDF	scalability, synchronization, efficiency, Multicore, NoC, barrier, Manycore
15	Vinod Viswanath	Multi-log Processor - Towards Scalable Event-Driven Multiprocessors.	DSD	2004	DBLP DOI BibTeX RDF
15	Dana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath	The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture.	ARVLSI	1999	DBLP DOI BibTeX RDF
13	Yitzhak Birk, Vladimir Zdornov	Improving communication-phase completion times in HPC clusters through congestion mitigation.	SYSTOR	2009	DBLP DOI BibTeX RDF	congestion control, interconnects, adaptive routing, congestion, InfiniBand, computer clusters
13	Hojjat Sharifi, Mohammad Kazem Akbari, Bahman Javadi	An Analytical Model of Communication Networks in Multi-cluster Systems in the Presence of Non-uniform Traffic.	CSE (1)	2009	DBLP DOI BibTeX RDF
13	Zied Marrakchi, Hayder Mrabet, Habib Mehrez	A new Multilevel Hierarchical MFPGA and its suitable configuration tools.	ISVLSI	2006	DBLP DOI BibTeX RDF
13	Zied Marrakchi, Hayder Mrabet, Habib Mehrez	Configuration tools for a new multilevel hierarchical FPGA.	FPGA	2006	DBLP DOI BibTeX RDF
13	Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez	A multilevel hierarchical interconnection structure for FPGA.	FPGA	2006	DBLP DOI BibTeX RDF
13	Heikki Kariniemi, Jari Nurmi	On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips.	FPL	2006	DBLP DOI BibTeX RDF
13	Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez	Performances improvement of FPGA using novel multilevel hierarchical interconnection structure.	ICCAD	2006	DBLP DOI BibTeX RDF
13	Frank Olaf Sem-Jacobsen, Tor Skeie, Olav Lysne, José Duato	Dynamic Fault Tolerance with Misrouting in Fat Trees.	ICPP	2006	DBLP DOI BibTeX RDF
13	Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi	Designing On-Chip Network Based on Optimal Latency Criteria.	ICESS	2005	DBLP DOI BibTeX RDF
13	Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi	Realization of Video Object Plane Decoder on On-Chip Network Architecture.	ICESS	2005	DBLP DOI BibTeX RDF
13	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar	H.264 HDTV Decoder Using Application-Specific Networks-On-Chip.	ICME	2005	DBLP DOI BibTeX RDF
13	John Shalf, Shoaib Kamil 0001, Leonid Oliker, David Skinner	Analyzing Ultra-Scale Application Communication Requirements for a Reconfigurable Hybrid Interconnect.	SC	2005	DBLP DOI BibTeX RDF
13	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	BFT, scalability, pipelining, bus, MP-SoC
13	Zheng Zhang 0001	The Power of DHT as a Logical Space.	FTDCS	2004	DBLP DOI BibTeX RDF
13	Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh	Design of a switch for network on chip applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
13	Jeremy Brown, J. P. Grossman, Tom Knight	A lightweight idempotent messaging protocol for faulty networks.	SPAA	2002	DBLP DOI BibTeX RDF	block-structured traces, source-reliable messaging, idempotence
13	Peter R. Cappello, Dimitros Mourloukos	A scalable, robust network for parallel computing.	Java Grande	2001	DBLP DOI BibTeX RDF	Java, scalable, parallel processing, robust, network computing
13	G. Andrew Boughton	Arctic Switch Fabric.	PCRCW	1997	DBLP DOI BibTeX RDF
13	Robert W. Horst	ServerNet Deadlock Avoidance and Fractahedral Topologies.	IPPS	1996	DBLP DOI BibTeX RDF	scalable topologies, fractahedral topologies, maximum link contention, 6-port ServerNet routers, performance evaluation, concurrency control, hypercube, mesh, multistage interconnection networks, network routing, deadlock avoidance, multistage networks, deadlock-free
13	Shimon Even, Ami Litman	A Unified Scheme for Routing in Expander Based Networks.	CIAC	1994	DBLP DOI BibTeX RDF