Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Rasha Montaser, Ahmed Younes, Mahmoud A. Abdel-Aty |
New Design of Reversible Full Adder/Subtractor using R gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1708.00306, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
20 | Ramin Rajaei |
Highly reliable and low-power magnetic full-adder designs for nanoscale technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 73, pp. 129-135, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Kamela C. Rahman, Masoodur Rahman Khan, Marek A. Perkowski |
Memristor based 8-bit iterative full adder with space-time notation and sneak-path protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 695-698, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Giane Ulloa, Vinicius Lucena, Cristina Meinhardt |
Comparing 32nm full adder TMR and DTMR architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017, pp. 294-297, 2017, IEEE, 978-1-5386-1911-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Xiaoping Wang 0001, Ran Yang, Qiao Chen, Zhigang Zeng |
An improved memristor-CMOS XOR logic gate and a novel full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACI ![In: Ninth International Conference on Advanced Computational Intelligence, ICACI 2017, Doha, Qatar, February 4-6, 2017, pp. 7-11, 2017, IEEE, 978-1-5090-4726-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | K. S. Jitendra, Avireni Srinivasulu, Brahmadeo Prasad Singh |
A new low-power full-adder cell for low voltage using CNTFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECAI ![In: 9th International Conference on Electronics, Computers and Artificial Intelligence, ECAI 2017, Targoviste, Romania, June 29 - July 1, 2017, pp. 1-5, 2017, IEEE, 978-1-5090-6457-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Poorna Marthi, Nazir Hossain, Huan Wang 0009, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González |
A high performance Full Adder based on Ballistic Deflection Transistor technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Javad Talafy, Hamid R. Zarandi |
Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, Thessaloniki, Greece, July 3-5, 2017, pp. 207-208, 2017, IEEE, 978-1-5386-0352-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Kuimin Zhang, Xiaole Cui, Xiaoxin Cui |
A design of high performance full adder with memristors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 746-479, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Subhendu Kumar Sahoo, Gangishetty Akhilesh, Rasmita Sahoo |
Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017, pp. 46-49, 2017, IEEE, 978-1-5386-1356-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Shokat Ganjeheizadeh Rohani, Nima Taherinejad |
An improved algorithm for IMPLY logic based memristive Full-adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 30th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2017, Windsor, ON, Canada, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5538-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Ramanand Jaiswal, Trailokya Nath Sasamal |
Efficient design of full adder and subtractor using 5-input majority gate in QCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC3 ![In: Tenth International Conference on Contemporary Computing, IC3 2017, Noida, India, August 10-12, 2017, pp. 1-6, 2017, IEEE Computer Society, 978-1-5386-3077-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Fereshteh Jafarzadehpour, Peiman Keshavarzian |
Low-power consumption ternary full adder based on CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 10(5), pp. 365-374, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Mohammad Mohammadi, Majid Mohammadi, Saeid Gorgin 0001 |
An efficient design of full adder in quantum-dot cellular automata (QCA) technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 50, pp. 35-43, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Mohammad Hossein Moaiyeri, Elham Taherkhani, Shaahin Angizi |
A Novel Efficient Reversible Full Adder-Subtractor in QCA Nanotechnology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1610.09473, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
20 | Sankit R. Kassa, Rajendra Kumar Nagaria |
An Innovative Low Power Full Adder Design in Nano Technology Based Quantum Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 12(2), pp. 107-111, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Jiwanjot Kahlon, Pradeep Kumar 0006, Anubhav Garg, Ashutosh Gupta 0002 |
Low power and temperature compatible FinFET based full adder circuit with optimised area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2016 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2016, Jaipur, India, September 21-24, 2016, pp. 2121-2125, 2016, IEEE, 978-1-5090-2029-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Chauhan Sugandha, Sharma Tripti |
Low Power 14T Hybrid Full Adder Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FICTA (2) ![In: Proceedings of the 5th International Conference on Frontiers in Intelligent Computing: Theory and Applications - FICTA 2016, Bhubaneswar, Odisa, India, Volume 2, pp. 151-160, 2016, Springer, 978-981-10-3155-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Akshay Bhaskar, Dheeraj Reddy, Shabhari Saravanan, K. Jagannadha Naidu |
A low power and high speed 10 transistor full adder using multi threshold technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIIS ![In: 11th International Conference on Industrial and Information Systems, ICIIS 2016, Roorkee, India, December 3-4, 2016, pp. 371-374, 2016, IEEE, 978-1-5090-3818-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Shailesh Dwivedi, Kavita Khare, Ajay Kumar Dadoria |
Low-Power High Speed 1-bit Full Adder Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTCS ![In: ICTCS, pp. 106:1-106:5, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Hao Cai, You Wang 0002, Lirida A. B. Naviner, Zhaohao Wang, Weisheng Zhao |
Approximate computing in MOS/spintronic non-volatile full-adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016, Beijing, China, July 18-20, 2016, pp. 203-208, 2016, ACM, 978-1-4503-4330-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Manan Mewada, Mazad Zaveri |
A low-power high-speed hybrid full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-1422-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar, Anup Dandapat |
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(10), pp. 2001-2008, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Mohammad Eshghi |
A novel low-energy CNFET-based full adder cell using pass-transistor logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 5(4), pp. 193-201, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Somaye Mohammadyan, Shaahin Angizi, Keivan Navi |
New fully single layer QCA full-adder cell based on feedback model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 5(4), pp. 202-208, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Yavar Safaei Mehrabani, Mohammad Eshghi |
A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 34(3), pp. 739-759, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Yavar Safaei Mehrabani, Mohammad Eshghi |
Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 34(3), pp. 761, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Vishesh Dokania, Aminul Islam 0002 |
Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 9(3), pp. 204-212, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Razieh Farazkish, Fatemeh Khodaparast 0001 |
Design and characterization of a new fault-tolerant full-adder for quantum-dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 39(6), pp. 426-433, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Yavar Safaei Mehrabani, Mohammad Eshghi |
High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(9), pp. 1550130:1-1550130:24, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Majid Haghparast, Soghra Shoaei |
Design of a New Parity Preserving Reversible Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(1), pp. 1550006:1-1550006:11, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Arman Roohi, Ronald F. DeMara, Navid Khoshavi |
Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 46(6), pp. 531-542, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Andrew Adamatzky |
Binary full adder, made of fusion gates, in sub-excitable Belousov-Zhabotinsky system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1506.08399, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
20 | Mehri Teimoory, Amirali Amirsoleimani, Jafar Shamsi, Arash Ahmadi, Shahpour Alirezaee, Majid Ahmadi |
Optimized Implementation of Memristor-Based Full Adder by Material Implication Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1501.00606, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
20 | Ella Gale |
Single Memristor Logic Gates: From NOT to a Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1510.05705, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
20 | Shaahin Angizi, Fahimeh Danehdaran, Soheil Sarmadi, Shadi Sheikhfaal, Nader Bagherzadeh, Keivan Navi |
An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 11(2), pp. 173-180, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Erya Deng, Yue Zhang 0010, Wang Kang 0001, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao |
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7), pp. 1757-1765, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Kejie Huang, Rong Zhao, Yong Lian 0001 |
A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4), pp. 1109-1116, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Erya Deng, You Wang 0002, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat, Weisheng Zhao |
Robust magnetic full-adder with voltage sensing 2T/2MTJ cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015, pp. 27-32, 2015, IEEE Computer Society, 978-1-4673-7849-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Qi An, Li Su, Jacques-Olivier Klein, Sébastien Le Beux, Ian O'Connor, Weisheng Zhao |
Full-adder circuit design based on all-spin logic device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015, pp. 163-168, 2015, IEEE Computer Society, 978-1-4673-7849-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Biswarup Mukherjee 0003, Aniruddha Ghosal |
Design & study of a low power high speed full adder using GDI multiplexer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReTIS ![In: 2nd IEEE International Conference on Recent Trends in Information Systems, ReTIS 2015, Kolkata, India, July 9-11, 2015, pp. 465-470, 2015, IEEE, 978-1-4799-8349-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Sneh Lata Murotiya, Anu Gupta |
Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015, pp. 292-297, 2015, IEEE Computer Society, 978-1-4799-6658-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Rishika Sethi, Gaurav Soni |
Comparative Analysis of Si-MOSFET and CNFET-Based 28T Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SocProS (1) ![In: Proceedings of Fifth International Conference on Soft Computing for Problem Solving - SocProS 2015, Volume 1, Saharanpur, Uttar Pradesh, India, December 18-20, 2015., pp. 439-451, 2015, Springer, 978-981-10-0447-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Vahid Foroutan, MohammadReza Taheri, Keivan Navi, Arash Azizi Mazreah |
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 47(1), pp. 48-61, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | R. M. Bommi, S. Selvakumar Raja |
All optical Implementation of High Speed and low Power Reversible Full Adder using semiconductor optical amplifier based Mach-Zehnder Interferometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. ![In: J. Comput. Sci. 10(7), pp. 1130-1134, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Peiman Keshavarzian, Rahil Sarikhani |
A Novel CNTFET-based Ternary Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 33(3), pp. 665-679, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Raghvendra Singh, Shyam Akashe |
Modeling and Analysis of Low Power 10 T Full Adder with Reduced Ground Bounce noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 23(1), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Ali Ghorbani, Ghazaleh Ghorbani |
Energy Efficient Full Adder Cell Design With Using Carbon Nanotube Field Effect Transistors In 32 Nanometer Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1411.2088, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
20 | Mehdi Masoudi, Milad Mazaheri, Aliakbar Rezaei, Keivan Navi |
Designing high-speed, low-power full adder cells based on carbon nanotube technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1411.2212, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
20 | Bahniman Ghosh, A. Ajay |
2-Bit Full Adder Implementation Using Single Spin Logic Paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 10(2), pp. 214-219, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Nehru Kandasamy, A. Shanmugam |
Design of high-performance low-power full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Appl. Technol. ![In: Int. J. Comput. Appl. Technol. 49(2), pp. 134-140, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Zahra Mohammadi, Majid Mohammadi |
Implementing a one-bit reversible full adder using quantum-dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Quantum Inf. Process. ![In: Quantum Inf. Process. 13(9), pp. 2127-2147, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Robert Perricone, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier |
Design of 3D nanomagnetic logic circuits: A full-adder case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, pp. 1-6, 2014, European Design and Automation Association, 978-3-9815370-2-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Mehri Teimoory, Amirali Amirsoleimani, Jafar Shamsi, Arash Ahmadi, Shahpour Alirezaee, Majid Ahmadi |
Optimized implementation of memristor-based full adder by material implication logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, pp. 562-565, 2014, IEEE, 978-1-4799-4242-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | A. Kishore Kumar, D. Somasundareswari, V. Duraisamy, T. Shunbaga Pradeepa |
Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2013, pp. 157872:1-157872:9, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh |
A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 4(4), pp. 196-203, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Karthik Reddy G |
Low power-area designs of 1bit full adder in cadence virtuoso platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1309.2458, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
20 | Bahniman Ghosh, Chandramauli Singh, Akshay Kumar Salimath |
A Novel Approach of Full Adder and Arithmetic Logic Unit Design in Quantum Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 9(4), pp. 452-457, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Azadeh Safari, James Nugent, Yinan Kong |
Novel implementation of full adder based scaling in Residue Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 657-660, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Narasimha Rao Konijeti, J. V. R. Ravindra, Pandurangaiah Yagateela |
Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMS ![In: Seventh UKSim/AMSS European Modelling Symposium, EMS 2013, 20-22 November, 2013, Manchester UK, pp. 697-700, 2013, IEEE, 978-1-4799-2578-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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20 | Gangadhar Reddy Ramireddy, J. V. R. Ravindra, Harikrishna Kamatham |
Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMS ![In: Seventh UKSim/AMSS European Modelling Symposium, EMS 2013, 20-22 November, 2013, Manchester UK, pp. 691-696, 2013, IEEE, 978-1-4799-2578-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Yue Zhang 0010, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller |
Synchronous full-adder based on complementary resistive switching memory cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, Paris, France, June 16-19, 2013, pp. 1-4, 2013, IEEE, 978-1-4799-0618-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Xiaobao Chen, Zuocheng Xing, Bingcai Sui |
A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCCET ![In: Computer Engineering and Technology - 17th CCF Conference, NCCET 2013, Xining, China, July 20-22, 2013. Revised Selected Papers, pp. 244-250, 2013, Springer, 978-3-642-41634-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Ireneusz Brzozowski, Damian Palys, Andrzej Kos |
An analysis of full adder cells for low-power data oriented adders design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, Gdynia, Poland, June 20-22, 2013, pp. 346-351, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
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20 | Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari |
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2012, pp. 173079:1-173079:18, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Shiwani Singh, Tripti Sharma, K. G. Sharma, B. P. Singh |
9T Full Adder Design in Subthreshold Region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2012, pp. 248347:1-248347:5, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Sohan Purohit, Martin Margala |
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(7), pp. 1327-1331, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Mohammad Reza Reshadinezhad, Mohammad Hossein Moaiyeri, Keivan Navi |
An Energy-Efficient Full Adder Cell Using CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 95-C(4), pp. 744-751, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Mahdiar Hosein Ghadiry, Mahdieh Nadi Senjani, Hosein Mohammadi, Asrulnizam Bin Abd Manaf |
Analysis of a Novel Full Adder Designed for Implementing in Carbone nanotube Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 21(5), 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Mehdi Ghasemi, Mohammad Hossein Moaiyeri, Keivan Navi |
A New Full Adder Cell for Molecular Electronics ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1201.2043, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
20 | Manoj Kumar 0005, Sandeep Kumar Arya, Sujata Pandey |
Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1201.1966, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
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20 | Gajula Ramana Murthy, Chinnaiyan Senthilpari, Pitchandi Velrajkumar, Tien Sze Lim |
A new 6-T multiplexer based full-adder for low power and leakage current optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 9(17), pp. 1434-1441, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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20 | Kamran Delfan Hemmati, Mojtaba Behzad Fallahpour, Abbas Golmakani, Kamyar Delfan Hemmati |
A high-speed hybrid Full Adder with low power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 9(24), pp. 1900-1905, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar |
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: International Symposium on Electronic System Design, ISEDs 2012, Kolkata, India, December 19-22, 2012, pp. 130-134, 2012, IEEE, 978-1-4673-4704-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Manoj Kumar 0005 |
Design of 9-transistor single bit full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCSEIT ![In: The Second International Conference on Computational Science, Engineering and Information Technology, CCSEIT '12, Coimbatore, India, October 26-28, 2012, pp. 337-340, 2012, ACM, 978-1-4503-1310-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
Low power 10-transistor full adder design based on degenerate pass transistor logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 496-499, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Richa Saraswat, Shyam Akashe, Shyam Babu |
Analysis and Simulation of Full Adder Design Using MTCMOS Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIC-TA (2) ![In: Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012) - Volume 2, pp. 189-198, 2012, Springer, 978-81-322-1040-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Yi Wei, Jizhong Shen |
Design of a novel low power 8-transistor 1-bit full adder cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Zhejiang Univ. Sci. C ![In: J. Zhejiang Univ. Sci. C 12(7), pp. 604-607, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Keivan Navi, Horialsadat Hossein Sajedi, Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Ali Jalali, Omid Kavehei |
High-speed full adder based on minority function and bridge style for nanoscale. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 44(3), pp. 155-162, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Hamid Khorsand, Keivan Navi |
A New Robust and High-Performance Hybrid Full Adder Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 20(4), pp. 641-655, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Mahdiar Hosein Ghadiry, Abu Khari A'Ain, Mahdieh Nadi Senjani |
Design and Analysis of a Novel Low PDP Full Adder Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 20(3), pp. 439-445, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Sunil Gavaskar Reddy, Rajendra Prasad |
Power comparison of CMOS and adiabatic full adder circuit ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1110.1549, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
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20 | Ashkan Khatir, Shaghayegh Abdolahzadegan, Iman Mahmoudi |
High Speed Multiple Valued Logic Full Adder Using Carbon Nano Tube Field Effect Transistor ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1104.0298, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
20 | Lixin Gao |
High performance Complementary Pass transistor Logic full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMEIT ![In: International Conference on Electronic and Mechanical Engineering and Information Technology, EMEIT 2011, Harbin, Heilongjiang, China, 12-14 August, 2011, pp. 4306-4309, 2011, IEEE, 978-1-61284-087-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Mallikarjuna Rao Nimmagadda, Ajit Pal |
Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India, pp. 345-346, 2011, IEEE Computer Society, 978-0-7695-4447-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | David J. Willingham, Izzet Kale |
A Ternary Adiabatic Logic (TAL) implementation of a four-trit Full-Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, pp. 1-4, 2011, IEEE, 978-1-4577-0514-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Mohammad Javad Zavarei, Mohammad Reza Baghbanmanesh, Ehsan Kargaran, Hooman Nabovati, Abbas Golmakani |
Design of new full adder cell using hybrid-CMOS logic style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 451-454, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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20 | Iftekhar Ibne Basith, Tareq Muhammad Supon, Ajit Muhury, Rashid Rashidzadeh, Majid Ahmadi |
Performance enhancement of single electron junction 1-bit full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 157-160, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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20 | Sayyed Hasan Mozafari, Mahdi Fazeli, Shaahin Hessabi, Seyed Ghassem Miremadi |
A Low Cost circuit level fault detection technique to Full Adder design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 446-450, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Yngvar Berg |
Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011, Tuusula, Finland, May 23-25, 2011, pp. 259-262, 2011, IEEE Computer Society, 978-0-7695-4405-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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20 | Keivan Navi, Fazel Sharifi, Amir Momeni, Peiman Keshavarzian |
Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 93-C(6), pp. 932-934, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Keivan Navi, Razieh Farazkish, Samira Sayedsalehi, Mostafa Rahimi Azghadi |
A new quantum-dot cellular automata full-adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 41(12), pp. 820-826, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Md. Saiful Islam 0003 |
A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1008.3533, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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20 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Realization of a Novel Fault Tolerant Reversible Full Adder Circuit in Nanotechnology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. Arab J. Inf. Technol. ![In: Int. Arab J. Inf. Technol. 7(3), pp. 317-323, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
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20 | Sohan Purohit, Marco Lanuzza, Martin Margala |
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 6(4), pp. 469-481, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Kiran K. Chaddha, Rajeevan Chandel |
Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 6(4), pp. 482-490, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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20 | Ilham Hassoune, Denis Flandre, Ian O'Connor, Jean-Didier Legat |
ULPFA: A New Efficient Design of a Power-Aware Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8), pp. 2066-2074, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Keivan Navi, Mehrdad Maeen, Vahid Foroutan, Somayeh Timarchi, Omid Kavehei |
A novel low-power full-adder cell for low voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 42(4), pp. 457-467, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Jeong Beom Kim |
Current Mode CMOS Quaternary Logic Full-Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 18(1), pp. 199-208, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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20 | Keivan Navi, Vahid Foroutan, Mostafa Rahimi Azghadi, Mehrdad Maeen, Maryam Ebrahimpour, M. Kaveh, Omid Kavehei |
A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 40(10), pp. 1441-1448, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|