Search results for "full-adder"

Hits ?▲	Authors	Title	Venue	Year	Link
20	Rasha Montaser, Ahmed Younes, Mahmoud A. Abdel-Aty	New Design of Reversible Full Adder/Subtractor using R gate.	CoRR	2017	DBLP BibTeX RDF
20	Ramin Rajaei	Highly reliable and low-power magnetic full-adder designs for nanoscale technologies.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
20	Kamela C. Rahman, Masoodur Rahman Khan, Marek A. Perkowski	Memristor based 8-bit iterative full adder with space-time notation and sneak-path protection.	MWSCAS	2017	DBLP DOI BibTeX RDF
20	Giane Ulloa, Vinicius Lucena, Cristina Meinhardt	Comparing 32nm full adder TMR and DTMR architectures.	ICECS	2017	DBLP DOI BibTeX RDF
20	Xiaoping Wang 0001, Ran Yang, Qiao Chen, Zhigang Zeng	An improved memristor-CMOS XOR logic gate and a novel full adder.	ICACI	2017	DBLP DOI BibTeX RDF
20	K. S. Jitendra, Avireni Srinivasulu, Brahmadeo Prasad Singh	A new low-power full-adder cell for low voltage using CNTFETs.	ECAI	2017	DBLP DOI BibTeX RDF
20	Poorna Marthi, Nazir Hossain, Huan Wang 0009, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González	A high performance Full Adder based on Ballistic Deflection Transistor technology.	ISCAS	2017	DBLP DOI BibTeX RDF
20	Javad Talafy, Hamid R. Zarandi	Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution.	IOLTS	2017	DBLP DOI BibTeX RDF
20	Kuimin Zhang, Xiaole Cui, Xiaoxin Cui	A design of high performance full adder with memristors.	ASICON	2017	DBLP DOI BibTeX RDF
20	Subhendu Kumar Sahoo, Gangishetty Akhilesh, Rasmita Sahoo	Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET.	iNIS	2017	DBLP DOI BibTeX RDF
20	Shokat Ganjeheizadeh Rohani, Nima Taherinejad	An improved algorithm for IMPLY logic based memristive Full-adder.	CCECE	2017	DBLP DOI BibTeX RDF
20	Ramanand Jaiswal, Trailokya Nath Sasamal	Efficient design of full adder and subtractor using 5-input majority gate in QCA.	IC3	2017	DBLP DOI BibTeX RDF
20	Fereshteh Jafarzadehpour, Peiman Keshavarzian	Low-power consumption ternary full adder based on CNTFET.	IET Circuits Devices Syst.	2016	DBLP DOI BibTeX RDF
20	Mohammad Mohammadi, Majid Mohammadi, Saeid Gorgin 0001	An efficient design of full adder in quantum-dot cellular automata (QCA) technology.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
20	Mohammad Hossein Moaiyeri, Elham Taherkhani, Shaahin Angizi	A Novel Efficient Reversible Full Adder-Subtractor in QCA Nanotechnology.	CoRR	2016	DBLP BibTeX RDF
20	Sankit R. Kassa, Rajendra Kumar Nagaria	An Innovative Low Power Full Adder Design in Nano Technology Based Quantum Dot Cellular Automata.	J. Low Power Electron.	2016	DBLP DOI BibTeX RDF
20	Jiwanjot Kahlon, Pradeep Kumar 0006, Anubhav Garg, Ashutosh Gupta 0002	Low power and temperature compatible FinFET based full adder circuit with optimised area.	ICACCI	2016	DBLP DOI BibTeX RDF
20	Chauhan Sugandha, Sharma Tripti	Low Power 14T Hybrid Full Adder Cell.	FICTA (2)	2016	DBLP DOI BibTeX RDF
20	Akshay Bhaskar, Dheeraj Reddy, Shabhari Saravanan, K. Jagannadha Naidu	A low power and high speed 10 transistor full adder using multi threshold technique.	ICIIS	2016	DBLP DOI BibTeX RDF
20	Shailesh Dwivedi, Kavita Khare, Ajay Kumar Dadoria	Low-Power High Speed 1-bit Full Adder Circuit Design.	ICTCS	2016	DBLP DOI BibTeX RDF
20	Hao Cai, You Wang 0002, Lirida A. B. Naviner, Zhaohao Wang, Weisheng Zhao	Approximate computing in MOS/spintronic non-volatile full-adder.	NANOARCH	2016	DBLP DOI BibTeX RDF
20	Manan Mewada, Mazad Zaveri	A low-power high-speed hybrid full adder.	VDAT	2016	DBLP DOI BibTeX RDF
20	Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar, Anup Dandapat	Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
20	Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Mohammad Eshghi	A novel low-energy CNFET-based full adder cell using pass-transistor logic.	Int. J. High Perform. Syst. Archit.	2015	DBLP DOI BibTeX RDF
20	Somaye Mohammadyan, Shaahin Angizi, Keivan Navi	New fully single layer QCA full-adder cell based on feedback model.	Int. J. High Perform. Syst. Archit.	2015	DBLP DOI BibTeX RDF
20	Yavar Safaei Mehrabani, Mohammad Eshghi	A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology.	Circuits Syst. Signal Process.	2015	DBLP DOI BibTeX RDF
20	Yavar Safaei Mehrabani, Mohammad Eshghi	Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology.	Circuits Syst. Signal Process.	2015	DBLP DOI BibTeX RDF
20	Vishesh Dokania, Aminul Islam 0002	Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells.	IET Circuits Devices Syst.	2015	DBLP DOI BibTeX RDF
20	Razieh Farazkish, Fatemeh Khodaparast 0001	Design and characterization of a new fault-tolerant full-adder for quantum-dot cellular automata.	Microprocess. Microsystems	2015	DBLP DOI BibTeX RDF
20	Yavar Safaei Mehrabani, Mohammad Eshghi	High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
20	Majid Haghparast, Soghra Shoaei	Design of a New Parity Preserving Reversible Full Adder.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
20	Arman Roohi, Ronald F. DeMara, Navid Khoshavi	Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
20	Andrew Adamatzky	Binary full adder, made of fusion gates, in sub-excitable Belousov-Zhabotinsky system.	CoRR	2015	DBLP BibTeX RDF
20	Mehri Teimoory, Amirali Amirsoleimani, Jafar Shamsi, Arash Ahmadi, Shahpour Alirezaee, Majid Ahmadi	Optimized Implementation of Memristor-Based Full Adder by Material Implication Logic.	CoRR	2015	DBLP BibTeX RDF
20	Ella Gale	Single Memristor Logic Gates: From NOT to a Full Adder.	CoRR	2015	DBLP BibTeX RDF
20	Shaahin Angizi, Fahimeh Danehdaran, Soheil Sarmadi, Shadi Sheikhfaal, Nader Bagherzadeh, Keivan Navi	An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
20	Erya Deng, Yue Zhang 0010, Wang Kang 0001, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao	Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
20	Kejie Huang, Rong Zhao, Yong Lian 0001	A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
20	Erya Deng, You Wang 0002, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat, Weisheng Zhao	Robust magnetic full-adder with voltage sensing 2T/2MTJ cell.	NANOARCH	2015	DBLP DOI BibTeX RDF
20	Qi An, Li Su, Jacques-Olivier Klein, Sébastien Le Beux, Ian O'Connor, Weisheng Zhao	Full-adder circuit design based on all-spin logic device.	NANOARCH	2015	DBLP DOI BibTeX RDF
20	Biswarup Mukherjee 0003, Aniruddha Ghosal	Design & study of a low power high speed full adder using GDI multiplexer.	ReTIS	2015	DBLP DOI BibTeX RDF
20	Sneh Lata Murotiya, Anu Gupta	Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs.	VLSID	2015	DBLP DOI BibTeX RDF
20	Rishika Sethi, Gaurav Soni	Comparative Analysis of Si-MOSFET and CNFET-Based 28T Full Adder.	SocProS (1)	2015	DBLP DOI BibTeX RDF
20	Vahid Foroutan, MohammadReza Taheri, Keivan Navi, Arash Azizi Mazreah	Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style.	Integr.	2014	DBLP DOI BibTeX RDF
20	R. M. Bommi, S. Selvakumar Raja	All optical Implementation of High Speed and low Power Reversible Full Adder using semiconductor optical amplifier based Mach-Zehnder Interferometer.	J. Comput. Sci.	2014	DBLP DOI BibTeX RDF
20	Peiman Keshavarzian, Rahil Sarikhani	A Novel CNTFET-based Ternary Full Adder.	Circuits Syst. Signal Process.	2014	DBLP DOI BibTeX RDF
20	Raghvendra Singh, Shyam Akashe	Modeling and Analysis of Low Power 10 T Full Adder with Reduced Ground Bounce noise.	J. Circuits Syst. Comput.	2014	DBLP DOI BibTeX RDF
20	Ali Ghorbani, Ghazaleh Ghorbani	Energy Efficient Full Adder Cell Design With Using Carbon Nanotube Field Effect Transistors In 32 Nanometer Technology.	CoRR	2014	DBLP BibTeX RDF
20	Mehdi Masoudi, Milad Mazaheri, Aliakbar Rezaei, Keivan Navi	Designing high-speed, low-power full adder cells based on carbon nanotube technology.	CoRR	2014	DBLP BibTeX RDF
20	Bahniman Ghosh, A. Ajay	2-Bit Full Adder Implementation Using Single Spin Logic Paradigm.	J. Low Power Electron.	2014	DBLP DOI BibTeX RDF
20	Nehru Kandasamy, A. Shanmugam	Design of high-performance low-power full adder.	Int. J. Comput. Appl. Technol.	2014	DBLP DOI BibTeX RDF
20	Zahra Mohammadi, Majid Mohammadi	Implementing a one-bit reversible full adder using quantum-dot cellular automata.	Quantum Inf. Process.	2014	DBLP DOI BibTeX RDF
20	Robert Perricone, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier	Design of 3D nanomagnetic logic circuits: A full-adder case study.	DATE	2014	DBLP DOI BibTeX RDF
20	Mehri Teimoory, Amirali Amirsoleimani, Jafar Shamsi, Arash Ahmadi, Shahpour Alirezaee, Majid Ahmadi	Optimized implementation of memristor-based full adder by material implication logic.	ICECS	2014	DBLP DOI BibTeX RDF
20	A. Kishore Kumar, D. Somasundareswari, V. Duraisamy, T. Shunbaga Pradeepa	Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL.	VLSI Design	2013	DBLP DOI BibTeX RDF
20	Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh	A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages.	Int. J. High Perform. Syst. Archit.	2013	DBLP DOI BibTeX RDF
20	Karthik Reddy G	Low power-area designs of 1bit full adder in cadence virtuoso platform.	CoRR	2013	DBLP BibTeX RDF
20	Bahniman Ghosh, Chandramauli Singh, Akshay Kumar Salimath	A Novel Approach of Full Adder and Arithmetic Logic Unit Design in Quantum Dot Cellular Automata.	J. Low Power Electron.	2013	DBLP DOI BibTeX RDF
20	Azadeh Safari, James Nugent, Yinan Kong	Novel implementation of full adder based scaling in Residue Number Systems.	MWSCAS	2013	DBLP DOI BibTeX RDF
20	Narasimha Rao Konijeti, J. V. R. Ravindra, Pandurangaiah Yagateela	Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology.	EMS	2013	DBLP DOI BibTeX RDF
20	Gangadhar Reddy Ramireddy, J. V. R. Ravindra, Harikrishna Kamatham	Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style.	EMS	2013	DBLP DOI BibTeX RDF
20	Yue Zhang 0010, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller	Synchronous full-adder based on complementary resistive switching memory cells.	NEWCAS	2013	DBLP DOI BibTeX RDF
20	Xiaobao Chen, Zuocheng Xing, Bingcai Sui	A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature.	NCCET	2013	DBLP DOI BibTeX RDF
20	Ireneusz Brzozowski, Damian Palys, Andrzej Kos	An analysis of full adder cells for low-power data oriented adders design.	MIXDES	2013	DBLP BibTeX RDF
20	Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari	Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design.	VLSI Design	2012	DBLP DOI BibTeX RDF
20	Shiwani Singh, Tripti Sharma, K. G. Sharma, B. P. Singh	9T Full Adder Design in Subthreshold Region.	VLSI Design	2012	DBLP DOI BibTeX RDF
20	Sohan Purohit, Martin Margala	Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
20	Mohammad Reza Reshadinezhad, Mohammad Hossein Moaiyeri, Keivan Navi	An Energy-Efficient Full Adder Cell Using CNFET Technology.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
20	Mahdiar Hosein Ghadiry, Mahdieh Nadi Senjani, Hosein Mohammadi, Asrulnizam Bin Abd Manaf	Analysis of a Novel Full Adder Designed for Implementing in Carbone nanotube Technology.	J. Circuits Syst. Comput.	2012	DBLP DOI BibTeX RDF
20	Mehdi Ghasemi, Mohammad Hossein Moaiyeri, Keivan Navi	A New Full Adder Cell for Molecular Electronics	CoRR	2012	DBLP BibTeX RDF
20	Manoj Kumar 0005, Sandeep Kumar Arya, Sujata Pandey	Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate	CoRR	2012	DBLP BibTeX RDF
20	Gajula Ramana Murthy, Chinnaiyan Senthilpari, Pitchandi Velrajkumar, Tien Sze Lim	A new 6-T multiplexer based full-adder for low power and leakage current optimization.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
20	Kamran Delfan Hemmati, Mojtaba Behzad Fallahpour, Abbas Golmakani, Kamyar Delfan Hemmati	A high-speed hybrid Full Adder with low power consumption.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
20	Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar	Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme.	ISED	2012	DBLP DOI BibTeX RDF
20	Manoj Kumar 0005	Design of 9-transistor single bit full adder.	CCSEIT	2012	DBLP DOI BibTeX RDF
20	Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu	Low power 10-transistor full adder design based on degenerate pass transistor logic.	ISCAS	2012	DBLP DOI BibTeX RDF
20	Richa Saraswat, Shyam Akashe, Shyam Babu	Analysis and Simulation of Full Adder Design Using MTCMOS Technique.	BIC-TA (2)	2012	DBLP DOI BibTeX RDF
20	Yi Wei, Jizhong Shen	Design of a novel low power 8-transistor 1-bit full adder cell.	J. Zhejiang Univ. Sci. C	2011	DBLP DOI BibTeX RDF
20	Keivan Navi, Horialsadat Hossein Sajedi, Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Ali Jalali, Omid Kavehei	High-speed full adder based on minority function and bridge style for nanoscale.	Integr.	2011	DBLP DOI BibTeX RDF
20	Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Hamid Khorsand, Keivan Navi	A New Robust and High-Performance Hybrid Full Adder Cell.	J. Circuits Syst. Comput.	2011	DBLP DOI BibTeX RDF
20	Mahdiar Hosein Ghadiry, Abu Khari A'Ain, Mahdieh Nadi Senjani	Design and Analysis of a Novel Low PDP Full Adder Cell.	J. Circuits Syst. Comput.	2011	DBLP DOI BibTeX RDF
20	Sunil Gavaskar Reddy, Rajendra Prasad	Power comparison of CMOS and adiabatic full adder circuit	CoRR	2011	DBLP BibTeX RDF
20	Ashkan Khatir, Shaghayegh Abdolahzadegan, Iman Mahmoudi	High Speed Multiple Valued Logic Full Adder Using Carbon Nano Tube Field Effect Transistor	CoRR	2011	DBLP BibTeX RDF
20	Lixin Gao	High performance Complementary Pass transistor Logic full adder.	EMEIT	2011	DBLP DOI BibTeX RDF
20	Mallikarjuna Rao Nimmagadda, Ajit Pal	Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design.	ISVLSI	2011	DBLP DOI BibTeX RDF
20	David J. Willingham, Izzet Kale	A Ternary Adiabatic Logic (TAL) implementation of a four-trit Full-Adder.	NORCHIP	2011	DBLP DOI BibTeX RDF
20	Mohammad Javad Zavarei, Mohammad Reza Baghbanmanesh, Ehsan Kargaran, Hooman Nabovati, Abbas Golmakani	Design of new full adder cell using hybrid-CMOS logic style.	ICECS	2011	DBLP DOI BibTeX RDF
20	Iftekhar Ibne Basith, Tareq Muhammad Supon, Ajit Muhury, Rashid Rashidzadeh, Majid Ahmadi	Performance enhancement of single electron junction 1-bit full adder.	ICECS	2011	DBLP DOI BibTeX RDF
20	Sayyed Hasan Mozafari, Mahdi Fazeli, Shaahin Hessabi, Seyed Ghassem Miremadi	A Low Cost circuit level fault detection technique to Full Adder design.	ICECS	2011	DBLP DOI BibTeX RDF
20	Yngvar Berg	Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic.	ISMVL	2011	DBLP DOI BibTeX RDF
20	Keivan Navi, Fazel Sharifi, Amir Momeni, Peiman Keshavarzian	Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates.	IEICE Trans. Electron.	2010	DBLP DOI BibTeX RDF
20	Keivan Navi, Razieh Farazkish, Samira Sayedsalehi, Mostafa Rahimi Azghadi	A new quantum-dot cellular automata full-adder.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
20	Md. Saiful Islam 0003	A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology	CoRR	2010	DBLP BibTeX RDF
20	Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz	Realization of a Novel Fault Tolerant Reversible Full Adder Circuit in Nanotechnology.	Int. Arab J. Inf. Technol.	2010	DBLP BibTeX RDF
20	Sohan Purohit, Marco Lanuzza, Martin Margala	Design Space Exploration of Split-Path Data Driven Dynamic Full Adder.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
20	Kiran K. Chaddha, Rajeevan Chandel	Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
20	Ilham Hassoune, Denis Flandre, Ian O'Connor, Jean-Didier Legat	ULPFA: A New Efficient Design of a Power-Aware Full Adder.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
20	Keivan Navi, Mehrdad Maeen, Vahid Foroutan, Somayeh Timarchi, Omid Kavehei	A novel low-power full-adder cell for low voltage.	Integr.	2009	DBLP DOI BibTeX RDF
20	Jeong Beom Kim	Current Mode CMOS Quaternary Logic Full-Adder.	J. Circuits Syst. Comput.	2009	DBLP DOI BibTeX RDF
20	Keivan Navi, Vahid Foroutan, Mostafa Rahimi Azghadi, Mehrdad Maeen, Maryam Ebrahimpour, M. Kaveh, Omid Kavehei	A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter.	Microelectron. J.	2009	DBLP DOI BibTeX RDF