Search results for "multipliers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh	Systematic design of high-radix Montgomery multipliers for RSA processors.	ICCD	2008	DBLP DOI BibTeX RDF
20	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Switching activity estimation for shift-and-add based constant multipliers.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan	Fault tolerant bit parallel finite field multipliers using LDPC codes.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman 0001, Dhiraj K. Pradhan	Single Error Correcting Finite Field Multipliers Over GF(2m).	VLSI Design	2008	DBLP DOI BibTeX RDF	Galois Field Multiplier, VLSI, Cryptography, Error Correcting Codes
20	Henrik Eriksson	Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers.	PATMOS	2007	DBLP DOI BibTeX RDF
20	Jiun-Ping Wang, Shiann-Rong Kuang	Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit.	SiPS	2007	DBLP DOI BibTeX RDF
20	Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu	Low Power Multipliers Using Enhenced Row Bypassing Schemes.	SiPS	2007	DBLP DOI BibTeX RDF
20	Jamshid Shokrollahi, Elisa Gorla, Christoph Puttmann	Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97).	FPL	2007	DBLP DOI BibTeX RDF
20	Nathaniel Ross Pinckney, David Money Harris	Parallelized radix-4 scalable montgomery multipliers.	SBCCI	2007	DBLP DOI BibTeX RDF	cryptography, RSA, Montgomery Multiplication
20	Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena	Switching Activity Models for Power Estimation in FPGA Multipliers.	ARC	2007	DBLP DOI BibTeX RDF
20	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan	Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).	VLSI Design	2007	DBLP DOI BibTeX RDF
20	Samir Hamaci, Jean-Louis Boimond, Sébastien Lahaye	Modeling and Control of Hybrid Timed Event Graphs with Multipliers Using (Min, +) Algebra.	Discret. Event Dyn. Syst.	2006	DBLP DOI BibTeX RDF	Hybrid timed event graph, (min, +) algebra, Just-in-time control
20	Mustafa Gök, Michael J. Schulte, Mark G. Arnold	Integer Multipliers with Overflow Detection.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	high-speed arithmetic algorithms, overflow detection, Computer arithmetic, multiplication, combinational logic
20	Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu	Carry Estimation for Two's Complement Fixed-Width Multipliers.	SiPS	2006	DBLP DOI BibTeX RDF
20	Gordana Jovanovic-Dolecek, M. A. Perez-Xochicale	One Method for Design of Wide-band FIR Filters Without Multipliers.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
20	George Economakos, Kostas Anagnostopoulos	Bit level architectural exploration technique for the design of low power multipliers.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Zih-Heng Chen, Ming-Haw Jing, Jian-Hong Chen, Yaotsu Chang	New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Paul Bougas, Andreas Tsirikos, Kostas Anagnostopoulos, Isidoros Sideris, Kiamal Z. Pekmestzi	Segmentation based design of serial parallel multipliers.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Yoo-Jin Baek, Mi-Jung Noh	DPA-Resistant Finite Field Multipliers and Secure AES Design.	ISPEC	2006	DBLP DOI BibTeX RDF
20	Hayssam El-Razouk, Zine Abid	Area and Power Efficient Array and Tree Multipliers.	CCECE	2006	DBLP DOI BibTeX RDF
20	Masahiro Iwahashi, Dang Khoa Dang, Masahiro Ohnishi, Somchart Chokchaitam	A new structure of integer DCT least sensitive to finite word length expression of multipliers.	ICIP (2)	2005	DBLP DOI BibTeX RDF
20	E. George Walters III, Michael J. Schulte	Efficient Function Approximation Using Truncated Multipliers and Squarers.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
20	Ravi Kumar Satzoda, Chip-Hong Chang	VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
20	Jianbing Li 0003, Zhongxia Niu, Dongfiang Zhou, Yujie Shi	Analysis of series-parallel resonant converter with multipliers.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
20	Min-An Song, Lan-Da Van, Chih-Chyau Yang, Shih-Chieh Chiu, Sy-Yen Kuo	A framework for the design of error-aware power-efficient fixed-width Booth multipliers.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
20	Arash Reyhani-Masoleh, M. Anwar Hasan	Efficient digit-serial normal basis multipliers over binary extension fields.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	security, finite field, normal basis, Digit-serial multiplier
20	Yoshinobu Tonomura, Somchart Chokchaitam, Masahiro Iwahashi	Minrmum hardware implementation of multipliers of the lifting wavelet transform.	ICIP	2004	DBLP DOI BibTeX RDF
20	Zhaoshui He, Shengli Xie, Yuli Fu 0001	An approach to blind separation based on penalty function with multipliers.	ICARCV	2004	DBLP DOI BibTeX RDF
20	Mitchell J. Myjak, José G. Delgado-Frias	Pipelined Multipliers for Reconfigurable Hardware.	IPDPS	2004	DBLP DOI BibTeX RDF
20	Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH.	ISMVL	2004	DBLP DOI BibTeX RDF
20	Andrew G. Dempster, Malcolm D. Macleod	Using all signed-digit representations to design single integer multipliers using subexpression elimination.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
20	Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase	Parallel Montgomery Multipliers.	ASAP	2004	DBLP DOI BibTeX RDF
20	Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu	Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division
20	Satish K. Bandapati, Scott C. Smith, Minsu Choi	Design and Characterization of Null Convention Self-Timed Multipliers.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
20	Masahiro Iwahashi, Osamu Nishida, Somchart Chokchaitam, Noriyoshi Kambayashi	Optimum word length allocation for multipliers of integer DCT.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
20	Shugang Wei, Kensuke Shimizu	Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
20	Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty	Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.	DAC	2003	DBLP DOI BibTeX RDF	bandwidth matching, automatic test equipment (ATE), test access mechanism (TAM), scan chains, system-on-chip (SOC)
20	Carl James Debono, Franco Maloberti, Joseph Micallef	On the design of low-voltage, low-power CMOS analog multipliers for RF applications.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
20	Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	A New Architecture for Signed Radix-2m Pure Array Multipliers.	ICCD	2002	DBLP DOI BibTeX RDF
20	Maziar Tavakoli Dastjerdi, Rahul Sarpeshkar	A low-noise nonlinear feedback technique for compensating offset in analog multipliers.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
20	Arash Reyhani-Masoleh, M. Anwar Hasan	Efficient digit-serial normal basis multipliers over GF(2m).	ISCAS (5)	2002	DBLP DOI BibTeX RDF
20	A. Laratta, F. Zironi	Computation of Lagrange Multipliers for Linear Least Squares Problems with Equality Constraints.	Computing	2001	DBLP DOI BibTeX RDF	AMS Subject Classifications: 65K05, 90C31
20	C. Diaz-Goano, Peter Dimitrov Minev, Krishnaswamy Nandakumar	A Lagrange Multipliers/Fictitious Domain Approach for Particulate Flow.	LSSC	2001	DBLP DOI BibTeX RDF
20	Tetsushi Ueta, Shigeki Tsuji, Tetsuya Yoshinaga, Hiroshi Kawakami	Calculation of the isocline for the fixed point with a specified argument of complex multipliers.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
20	Vincent F. Koosh, Rodney M. Goodman	VLSI neural network with digital weights and analog multipliers.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
20	Vassilis Paliouras, Thanos Stouraitis	Novel high-radix residue number system multipliers and adders.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
20	Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers.	VTS	1999	DBLP DOI BibTeX RDF
20	Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu	Design of C-Testable Multipliers Based on the Modified Booth Algorithm.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model
20	Uwe Sparmann, Sudhakar M. Reddy	On the effectiveness of residue code checking for parallel two's complement multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
20	Angela Kunoth	Multilevel preconditioning - Appending boundary conditions by Lagrange multipliers.	Adv. Comput. Math.	1995	DBLP DOI BibTeX RDF	AMS subject classification 15A12, 41A17, 65N30, 41A63, 65F35, 49M29, 46E35
20	Jang Dae Kim, Shiu-Kai Chin	Formal Verification of Serial Pipeline Multipliers.	TPHOLs	1995	DBLP DOI BibTeX RDF
20	Paolo Montuschi, Luigi Ciminiera	n × n carry-save multipliers without final addition.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
16	Atef Ibrahim, Fayez Gebali, Hamed Elsimary, Amin M. Nassar	Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm.	IEEE Trans. Parallel Distributed Syst.	2011	DBLP DOI BibTeX RDF	low power modular multipliers, scalability, cryptography, Montgomery multiplication, secure communications, Processor array
16	Alexander Shapiro 0001	Semidefinite Programming: Optimality Conditions and Stability.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Tangent cone, Complementarity condition, Stability, Sensitivity analysis, Semidefinite programming, Duality, Lagrange multipliers, Nondegeneracy
16	John N. Hooker	Integer Programming: Lagrangian Relaxation.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Lagrangian dual, Integer programming, Branch and bound, Lagrangian relaxation, Lagrange multipliers
16	Franco Giannessi	Theorems of the Alternative and Optimization.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Theorem of the alternative, Transposition theorem, Lagrange function, Dual problem, Lagrange multipliers, Image space, Separation theorems, Dual space
16	Franco Giannessi	Image Space Approach to Optimization.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Separation functions, Lagrange function, Separation, Sufficient condition, Lagrange multipliers, Euler equation, Necessary conditions, Image space
16	Tania Maia Querido, Dukwon Kim	Lagrange, Joseph-Louis.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Lagrange multipliers, Calculus of variations
16	Vaithilingam Jeyakumar, S. Srisatkunarajah	Lagrange multiplier necessary conditions for global optimality for non-convex minimization over a quadratic constraint via S-lemma.	Optim. Lett.	2009	DBLP DOI BibTeX RDF	Smooth non-convex minimization, Difference of quadratic and convex functions, Single quadratic constraint, Global optimality, Lagrange multipliers, Fractional programs
16	Han Chen, Pasquale Malacaria	Quantifying maximal loss of anonymity in protocols.	AsiaCCS	2009	DBLP DOI BibTeX RDF	anonymity, quantitative analysis, Lagrange multipliers
16	Levent Aksoy, Diego Jaccottet, Eduardo Costa 0001	Design of low complexity digital FIR filters.	SBCCI	2009	DBLP DOI BibTeX RDF	low-level synthesis, multiple constant multiplications, multiplierless filter design, high-level synthesis, array multipliers
16	Igor Griva, Roman A. Polyak	1.5-Q-superlinear convergence of an exterior-point method for constrained optimization.	J. Glob. Optim.	2008	DBLP DOI BibTeX RDF	Nonlinear rescaling, Multipliers method, duality, Primal-dual, Augmented Lagrangian
16	Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz	Optimized Architectural Synthesis of Fixed-Point Datapaths.	ReConFig	2008	DBLP DOI BibTeX RDF	Embedded Multipliers, Fixed-Point, Architectural Synthesis
16	Roman A. Polyak, Shen-Shyang Ho, Igor Griva	Support vector machine via nonlinear rescaling method.	Optim. Lett.	2007	DBLP DOI BibTeX RDF	Support vector machine, Duality, Convex optimization, Lagrange multipliers
16	Paavo Kukkurainen	Fuzzy Subgroups with Meet Operation in the Connection of Möbius Transformations.	IFSA (1)	2007	DBLP DOI BibTeX RDF	Fixed points and multipliers of Möbius transformations, conjugation, fuzzy subgroups, meet operation, stabilizers
16	Maria Jesus Lopez-Herrero	A maximum entropy approach for the busy period of the M/G/1 retrial queue.	Ann. Oper. Res.	2006	DBLP DOI BibTeX RDF	Busy period, Lagrange multipliers, Retrial queue, Laplace transforms, Maximum entropy principle
16	Igor Griva, Roman A. Polyak	Primal-dual nonlinear rescaling method with dynamic scaling parameter update.	Math. Program.	2006	DBLP DOI BibTeX RDF	Nonlinear rescaling, Lagrangian, multipliers method, duality, primal-dual
16	Lucas Andrew Milner, Gabriel A. Rincón-Mora	A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications.	ISLPED	2005	DBLP DOI BibTeX RDF	active ripple filters, inductor multipliers, integrated inductors, power management
16	Colleen O'Rourke, Berk Sunar	Achieving NTRU with Montgomery Multiplication.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Montgomery multipliers, Cryptography, finite fields, Montgomery multiplication, NTRU, unified architectures
16	John J. Benedetto, Matthew Fickus	Finite Normalized Tight Frames.	Adv. Comput. Math.	2003	DBLP DOI BibTeX RDF	tight frames, potential energy, equidistribution, equilibrium, Lagrange multipliers
16	Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi	Noise tolerant low voltage XOR-XNOR for fast arithmetic.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	XOR-XNOR circuits, multipliers, noise tolerant, deep submicron, nanometer technology
16	Dieter Gollmann	Equally Spaced Polynomials, Dual Bases, and Multiplication in F2n.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Equally spaced polynomials, dual bases, multipliers for {rm F}_{2^n}, trace
16	Lorenzo Héctor Juárez, Roland Glowinski, Tsorng-Whay Pan	Numerical Simulation of the Sedimentation of Rigid Bodies in an Incompressible Viscous Fluid by Lagrange Multiplier/Fictitious Domain Methods Combined with the Taylor-Hood Finite Element Approximation.	J. Sci. Comput.	2002	DBLP DOI BibTeX RDF	fictitious domain, distributed Lagrange multipliers, moving rigid bodies, operator splitting, finite element, Navier-Stokes equations
16	William L. Freking, Keshab K. Parhi	Performance-Scalable Array Architectures for Modular Multiplication.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	modular multipliers, systolic computation, high-radix arithmetic implementation, pipelined architectures
16	Elmor L. Peterson	The Fundamental Relations between Geometric Programming Duality, Parametric Programming Duality, and Ordinary Lagrangian Duality.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	ordinary programming, post-optimality analysis, conjugate transformation, Legendre transformation, dual cones, orthogonal complementary subspaces, recession directions, separable optimization, sub-optimization, optimization, convex optimization, Lagrange multipliers, geometric programming, orthogonal projection, duality theory, parametric programming
16	Sorin Cotofana, Stamatis Vassiliadis	Signed Digit Addition and Related Operations with Threshold Logic.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	signed-digit arithmetic, redundant adders, redundant multipliers, neural networks, Computer arithmetic, threshold logic, carry-free addition, signed-digit number representation
16	Reto Zimmermann	Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF	Modulo (2^n=B11) adders and multipliers, end-around-carry parallel-prefix adders, IDEA cipher, cryptography, computer arithmetic, RNS, VLSI circuits
16	Mary E. Helander, Ming Zhao, Niclas Ohlsson	Planning Models for Software Reliability and Cost.	IEEE Trans. Software Eng.	1998	DBLP DOI BibTeX RDF	Budget constraints, cleanroom software development, Budget-Constrained Reliability-Maximization (BCRM) Model, cost planning, failure intensity, reliability allocation, Reliability-Constrained Cost-Minimization (RCCM) Model, software reliability. (*Terms introduced in this paper.), linear programming, software components, certification, nonlinear programming, COCOMO, operational profile, Lagrangian multipliers
16	Martine D. F. Schlag, F. Joel Ferguson	Detection of Multiple Faults in Two-Dimensional ILAs.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	testing, functional testing, multipliers, multiple faults, Iterative logic arrays
16	Irith Pomeranz, Sudhakar M. Reddy	On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Lower bound on test set size, pipelining, multipliers, path delay faults, resynthesis
16	Elio D. Di Claudio, Francesco Piazza, Gianni Orlandi	Fast Combinatorial RNS Processors for DSP Applications.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Binary multipliers, mixed radix arithmetic, pseudo-residue, VLSI processors, parallel architectures, digital signal processing, systolic arrays, residue number system
16	George A. Hadgis, P. R. Mukund	A novel CMOS monolithic analog multiplier with wide input dynamic range.	VLSI Design	1995	DBLP DOI BibTeX RDF	analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits
16	Dan Zuras	More On Squaring and Multiplying Large Integers.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	large integers, FFT multipliers, digital arithmetic, multiplying, multiplying circuits, squaring, data handling
16	Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man	Design of a C-testable booth multiplier using a realistic fault model.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	test generation, design for testability, fault modelling, Array multipliers, C-testability
16	Anthony J. McAuley	Four State Asynchronous Architectures.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	four state asynchronous architectures, asynchronous wavefront array, one-dimensional multipliers, two-dimensional sorter, reliability, throughput, sequential circuits, many-valued logics, design complexity, asynchronous sequential logic
16	Homayoon Sam, Arupratan Gupta	A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fixed coefficient multiplication, controlled coefficient multiplication, multibit recoding algorithm, signed two's complement binary numbers, radix 2/sup k/, very high speed adders, hardware parallel multipliers, 5-bit recoding, performance, computer arithmetic, digital arithmetic, multiplying circuits, signed-digit representation
16	Sally G. Smith	Incremental Computation of Squares and Sums of Squares.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	bit-sequential operation, symmetry properties, incremental multipliers, hardware modules, digit-on-line algorithm, magnitude extraction operations, plane vectors, digital arithmetic, scalar multiplication, hardware architectures, incremental algorithm, sums of squares
16	Janak H. Patel, Leona Y. Fung	Concurrent Error Detection in Multiply and Divide Arrays.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	RESO, multipliers, concurrent error detection, dividers, Cellular logic
16	Sebastián Dormido 0001, M. A. Canto	An Upper Bound for the Synthesis of Generalized Parallel Counters.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	parallel counter networks, Digital counters, multiple input adders, parallel counters, fast multipliers
16	Hung Chi Lai, Saburo Muroga	Logic Networks of Carry-Save Adders.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
16	Daniel Gajski	Parallel Compressors.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	carry-shower counters, elementary logic functions, multiple-operand addition, content- addressable memory, high-speed arithmetic, parallel counters, Associative processors, fast multipliers
16	Hideaki Kobayashi, Hiroyoshi Ohara	A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	Array logics, carry-shower counters, digital counters, multiple-input adders, parallel-counter networks, parallel counters, associative processors, fast multipliers
16	William J. Stenzel, William J. Kubitz, Gilles H. Garcia	A Compact High-Speed Parallel Multiplication Scheme.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	generalized counters, partial-product reduction, fast multipliers, Binary multiplication
16	Paul W. Baker	Parallel Multiplicative Algorithms for Some Elementary Functions.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Continued products and sums, parallel m-bit multipliers, digital arithmetic, iterative algorithms, elementary functions
15	Husain Parvez, Zied Marrakchi, Habib Mehrez	Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	asif, fpga, architecture, application specific, cad
15	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Field Programmable Compressor Tree (FPCT), compressor tree, Field Programmable Gate Array (FPGA)
15	Ira Neitzel, Uwe Prüfert, Thomas Slawig	Strategies for time-dependent PDE control with inequality constraints using an integrated modeling and simulation environment.	Numer. Algorithms	2009	DBLP DOI BibTeX RDF	Parabolic PDEs, Integrated modeling and simulation environments, Optimal control, Inequality constraints
15	Alexandre Belloni, Claudia A. Sagastizábal	Dynamic bundle methods.	Math. Program.	2009	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 90C25, 90C27, 65K05
15	Majid Ahmadi, Ashkan Hosseinzadeh Namin, Karl Leboeuf, Huapeng Wu	Artificial neural networks activation function HDL coder.	EIT	2009	DBLP DOI BibTeX RDF
15	Márcia Barros de Sales, Ricardo Azambuja Silveira, André Barros de Sales, Rita de Cássia Guarezi	Learning by Peers: An Alternative Learning Model for Digital Inclusion of Elderly People.	WCCE	2009	DBLP DOI BibTeX RDF	Learning by peers, third age digital inclusion