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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1366 occurrences of 709 keywords
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Results
Found 2778 publication records. Showing 2778 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
Systematic design of high-radix Montgomery multipliers for RSA processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 416-421, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Kenny Johansson, Oscar Gustafsson, Lars Wanhammar |
Switching activity estimation for shift-and-add based constant multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 676-679, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan |
Fault tolerant bit parallel finite field multipliers using LDPC codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1684-1687, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman 0001, Dhiraj K. Pradhan |
Single Error Correcting Finite Field Multipliers Over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 33-38, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Galois Field Multiplier, VLSI, Cryptography, Error Correcting Codes |
20 | Henrik Eriksson |
Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 566-575, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Jiun-Ping Wang, Shiann-Rong Kuang |
Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 157-162, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu |
Low Power Multipliers Using Enhenced Row Bypassing Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 136-141, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Jamshid Shokrollahi, Elisa Gorla, Christoph Puttmann |
Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 339-344, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Nathaniel Ross Pinckney, David Money Harris |
Parallelized radix-4 scalable montgomery multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 306-311, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cryptography, RSA, Montgomery Multiplication |
20 | Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena |
Switching Activity Models for Power Estimation in FPGA Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007., pp. 201-213, 2007, Springer, 978-3-540-71430-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan |
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 479-484, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Samir Hamaci, Jean-Louis Boimond, Sébastien Lahaye |
Modeling and Control of Hybrid Timed Event Graphs with Multipliers Using (Min, +) Algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Event Dyn. Syst. ![In: Discret. Event Dyn. Syst. 16(2), pp. 241-256, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Hybrid timed event graph, (min, +) algebra, Just-in-time control |
20 | Mustafa Gök, Michael J. Schulte, Mark G. Arnold |
Integer Multipliers with Overflow Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(8), pp. 1062-1066, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high-speed arithmetic algorithms, overflow detection, Computer arithmetic, multiplication, combinational logic |
20 | Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu |
Carry Estimation for Two's Complement Fixed-Width Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 345-350, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Gordana Jovanovic-Dolecek, M. A. Perez-Xochicale |
One Method for Design of Wide-band FIR Filters Without Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONIELECOMP ![In: 16th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2006), 27 February 2005 - 1 March 2006, Cholula, Puebla, Mexico, pp. 17, 2006, IEEE Computer Society, 0-7695-2505-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | George Economakos, Kostas Anagnostopoulos |
Bit level architectural exploration technique for the design of low power multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Zih-Heng Chen, Ming-Haw Jing, Jian-Hong Chen, Yaotsu Chang |
New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Paul Bougas, Andreas Tsirikos, Kostas Anagnostopoulos, Isidoros Sideris, Kiamal Z. Pekmestzi |
Segmentation based design of serial parallel multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Yoo-Jin Baek, Mi-Jung Noh |
DPA-Resistant Finite Field Multipliers and Secure AES Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPEC ![In: Information Security Practice and Experience, Second International Conference, ISPEC 2006, Hangzhou, China, April 11-14, 2006, Proceedings, pp. 1-12, 2006, Springer, 3-540-33052-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Hayssam El-Razouk, Zine Abid |
Area and Power Efficient Array and Tree Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 713-716, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Masahiro Iwahashi, Dang Khoa Dang, Masahiro Ohnishi, Somchart Chokchaitam |
A new structure of integer DCT least sensitive to finite word length expression of multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (2) ![In: Proceedings of the 2005 International Conference on Image Processing, ICIP 2005, Genoa, Italy, September 11-14, 2005, pp. 269-272, 2005, IEEE, 0-7803-9134-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | E. George Walters III, Michael J. Schulte |
Efficient Function Approximation Using Truncated Multipliers and Squarers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 232-239, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Ravi Kumar Satzoda, Chip-Hong Chang |
VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 693-706, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Jianbing Li 0003, Zhongxia Niu, Dongfiang Zhou, Yujie Shi |
Analysis of series-parallel resonant converter with multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4449-4452, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Min-An Song, Lan-Da Van, Chih-Chyau Yang, Shih-Chieh Chiu, Sy-Yen Kuo |
A framework for the design of error-aware power-efficient fixed-width Booth multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 81-84, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Arash Reyhani-Masoleh, M. Anwar Hasan |
Efficient digit-serial normal basis multipliers over binary extension fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(3), pp. 575-592, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
security, finite field, normal basis, Digit-serial multiplier |
20 | Yoshinobu Tonomura, Somchart Chokchaitam, Masahiro Iwahashi |
Minrmum hardware implementation of multipliers of the lifting wavelet transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP ![In: Proceedings of the 2004 International Conference on Image Processing, ICIP 2004, Singapore, October 24-27, 2004, pp. 2499-2502, 2004, IEEE, 0-7803-8554-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Zhaoshui He, Shengli Xie, Yuli Fu 0001 |
An approach to blind separation based on penalty function with multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: 8th International Conference on Control, Automation, Robotics and Vision, ICARCV 2004, Kunming, China, 6-9 December 2004, Proceedings, pp. 2326-2330, 2004, IEEE, 0-7803-8653-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Mitchell J. Myjak, José G. Delgado-Frias |
Pipelined Multipliers for Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001 |
Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 334-339, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Andrew G. Dempster, Malcolm D. Macleod |
Using all signed-digit representations to design single integer multipliers using subexpression elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 165-168, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase |
Parallel Montgomery Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 63-72, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu |
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 245-269, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division |
20 | Satish K. Bandapati, Scott C. Smith, Minsu Choi |
Design and Characterization of Null Convention Self-Timed Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(6), pp. 26-36, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Masahiro Iwahashi, Osamu Nishida, Somchart Chokchaitam, Noriyoshi Kambayashi |
Optimum word length allocation for multipliers of integer DCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 400-403, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Shugang Wei, Kensuke Shimizu |
Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 221-224, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty |
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 738-743, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
bandwidth matching, automatic test equipment (ATE), test access mechanism (TAM), scan chains, system-on-chip (SOC) |
20 | Carl James Debono, Franco Maloberti, Joseph Micallef |
On the design of low-voltage, low-power CMOS analog multipliers for RF applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(2), pp. 168-174, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001 |
A New Architecture for Signed Radix-2m Pure Array Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 112-117, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Maziar Tavakoli Dastjerdi, Rahul Sarpeshkar |
A low-noise nonlinear feedback technique for compensating offset in analog multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 725-728, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Arash Reyhani-Masoleh, M. Anwar Hasan |
Efficient digit-serial normal basis multipliers over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 781-784, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | A. Laratta, F. Zironi |
Computation of Lagrange Multipliers for Linear Least Squares Problems with Equality Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computing ![In: Computing 67(4), pp. 335-350, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
AMS Subject Classifications: 65K05, 90C31 |
20 | C. Diaz-Goano, Peter Dimitrov Minev, Krishnaswamy Nandakumar |
A Lagrange Multipliers/Fictitious Domain Approach for Particulate Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LSSC ![In: Large-Scale Scientific Computing, Third International Conference, LSSC 2001, Sozopol, Bulgaria, June 6-10, 2001, Revised Papers, pp. 409-416, 2001, Springer, 3-540-43043-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Tetsushi Ueta, Shigeki Tsuji, Tetsuya Yoshinaga, Hiroshi Kawakami |
Calculation of the isocline for the fixed point with a specified argument of complex multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 755-758, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Vincent F. Koosh, Rodney M. Goodman |
VLSI neural network with digital weights and analog multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 233-236, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Vassilis Paliouras, Thanos Stouraitis |
Novel high-radix residue number system multipliers and adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 451-454, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian |
An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 252-259, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu |
Design of C-Testable Multipliers Based on the Modified Booth Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 42-47, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model |
20 | Uwe Sparmann, Sudhakar M. Reddy |
On the effectiveness of residue code checking for parallel two's complement multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(2), pp. 227-239, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
20 | Angela Kunoth |
Multilevel preconditioning - Appending boundary conditions by Lagrange multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Comput. Math. ![In: Adv. Comput. Math. 4(1), pp. 145-170, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
AMS subject classification 15A12, 41A17, 65N30, 41A63, 65F35, 49M29, 46E35 |
20 | Jang Dae Kim, Shiu-Kai Chin |
Formal Verification of Serial Pipeline Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Higher Order Logic Theorem Proving and Its Applications, 8th International Workshop, Aspen Grove, UT, USA, September 11-14, 1995, Proceedings, pp. 229-244, 1995, Springer, 3-540-60275-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
20 | Paolo Montuschi, Luigi Ciminiera |
n × n carry-save multipliers without final addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 54-61, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Atef Ibrahim, Fayez Gebali, Hamed Elsimary, Amin M. Nassar |
Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 22(7), pp. 1142-1149, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
low power modular multipliers, scalability, cryptography, Montgomery multiplication, secure communications, Processor array |
16 | Alexander Shapiro 0001 |
Semidefinite Programming: Optimality Conditions and Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Optimization ![In: Encyclopedia of Optimization, Second Edition, pp. 3380-3384, 2009, Springer, 978-0-387-74758-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Tangent cone, Complementarity condition, Stability, Sensitivity analysis, Semidefinite programming, Duality, Lagrange multipliers, Nondegeneracy |
16 | John N. Hooker |
Integer Programming: Lagrangian Relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Optimization ![In: Encyclopedia of Optimization, Second Edition, pp. 1667-1673, 2009, Springer, 978-0-387-74758-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Lagrangian dual, Integer programming, Branch and bound, Lagrangian relaxation, Lagrange multipliers |
16 | Franco Giannessi |
Theorems of the Alternative and Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Optimization ![In: Encyclopedia of Optimization, Second Edition, pp. 3895-3902, 2009, Springer, 978-0-387-74758-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Theorem of the alternative, Transposition theorem, Lagrange function, Dual problem, Lagrange multipliers, Image space, Separation theorems, Dual space |
16 | Franco Giannessi |
Image Space Approach to Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Optimization ![In: Encyclopedia of Optimization, Second Edition, pp. 1561-1567, 2009, Springer, 978-0-387-74758-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Separation functions, Lagrange function, Separation, Sufficient condition, Lagrange multipliers, Euler equation, Necessary conditions, Image space |
16 | Tania Maia Querido, Dukwon Kim |
Lagrange, Joseph-Louis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Optimization ![In: Encyclopedia of Optimization, Second Edition, pp. 1799-1800, 2009, Springer, 978-0-387-74758-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Lagrange multipliers, Calculus of variations |
16 | Vaithilingam Jeyakumar, S. Srisatkunarajah |
Lagrange multiplier necessary conditions for global optimality for non-convex minimization over a quadratic constraint via S-lemma. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Optim. Lett. ![In: Optim. Lett. 3(1), pp. 23-33, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Smooth non-convex minimization, Difference of quadratic and convex functions, Single quadratic constraint, Global optimality, Lagrange multipliers, Fractional programs |
16 | Han Chen, Pasquale Malacaria |
Quantifying maximal loss of anonymity in protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsiaCCS ![In: Proceedings of the 2009 ACM Symposium on Information, Computer and Communications Security, ASIACCS 2009, Sydney, Australia, March 10-12, 2009, pp. 206-217, 2009, ACM, 978-1-60558-394-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
anonymity, quantitative analysis, Lagrange multipliers |
16 | Levent Aksoy, Diego Jaccottet, Eduardo Costa 0001 |
Design of low complexity digital FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low-level synthesis, multiple constant multiplications, multiplierless filter design, high-level synthesis, array multipliers |
16 | Igor Griva, Roman A. Polyak |
1.5-Q-superlinear convergence of an exterior-point method for constrained optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Glob. Optim. ![In: J. Glob. Optim. 40(4), pp. 679-695, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Nonlinear rescaling, Multipliers method, duality, Primal-dual, Augmented Lagrangian |
16 | Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz |
Optimized Architectural Synthesis of Fixed-Point Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 85-90, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Embedded Multipliers, Fixed-Point, Architectural Synthesis |
16 | Roman A. Polyak, Shen-Shyang Ho, Igor Griva |
Support vector machine via nonlinear rescaling method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Optim. Lett. ![In: Optim. Lett. 1(4), pp. 367-378, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Support vector machine, Duality, Convex optimization, Lagrange multipliers |
16 | Paavo Kukkurainen |
Fuzzy Subgroups with Meet Operation in the Connection of Möbius Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFSA (1) ![In: Foundations of Fuzzy Logic and Soft Computing, 12th International Fuzzy Systems Association World Congress, IFSA 2007, Cancun, Mexico, June 18-21, 2007, Proceedings, pp. 445-450, 2007, Springer, 978-3-540-72917-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Fixed points and multipliers of Möbius transformations, conjugation, fuzzy subgroups, meet operation, stabilizers |
16 | Maria Jesus Lopez-Herrero |
A maximum entropy approach for the busy period of the M/G/1 retrial queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 141(1), pp. 271-281, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Busy period, Lagrange multipliers, Retrial queue, Laplace transforms, Maximum entropy principle |
16 | Igor Griva, Roman A. Polyak |
Primal-dual nonlinear rescaling method with dynamic scaling parameter update. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 106(2), pp. 237-259, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Nonlinear rescaling, Lagrangian, multipliers method, duality, primal-dual |
16 | Lucas Andrew Milner, Gabriel A. Rincón-Mora |
A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 84-89, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
active ripple filters, inductor multipliers, integrated inductors, power management |
16 | Colleen O'Rourke, Berk Sunar |
Achieving NTRU with Montgomery Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(4), pp. 440-448, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Montgomery multipliers, Cryptography, finite fields, Montgomery multiplication, NTRU, unified architectures |
16 | John J. Benedetto, Matthew Fickus |
Finite Normalized Tight Frames. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Comput. Math. ![In: Adv. Comput. Math. 18(2-4), pp. 357-385, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
tight frames, potential energy, equidistribution, equilibrium, Lagrange multipliers |
16 | Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi |
Noise tolerant low voltage XOR-XNOR for fast arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 285-288, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
XOR-XNOR circuits, multipliers, noise tolerant, deep submicron, nanometer technology |
16 | Dieter Gollmann |
Equally Spaced Polynomials, Dual Bases, and Multiplication in F2n. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(5), pp. 588-591, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Equally spaced polynomials, dual bases, multipliers for {rm F}_{2^n}, trace |
16 | Lorenzo Héctor Juárez, Roland Glowinski, Tsorng-Whay Pan |
Numerical Simulation of the Sedimentation of Rigid Bodies in an Incompressible Viscous Fluid by Lagrange Multiplier/Fictitious Domain Methods Combined with the Taylor-Hood Finite Element Approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Sci. Comput. ![In: J. Sci. Comput. 17(1-4), pp. 683-694, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fictitious domain, distributed Lagrange multipliers, moving rigid bodies, operator splitting, finite element, Navier-Stokes equations |
16 | William L. Freking, Keshab K. Parhi |
Performance-Scalable Array Architectures for Modular Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(2), pp. 101-116, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
modular multipliers, systolic computation, high-radix arithmetic implementation, pipelined architectures |
16 | Elmor L. Peterson |
The Fundamental Relations between Geometric Programming Duality, Parametric Programming Duality, and Ordinary Lagrangian Duality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 105(1-4), pp. 109-153, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
ordinary programming, post-optimality analysis, conjugate transformation, Legendre transformation, dual cones, orthogonal complementary subspaces, recession directions, separable optimization, sub-optimization, optimization, convex optimization, Lagrange multipliers, geometric programming, orthogonal projection, duality theory, parametric programming |
16 | Sorin Cotofana, Stamatis Vassiliadis |
Signed Digit Addition and Related Operations with Threshold Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(3), pp. 193-207, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
signed-digit arithmetic, redundant adders, redundant multipliers, neural networks, Computer arithmetic, threshold logic, carry-free addition, signed-digit number representation |
16 | Reto Zimmermann |
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 158-167, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Modulo (2^n=B11) adders and multipliers, end-around-carry parallel-prefix adders, IDEA cipher, cryptography, computer arithmetic, RNS, VLSI circuits |
16 | Mary E. Helander, Ming Zhao, Niclas Ohlsson |
Planning Models for Software Reliability and Cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 24(6), pp. 420-434, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Budget constraints, cleanroom software development, Budget-Constrained Reliability-Maximization (BCRM) Model*, cost planning, failure intensity, reliability allocation, Reliability-Constrained Cost-Minimization (RCCM) Model*, software reliability. (*Terms introduced in this paper.), linear programming, software components, certification, nonlinear programming, COCOMO, operational profile, Lagrangian multipliers |
16 | Martine D. F. Schlag, F. Joel Ferguson |
Detection of Multiple Faults in Two-Dimensional ILAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(6), pp. 741-746, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
testing, functional testing, multipliers, multiple faults, Iterative logic arrays |
16 | Irith Pomeranz, Sudhakar M. Reddy |
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(1), pp. 50-62, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Lower bound on test set size, pipelining, multipliers, path delay faults, resynthesis |
16 | Elio D. Di Claudio, Francesco Piazza, Gianni Orlandi |
Fast Combinatorial RNS Processors for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(5), pp. 624-633, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Binary multipliers, mixed radix arithmetic, pseudo-residue, VLSI processors, parallel architectures, digital signal processing, systolic arrays, residue number system |
16 | George A. Hadgis, P. R. Mukund |
A novel CMOS monolithic analog multiplier with wide input dynamic range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 310-314, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits |
16 | Dan Zuras |
More On Squaring and Multiplying Large Integers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(8), pp. 899-908, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
large integers, FFT multipliers, digital arithmetic, multiplying, multiplying circuits, squaring, data handling |
16 | Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man |
Design of a C-testable booth multiplier using a realistic fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(1), pp. 29-41, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
test generation, design for testability, fault modelling, Array multipliers, C-testability |
16 | Anthony J. McAuley |
Four State Asynchronous Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(2), pp. 129-142, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
four state asynchronous architectures, asynchronous wavefront array, one-dimensional multipliers, two-dimensional sorter, reliability, throughput, sequential circuits, many-valued logics, design complexity, asynchronous sequential logic |
16 | Homayoon Sam, Arupratan Gupta |
A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(8), pp. 1006-1015, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
fixed coefficient multiplication, controlled coefficient multiplication, multibit recoding algorithm, signed two's complement binary numbers, radix 2/sup k/, very high speed adders, hardware parallel multipliers, 5-bit recoding, performance, computer arithmetic, digital arithmetic, multiplying circuits, signed-digit representation |
16 | Sally G. Smith |
Incremental Computation of Squares and Sums of Squares. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(9), pp. 1325-1328, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
bit-sequential operation, symmetry properties, incremental multipliers, hardware modules, digit-on-line algorithm, magnitude extraction operations, plane vectors, digital arithmetic, scalar multiplication, hardware architectures, incremental algorithm, sums of squares |
16 | Janak H. Patel, Leona Y. Fung |
Concurrent Error Detection in Multiply and Divide Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(4), pp. 417-422, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
RESO, multipliers, concurrent error detection, dividers, Cellular logic |
16 | Sebastián Dormido 0001, M. A. Canto |
An Upper Bound for the Synthesis of Generalized Parallel Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(8), pp. 802-805, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
parallel counter networks, Digital counters, multiple input adders, parallel counters, fast multipliers |
16 | Hung Chi Lai, Saburo Muroga |
Logic Networks of Carry-Save Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(9), pp. 870-882, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders |
16 | Daniel Gajski |
Parallel Compressors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(5), pp. 393-398, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
carry-shower counters, elementary logic functions, multiple-operand addition, content- addressable memory, high-speed arithmetic, parallel counters, Associative processors, fast multipliers |
16 | Hideaki Kobayashi, Hiroyoshi Ohara |
A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(8), pp. 753-757, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
Array logics, carry-shower counters, digital counters, multiple-input adders, parallel-counter networks, parallel counters, associative processors, fast multipliers |
16 | William J. Stenzel, William J. Kubitz, Gilles H. Garcia |
A Compact High-Speed Parallel Multiplication Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(10), pp. 948-957, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
generalized counters, partial-product reduction, fast multipliers, Binary multiplication |
16 | Paul W. Baker |
Parallel Multiplicative Algorithms for Some Elementary Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(3), pp. 322-325, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
Continued products and sums, parallel m-bit multipliers, digital arithmetic, iterative algorithms, elementary functions |
15 | Husain Parvez, Zied Marrakchi, Habib Mehrez |
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 290, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asif, fpga, architecture, application specific, cad |
15 | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 13:1-13:36, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Field Programmable Compressor Tree (FPCT), compressor tree, Field Programmable Gate Array (FPGA) |
15 | Ira Neitzel, Uwe Prüfert, Thomas Slawig |
Strategies for time-dependent PDE control with inequality constraints using an integrated modeling and simulation environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Numer. Algorithms ![In: Numer. Algorithms 50(3), pp. 241-269, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Parabolic PDEs, Integrated modeling and simulation environments, Optimal control, Inequality constraints |
15 | Alexandre Belloni, Claudia A. Sagastizábal |
Dynamic bundle methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 120(2), pp. 289-311, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classification (2000) 90C25, 90C27, 65K05 |
15 | Majid Ahmadi, Ashkan Hosseinzadeh Namin, Karl Leboeuf, Huapeng Wu |
Artificial neural networks activation function HDL coder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 389-392, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Márcia Barros de Sales, Ricardo Azambuja Silveira, André Barros de Sales, Rita de Cássia Guarezi |
Learning by Peers: An Alternative Learning Model for Digital Inclusion of Elderly People. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCCE ![In: Education and Technology for a Better World, 9th IFIP TC 3 World Conference on Computers in Education, WCCE 2009, Bento Gonçalves, Brazil, July 27-31, 2009. Proceedings, pp. 436-444, 2009, Springer, 978-3-642-03114-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Learning by peers, third age digital inclusion |
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