Search results for "parasitics"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Hua Tang, Hui Zhang 0057, Alex Doboli	Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing.	ISVLSI	2003	DBLP DOI BibTeX RDF
12	Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Robert W. Heikaus, Okan Erdogan, Peter F. Curran, Bryan S. Goda, Kuan Zhou, John F. McDonald 0001	Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory.	FPL	2003	DBLP DOI BibTeX RDF
12	Venkatesan Rajappan, Sachin S. Sapatnekar	An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk.	ICCD	2003	DBLP DOI BibTeX RDF
12	Eugenio Culurciello, Andreas G. Andreou	An 8-bit, 1mW successive approximation ADC in SOI CMOS.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
12	Hua Tang, Hui Zhang 0057, Alex Doboli	Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	?? modulator, continuous-time filter, synthesis
12	M. C. Scott, M. O. Peralta, Jo Dale Carothers	System and Framework for QA of Process Design Kits.	ISQED	2003	DBLP DOI BibTeX RDF
12	Kris Tiri, Ingrid Verbauwhede	Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology.	CHES	2003	DBLP DOI BibTeX RDF
12	Massimo Alioto, Gaetano Palumbo	Analysis and comparison on full adder block in submicron technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
12	Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje	An analysis of the wire-load model uncertainty problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
12	Li Ding 0002, Pinaki Mazumder	Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling.	DATE	2002	DBLP DOI BibTeX RDF
12	Patrick Groeneveld	Physical Design Challenges for Billion Transistor Chips.	ICCD	2002	DBLP DOI BibTeX RDF
12	J. R. Moritz, Y. Sun	Automatic tuning of high frequency, high Q, multiple loop feedback bandpass filters.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
12	Manuel A. d'Abreu	Noise-Its Sources, and Impact on Design and Test of Mixed Signal Circuits.	DELTA	2002	DBLP DOI BibTeX RDF
12	Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang	VeriCDF: a new verification methodology for charged device failures.	DAC	2002	DBLP DOI BibTeX RDF	simulation, modeling, reliability
12	K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte	Analysis of Column Compression Multipliers.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
12	Håkan Bengtson, Christer Svensson	3V CMOS 0.35 µ transimpedance receiver for optical applications.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier.	ARVLSI	2001	DBLP DOI BibTeX RDF
12	Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell	Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations.	VLSI Design	2001	DBLP DOI BibTeX RDF
12	Martin Bächtold, Mirko Spasojevic, Christian Lage, Per B. Ljung	A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
12	Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov, David W. Winston	Transient sensitivity computation in controlled explicit piecewiselinear simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
12	Mohamed Dessouky, Marie-Minerve Louërat, Jacky Porte	Layout-Oriented Synthesis of High Performance Analog Circuits.	DATE	2000	DBLP DOI BibTeX RDF
12	Antonio G. M. Strollo, Ettore Napoli, Davide De Caro	New clock-gating techniques for low-power flip-flops.	ISLPED	2000	DBLP DOI BibTeX RDF	flip-fops, CMOS digital integrated circuits, transition probability, low-power circuits
12	Payam Heydari, Massoud Pedram	Analysis and Optimization of Ground Bounce in Digital CMOS Circuits.	ICCD	2000	DBLP DOI BibTeX RDF
12	Byungwoo Choi, D. M. H. Walker	Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation.	VTS	2000	DBLP DOI BibTeX RDF	interconnect coupling, delay fault model, process variation, timing analysis, delay fault test
12	Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal	Inductance Characterization of Small Interconnects Using Test-Signal Method.	VLSI Design	2000	DBLP DOI BibTeX RDF	Test-Signal Injection Method, Differential Circuit, Short Interconnects, Self and Mutual-Inductance, High Frequency Test Signal, Displacement Current, Lumped Package Models, Inductance, Characterization, Transmission Lines, Capacitance, Substrate
12	Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-Kuan Cheng	Block placement with symmetry constraints based on the O-tree non-slicing representation.	DAC	2000	DBLP DOI BibTeX RDF
12	Andrew B. Kahng, Sudhakar Muddu, Egino Sarto	On switch factor based analysis of coupled RC interconnects.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
12	Michael W. Beattie, Lawrence T. Pileggi	Error bounds for capacitance extraction via window techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
12	Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano	Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.	DATE	1999	DBLP DOI BibTeX RDF
12	Mattan Kamon, Steve McCormick, Ken Sheperd	Interconnect parasitic extraction in the digital IC design methodology.	ICCAD	1999	DBLP DOI BibTeX RDF
12	Alper Demir 0001, Peter Feldmann	Modeling and simulation of the interference due to digital switching in mixed-signal ICs.	ICCAD	1999	DBLP DOI BibTeX RDF
12	Bernard N. Sheehan	TICER: realizable reduction of extracted RC circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
12	Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor	Performance and Reliability Verification of C6201/C6701 Digital Signal Processors.	ICCD	1999	DBLP DOI BibTeX RDF
12	F. C. M. Kuijstermans, F. M. Diepstraten, Wouter A. Serdijn, Pieter van der Kloet, Arie van Staveren, Arthur H. M. van Roermund	The linear time-varying approach applied to a first-order dynamic translinear filter.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
12	Mark J. W. Rodwell, Q. Lee, Dino Mensa, J. Guthrie, Yoram Betser, S. C. Martin, R. P. Smith, S. Jaganathan, Thomas Mathew, P. Krishnan, C. Serhan, Stephen I. Long	Ultra high frequency integrated circuits using transferred substrate heterojunction bipolar transistors.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
12	Mircea R. Stan	Optimal Voltages and Sizing for Low Power.	VLSI Design	1999	DBLP DOI BibTeX RDF
12	Jinsong Zhao, Wayne Wei-Ming Dai, Sharad Kapur, David E. Long	Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green's Functions.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
12	Bogdan G. Arsintescu, Edoardo Charbon, Enrico Malavasi, Umakanta Choudhury, William H. Kao	General AC Constraint Transformation for Analog ICs.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
12	Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov	Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
12	Enrico Malavasi, Edoardo Charbon, Eric Felt, Alberto L. Sangiovanni-Vincentelli	Automation of IC layout with analog constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Desmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli	Digital sensitivity: predicting signal interaction using functional analysis.	ICCAD	1996	DBLP DOI BibTeX RDF	layout synthesis, Crosstalk, sensitivity, signal integrity
12	N. P. van der Meijs, T. Smedes	Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	Physical Design Verification, Interconnect Resistance Extraction, Interconnect Capacitance Extraction, Substrate Resistance Extraction, Interconnect Modeling
12	Enrico Malavasi, Davide Pandini	Optimum CMOS stack generation with analog constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
12	Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage	Time-domain macromodels for VLSI interconnect analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
12	Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli	Constraint-based channel routing for analog and mixed analog/digital circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli	Area routing for analog layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	John Y. Lee, Xiaoli Huang, Ronald A. Rohrer	Pole and zero sensitivity calculation in asymptotic waveform evaluation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
12	Luís Miguel Silveira, Jacob K. White 0001, Horácio C. Neto, Luís M. Vidigal	On exponential fitting for circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
12	J. Paul Harvey, Mohamed I. Elmasry, Bosco Leung	STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
12	B. Lokanathan, Edwin Kinnen	Performance optimized floor planning by graph planarization.	DAC	1989	DBLP DOI BibTeX RDF
12	Shun-Lin Su, Vasant B. Rao, Timothy N. Trick	HPEX: A Hierarchical Parasitic Circuit Extractor.	DAC	1987	DBLP DOI BibTeX RDF
12	R. D. Freeman, S. M. Kang, C. G. Lin-Hendel, M. L. Newby	Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning.	DAC	1986	DBLP DOI BibTeX RDF	SPICE