Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
34 | David Prutchi |
Electroceuticals - Replacing drugs by devices enabled through advanced VLSI technologies. |
VLSI-DAT |
2014 |
DBLP DOI BibTeX RDF |
|
34 | Sani R. Nassif, Yale N. Patt, Magdy S. Abadir |
Keynote 1 - VLSI 2.0: R&D Post Moore. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
34 | Mostafa Rahimi Azghadi, Said F. Al-Sarawi, Nicolangelo Iannella, Derek Abbott |
A new compact analog VLSI model for Spike Timing Dependent Plasticity. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
34 | Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak, Aljoscha Smolic |
Spatially-Varying Image Warping: Evaluations and VLSI Implementations. |
VLSI-SoC (Selected Papers) |
2012 |
DBLP DOI BibTeX RDF |
|
34 | Sandro Belfanti, Christian Benkeser, Karim Badawi, Qiuting Huang, Andreas Burg |
Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
34 | David Z. Pan, Jhih-Rong Gao, Bei Yu 0001 |
VLSI CAD for emerging nanolithography. |
VLSI-DAT |
2012 |
DBLP DOI BibTeX RDF |
|
34 | Siwat Saibua, Liuxi Qian, Dian Zhou |
Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Jialiang Liu, Xinhua Chen, Yibo Fan, Xiaoyang Zeng |
A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Yanan Sun 0003, Volkan Kursun |
Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Jiang Ying, Xinhua Chen, Yibo Fan, Xiaoyang Zeng |
MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Yang Chai, Minghui Sun, Zhiyong Xiao, Yuan Li, Min Zhang 0041, Philip C. H. Chan |
Towards future VLSI interconnects using aligned carbon nanotubes. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Christoph Studer, Markus Wenk, Andreas Burg |
VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems. |
VLSI-SoC (Selected Papers) |
2010 |
DBLP DOI BibTeX RDF |
|
34 | Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas |
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
delay reduction, Schmitt Trigger, Buffer Insertion, Power reduction |
34 | Gautam Hazari, Madhav P. Desai, G. Srinivas |
Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
|
34 | Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam |
Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
34 | S. Ramasamy, B. Venkataramani, K. Anbugeetha |
VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Giovanni De Micheli, Salvador Mir, Ricardo Reis 0001 (eds.) |
VLSI-SoC: Research Trends in VLSI and Systems on Chip - Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France |
VLSI-SoC (Selected Papers) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Sanghoan Chang, Gwan Choi |
Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
34 | |
VLSI Design 2005 Conference Awards. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Min Tang, Jun-Fa Mao |
Optimization of Global Interconnects in High Performance VLSI Circuits. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
34 | |
Call for Participation: 10th IEEE VLSI Design & Test Symposium. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
34 | |
VLSI Design 2006 Conference Awards. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
34 | |
VLSI Design Conference History. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
34 | |
Call for Participation: VLSI Design 2007. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Shekhar Borkar |
Probabilistic amp; Statistical Design - the Wave of the Future. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Lakshmi N. Chakrapani, Jason George, Bo Marr, Bilge Saglam Akgul, Krishna V. Palem |
Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Giovanni Beltrame, Donatella Sciuto, Cristina Silvano |
A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai |
Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Carlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, Augusto Nascetti, Davide Caputo, A. De Cesare |
Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Sam Kavusi, Kunal Ghosh, Abbas El Gamal |
Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Ulrich Bockelmann |
Electronic Detection of DNA Adsorption and Hybridization. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo |
Designing Routing and Message-Dependent Deadlock Free Networks on Chips. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Anna Bernasconi 0001, Valentina Ciriani, Roberto Cordone |
Logic Synthesis of EXOR Projected Sum of Products. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Shan Jiang, Manh Anh Do, Kiat Seng Yeo |
A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu |
CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz |
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Subhasish Mitra, Ming Zhang 0017, Norbert Seifert, T. M. Mak, Kee Sup Kim |
Soft Error Resilient System Design through Error Correction. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Arno Moonen, Chris Bartels, Marco Bekooij, René van den Berg, Harpreet Bhullar, Kees Goossens, Patrick Groeneveld, Jos Huisken, Jef L. van Meerbergen |
Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Antonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene |
Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Robert K. Henderson, Bruce Rae, David R. Renshaw, Edoardo Charbon |
Oversampled Time Estimation Techniques for Precision Photonic Detectors. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira |
Library Compatible Variational Delay Computation. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Jeff Brateman, Changjiu Xian, Yung-Hsiang Lu |
Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Julien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov |
Human++: Emerging Technology for Body Area Networks. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. |
VLSI-SoC (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Shekhar Borkar |
VLSI Design Challenges for Gigascale Integration. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Sabyasachi Mondal, Arijit De, P. K. Biswas |
A Low Power Reprogrammable Parallel Processing VLSI Architecture for Computation of B-Spline Based Medical Image Processing System for Fast Characterization of Tiny Objects Suspended in Cellular Fluid. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez |
Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Aniket, Ravishankar Arunachalam |
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Deng Lei, Wen Gao 0001, Ming-Zeng Hu, Zhenzhou Ji |
An Efficient VLSI Architecture for MC Interpolation in AVC Video Coding. |
ESA/VLSI |
2004 |
DBLP BibTeX RDF |
|
34 | Stephen Bates |
VLSI Issues for the Implementation of 10GBASE-T Ethernet. |
ESA/VLSI |
2004 |
DBLP BibTeX RDF |
|
34 | Jayapreetha Natesan, Damu Radhakrishnan |
A Novel Bus Encoding Technique for Low Power VLSI. |
ESA/VLSI |
2004 |
DBLP BibTeX RDF |
|
34 | Bassam Shaer, Kailash Aurangabadkar |
An Automated Algorithm for Partitioning Sequential VLSI Circuits. |
ESA/VLSI |
2004 |
DBLP BibTeX RDF |
|
34 | Rajiv V. Joshi, K. Kroell, Ching-Te Chuang |
A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Amardeep Singh |
Quantum Search Algorithm for Automated Test Pattern Generation in VLSI Testing. |
VLSI |
2003 |
DBLP BibTeX RDF |
|
34 | Evandro de Araújo Jardini, Dilvan de Abreu Moreira |
Multithreaded parallel VLSI Leaf Cell Generator Using Agents 2. |
VLSI |
2003 |
DBLP BibTeX RDF |
|
34 | Mamidala Jagadesh Kumar, D. Venkateshrao |
A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Srikar Movva, S. Srinivasan 0001 |
A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Koushik K. Das, Richard B. Brown |
Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Jong-Sheng Cherng, Sao-Jie Chen |
An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Rajeev Madhavan |
India-Building the Tall, Thin VLSI Engineer. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Hailong Cui, Sharad C. Seth, Shashank K. Mehta |
A Novel Method to Improve the Test Efficiency of VLSI Tests. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Kavish Seth, S. Srinivasan 0001 |
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
2D-DWT/IDWT Hardware, Non-expansive symmetric Extension, Canonic Signed Digit Arithmetic, Sub-expression Sharing, Low Power |
34 | Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta |
Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
VLSI Architecture for a Flexible Motion Estimation with Parameters. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Motion estimation, VHDL, Block matching |
34 | M. V. Atre, P. S. Subramanian, H. Narayanan |
Mathematical Methods in VLSI (Tutorial Abstract). |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Biswadip Mitra |
Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Sujit T. Zachariah, Sreejit Chakravarty |
A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Kaushik Roy 0001, Khurram Muhammad |
Low Power VLSI Signal Processing. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar |
Theory and Applications of Cellular Automata for VLSI Design and Testing. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Melvin A. Breuer, Sandeep K. Gupta 0001 |
New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
34 | S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin 0001 |
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri |
A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Sudip Nag, H. K. Verma, Kaushik Roy 0001 |
VLSI Signal Processing in FPGAs. |
VLSI Design |
1999 |
DBLP BibTeX RDF |
|
34 | Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang |
Modeling Crosstalk in Resistive VLSI Interconnections. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Shashank K. Mehta, Sharad C. Seth |
Empirical Computation of Reject Ratio in VLSI Testing. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Andrew B. Kahng, Sudhakar Muddu, Egino Sarto |
Interconnect Optimization Strategies for High-Performance VLSI Designs. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Stefan Thomas Obenaus, Ted H. Szymanski |
Placements Benchmarks for 3-D VLSI. |
VLSI |
1999 |
DBLP BibTeX RDF |
|
34 | Stefan Lachowicz, Kamran Eshraghian, Hans-Jörg Pfleiderer |
Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI. |
VLSI |
1999 |
DBLP BibTeX RDF |
|
34 | S. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin 0001 |
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Inseop Lee, W. Kenneth Jenkins |
The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
residue number, LMS, RNS |
34 | Rung-Bin Lin, Meng-Chiou Wu |
A New Statistical Approach to Timing Analysis of VLSI Circuits. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
Statistical timing anylysis, longest path delay, path correlation, timing simulation |
34 | Rajeev Jain, Charles Chien, Etan G. Cohen, Leader Ho |
Simulation and Synthesis of VLSI Communication Systems. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
DSP simulation, DSP design, Telecom |
34 | Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu |
A VLSI ATM Switch Architecture for VBR Traffic. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Debashis Saha, Anantha P. Chandrakasan |
Web-based Distributed VLSI Design. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili |
Design of a VLSI Hardware PET Decoder. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
34 | Milind B. Kamble, Kanad Ghose |
Energy-Efficiency of VLSI Caches: A Comparative Study. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
34 | Gary William Grewal, Thomas Charles Wilson |
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
34 | Anthony D. Johnson |
On Locally Optimal Breaking of Complex Cyclic Vertical Constraints in VLSI Channel Routing. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Seokjin Kim, Ramalingam Sridhar |
Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Maher E. Rizkalla, Richard L. Aldridge, Nadeem A. Khan, Harry C. Gundrum |
A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for ATM Applications. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu |
A Hierarchal Approach for Power Reduction in VLSI Chips. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
|
34 | A. Ratan Gupta, V. Visvanathan |
VLSI Implementation of DSP Architectures. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Anantha P. Chandrakasan, Kurt Keutzer, A. Khandekar, S. L. Maskara, B. D. Pradhan, Mani B. Srivastava |
Mobile Communications: Demands on VLSI Technology, Design and CAD. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Robert W. Brodersen, Rajeev Jain |
VLSI in Mobile Communication. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
34 | S. Mitra 0001, S. Das, Parimal Pal Chaudhuri, Sukumar Nandi |
Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Jacob A. Abraham, Gopi Ganapathy |
Practical Test and DFT for Next Generation VLSI. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Pallab Dasgupta, Prasenjit Mitra, P. P. Chakrabarti 0001, S. C. De Sarkar |
Multiobjective Search in VLSI Design. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Tanuj Bagchi, Sajal K. Das 0001 |
An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Mario Kovac, N. Ranganathan |
ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Abhaya Asthana, Mike Laznovsky, Boyd Mathews |
SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|