Search results for "ATS"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Laura Rodríguez Gómez, Hans-Joachim Wunderlich	A Neural-Network-Based Fault Classifier.	ATS	2016	DBLP DOI BibTeX RDF
1	Kazuki Shirahata, Takeshi Mizushima, Tasuku Fujibe, Hidenobu Matsumura, Tomoyuki Itakura, Masahiro Ishida, Daisuke Watanabe, Shin Masuda	An Optical Interconnection Test Method Applicable to 100-Gb/s Transceivers Using an ATE Based Hardware.	ATS	2016	DBLP DOI BibTeX RDF
1	Warin Sootkaneung, Sasithorn Chookaew, Suppachai Howimanporn	Combined Impact of BTI and Temperature Effect Inversion on Circuit Performance.	ATS	2016	DBLP DOI BibTeX RDF
1	Amir Masoud Gharehbaghi, Masahiro Fujita	A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality.	ATS	2016	DBLP DOI BibTeX RDF
1	M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman	A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction.	ATS	2016	DBLP DOI BibTeX RDF
1	Sayandeep Mitra, Moumita Das, Ansuman Banerjee, Kausik Datta, Tsung-Yi Ho	A Verification Guided Approach for Selective Program Transformations for Approximate Computing.	ATS	2016	DBLP DOI BibTeX RDF
1	Sujay Pandey, Sabyasachi Deyati, Adit D. Singh, Abhijit Chatterjee	Noise-Resilient SRAM Physically Unclonable Function Design for Security.	ATS	2016	DBLP DOI BibTeX RDF
1	Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang, Cheng-Wen Wu	Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation.	ATS	2016	DBLP DOI BibTeX RDF
1	Po-Fan Hou, Yi-Tsung Lin, Jiun-Lang Huang, Ann Shih, Zoe F. Conroy	An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing.	ATS	2016	DBLP DOI BibTeX RDF
1	Matthias Kampmann, Sybille Hellebrand	X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test.	ATS	2016	DBLP DOI BibTeX RDF
1	Riccardo Cantoro, Marco Palena, Paolo Pasini, Matteo Sonza Reorda	Test Time Minimization in Reconfigurable Scan Networks.	ATS	2016	DBLP DOI BibTeX RDF
1	Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee	Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits.	ATS	2016	DBLP DOI BibTeX RDF
1		25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016	ATS	2016	DBLP BibTeX RDF
1	Hao Shen, Lance Shen, Pierce Xu, Wu Yang, Junna Zhong	Application of Data Mining Based Scan Diagnosis Yield Analysis in a Foundry and Fabless Working Environment.	ATS	2016	DBLP DOI BibTeX RDF
1	Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li 0001	Testing Inter-Word Coupling Faults of Wide I/O DRAMs.	ATS	2015	DBLP DOI BibTeX RDF
1	Srinivasa Shashank Nuthakki, Santanu Chattopadhyay	An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets.	ATS	2015	DBLP DOI BibTeX RDF
1	Matthias Kampmann, Michael A. Kochte, Eric Schneider, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich	Optimized Selection of Frequencies for Faster-Than-at-Speed Test.	ATS	2015	DBLP DOI BibTeX RDF
1	Zhou Jiang, Dong Xiang, Kele Shen	A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test.	ATS	2015	DBLP DOI BibTeX RDF
1	Guopei Liu, Ying Wang 0001, Sen Li, Huawei Li 0001, Xiaowei Li 0001	A Lightweight Timing Channel Protection for Shared Memory Controllers.	ATS	2015	DBLP DOI BibTeX RDF
1	Payman Behnam, Bijan Alizadeh	In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms.	ATS	2015	DBLP DOI BibTeX RDF
1	Riccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson	On the testability of IEEE 1687 networks.	ATS	2015	DBLP DOI BibTeX RDF
1	Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada	A Technique for Analyzing On-Chip Power Supply Impedance.	ATS	2015	DBLP DOI BibTeX RDF
1	Swagata Mandal, Suman Sau, Amlan Chakrabarti, Sushanta Kumar Pal, Subhasish Chattopadhyay	FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code.	ATS	2015	DBLP DOI BibTeX RDF
1	Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume	Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories.	ATS	2015	DBLP DOI BibTeX RDF
1	Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay	Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints.	ATS	2015	DBLP DOI BibTeX RDF
1	Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa	A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions.	ATS	2015	DBLP DOI BibTeX RDF
1	Sukrat Gupta, Neel Gala, G. S. Madhusudan, V. Kamakoti 0001	SHAKTI-F: A Fault Tolerant Microprocessor Architecture.	ATS	2015	DBLP DOI BibTeX RDF
1	Virendra Singh, Adit D. Singh, Kewal K. Saluja	A Methodology for Identifying High Timing Variability Paths in Complex Designs.	ATS	2015	DBLP DOI BibTeX RDF
1	Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path.	ATS	2015	DBLP DOI BibTeX RDF
1	Josef Kinseher, Leonardo Bonet Zordan, Ilia Polian	On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs.	ATS	2015	DBLP DOI BibTeX RDF
1	Tino Flenker, André Sülflow, Görschwin Fey	Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation.	ATS	2015	DBLP DOI BibTeX RDF
1	Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen	At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic.	ATS	2015	DBLP DOI BibTeX RDF
1	Joyati Mondal, Debesh K. Das, Bhargab B. Bhattacharya	Design-for-testability in reversible logic circuits based on bit-swapping.	ATS	2015	DBLP DOI BibTeX RDF
1	Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee	Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security.	ATS	2015	DBLP DOI BibTeX RDF
1	Jun Zhou 0022, Huawei Li 0001, Tiancheng Wang, Sen Li, Ying Wang 0001, Xiaowei Li 0001	TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs.	ATS	2015	DBLP DOI BibTeX RDF
1	Ashwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Helia Naeimi, Arijit Raychowdhury	A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays.	ATS	2015	DBLP DOI BibTeX RDF
1	Adithyalal P. M, Shankar Balachandran, Virendra Singh	A Soft Error Resilient Low Leakage SRAM Cell Design.	ATS	2015	DBLP DOI BibTeX RDF
1	Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li	Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits.	ATS	2015	DBLP DOI BibTeX RDF
1	Hejia Liu, Vishwani D. Agrawal	Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key.	ATS	2015	DBLP DOI BibTeX RDF
1	Xijiang Lin, Wu-Tung Cheng, Janusz Rajski	On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults.	ATS	2015	DBLP DOI BibTeX RDF
1		24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015	ATS	2015	DBLP BibTeX RDF
1	Saikat Dutta 0001, Soumi Chattopadhyay, Ansuman Banerjee, Pallab Dasgupta	A New Approach for Minimal Environment Construction for Modular Property Verification.	ATS	2015	DBLP DOI BibTeX RDF
1	Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara	A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation.	ATS	2015	DBLP DOI BibTeX RDF
1	Dooyoung Kim, Muhammad Adil Ansari, Jihun Jung, Sungju Park	Scan-Puf: Puf Elements Selection Methods for Viable IC Identification.	ATS	2015	DBLP DOI BibTeX RDF
1	Sungyoul Seo, Yong Lee 0002, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang 0001	Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction.	ATS	2015	DBLP DOI BibTeX RDF
1	Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh	A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan.	ATS	2015	DBLP DOI BibTeX RDF
1	V. Prasanth, Rubin A. Parekhji, Bharadwaj S. Amrutur	Improved Methods for Accurate Safety Analysis of Real-Life Systems.	ATS	2015	DBLP DOI BibTeX RDF
1	Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang	SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator.	ATS	2015	DBLP DOI BibTeX RDF
1	Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian	Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch.	ATS	2015	DBLP DOI BibTeX RDF
1	Michael A. Kochte, Atefe Dalirsani, Andrea Bernabei, Martin Omaña 0001, Cecilia Metra, Hans-Joachim Wunderlich	Intermittent and Transient Fault Diagnosis on Sparse Code Signatures.	ATS	2015	DBLP DOI BibTeX RDF
1	Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang 0014	TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm.	ATS	2015	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification.	ATS	2015	DBLP DOI BibTeX RDF
1	Emil Gizdarski	Two-Step Dynamic Encoding for Linear Decompressors.	ATS	2014	DBLP DOI BibTeX RDF
1	Kuan-Te Wu, Jin-Fu Li 0001, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo	Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.	ATS	2014	DBLP DOI BibTeX RDF
1	Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich	High Quality System Level Test and Diagnosis.	ATS	2014	DBLP DOI BibTeX RDF
1	Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer	High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs.	ATS	2014	DBLP DOI BibTeX RDF
1	Chandan Kumar, Fadi Maamari, Kiran Vittal, Wilson Pradeep, Rajesh Tiwari, Srivaths Ravi 0001	Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs.	ATS	2014	DBLP DOI BibTeX RDF
1	Mehdi Sadi, Zoe Conroy, Bill Eklow, Matthias Kamm, Nematollah Bidokhti, Mark Mohammad Tehranipoor	An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs.	ATS	2014	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura	An On-Chip Digital Environment Monitor for Field Test.	ATS	2014	DBLP DOI BibTeX RDF
1	Huaguo Liang, Zhi Wang, Zhengfeng Huang, Aibin Yan	Design of a Radiation Hardened Latch for Low-Power Circuits.	ATS	2014	DBLP DOI BibTeX RDF
1	Yun-Chao You, Chi-Chun Yang, Jin-Fu Li 0001, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu	BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.	ATS	2014	DBLP DOI BibTeX RDF
1	Harry H. Chen	Perspectives on Test Data Mining from Industrial Experience.	ATS	2014	DBLP DOI BibTeX RDF
1	Jizhe Zhang, Sandeep Gupta 0001	SRAM Array Yield Estimation under Spatially-Correlated Process Variation.	ATS	2014	DBLP DOI BibTeX RDF
1	Cheng Xue, R. D. (Shawn) Blanton	Predicting IC Defect Level Using Diagnosis.	ATS	2014	DBLP DOI BibTeX RDF
1	Taewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang 0001	A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System.	ATS	2014	DBLP DOI BibTeX RDF
1	Da Cheng, Fangzhou Wang, Feng Gao, Sandeep K. Gupta 0001	Optimal Redundancy Designs for CNFET-Based Circuits.	ATS	2014	DBLP DOI BibTeX RDF
1	Byeongju Cha, Sandeep K. Gupta 0001	A Resizing Method to Minimize Effects of Hardware Trojans.	ATS	2014	DBLP DOI BibTeX RDF
1	Fan Yang 0060, Sreejit Chakravarty, Arun Gunda, Nicole Wu, Jianyu Ning	Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests.	ATS	2014	DBLP DOI BibTeX RDF
1	Masanori Hashimoto	Opportunities and Verification Challenges of Run-Time Performance Adaptation.	ATS	2014	DBLP DOI BibTeX RDF
1	Kelson Gent, Michael S. Hsiao	Dual-Purpose Mixed-Level Test Generation Using Swarm Intelligence.	ATS	2014	DBLP DOI BibTeX RDF
1	Shao-Feng Hung, Long-Yi Lin, Hao-Chiao Hong	A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles.	ATS	2014	DBLP DOI BibTeX RDF
1	Jose Moreira, Hubert Werkmann, Masahiro Ishida, Bernhard Roth, Volker Filsinger, Sui-Xia Yang	An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing Solution.	ATS	2014	DBLP DOI BibTeX RDF
1	Bappaditya Mondal, Dipak Kumar Kole, Debesh Kumar Das, Hafizur Rahaman 0001	Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method.	ATS	2014	DBLP DOI BibTeX RDF
1	John A. Porche, R. D. (Shawn) Blanton	Physically-Aware Diagnostic Resolution.	ATS	2014	DBLP DOI BibTeX RDF
1	Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng	Learning from Production Test Data: Correlation Exploration and Feature Engineering.	ATS	2014	DBLP DOI BibTeX RDF
1	Yong-Xiao Chen, Jin-Fu Li 0001	Testing of Non-volatile Logic-Based System Chips.	ATS	2014	DBLP DOI BibTeX RDF
1	Xiaobing Shi, Nicola Nicolici	On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli.	ATS	2014	DBLP DOI BibTeX RDF
1	Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, Cheng-You Ho, Yingchieh Ho, Ruei-Ting Gu, Bo-Chuan Cheng	Optimized Pre-bond Test Methodology for Silicon Interposer Testing.	ATS	2014	DBLP DOI BibTeX RDF
1	Vasileios Tenentes, S. Saqib Khursheed, Bashir M. Al-Hashimi, Shida Zhong, Sheng Yang 0003	High Quality Testing of Grid Style Power Gating.	ATS	2014	DBLP DOI BibTeX RDF
1	Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Arnaud Virazel, Etienne Auvray	On the Generation of Diagnostic Test Set for Intra-cell Defects.	ATS	2014	DBLP DOI BibTeX RDF
1	Li Ling, Jianhui Jiang	Exploit Dynamic Voltage and Frequency Scaling for SoC Test Scheduling under Thermal Constraints.	ATS	2014	DBLP DOI BibTeX RDF
1	Yu Bi, Pierre-Emmanuel Gaillardon, Xiaobo Sharon Hu, Michael T. Niemier, Jiann-Shiun Yuan, Yier Jin	Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs.	ATS	2014	DBLP DOI BibTeX RDF
1	Cheng-Hung Wu, Kuen-Jong Lee	An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults.	ATS	2014	DBLP DOI BibTeX RDF
1	Jie Zou, Chao Han, Adit D. Singh	Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing.	ATS	2014	DBLP DOI BibTeX RDF
1	Kun-Han Tsai	Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large Designs.	ATS	2014	DBLP DOI BibTeX RDF
1		23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014	ATS	2014	DBLP BibTeX RDF
1	Dominik Erb, Karsten Scheibler, Matthias Sauer 0002, Sudhakar M. Reddy, Bernd Becker 0001	Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects.	ATS	2014	DBLP DOI BibTeX RDF
1	Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-Baath	Design, Verification, and Application of IEEE 1687.	ATS	2014	DBLP DOI BibTeX RDF
1	Kele Shen, Dong Xiang, Zhou Jiang	Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond Testing.	ATS	2014	DBLP DOI BibTeX RDF
1	Guillaume Renaud, Manuel J. Barragán, Salvador Mir, Marc Sabut	On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test.	ATS	2014	DBLP DOI BibTeX RDF
1	Zipeng Li, Trung Anh Dinh, Tsung-Yi Ho, Krishnendu Chakrabarty	Reliability-Driven Pipelined Scan-Like Testing of Digital Microfluidic Biochips.	ATS	2014	DBLP DOI BibTeX RDF
1	Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura	Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test.	ATS	2014	DBLP DOI BibTeX RDF
1	Anshuman Chandra, Subramanian Chebiyam, Rohit Kapur	A Case Study on Implementing Compressed DFT Architecture.	ATS	2014	DBLP DOI BibTeX RDF
1	Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara	Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories.	ATS	2014	DBLP DOI BibTeX RDF
1	Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang	FPGA-Based Subset Sum Delay Lines.	ATS	2014	DBLP DOI BibTeX RDF
1	Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee	High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure.	ATS	2014	DBLP DOI BibTeX RDF
1	Yukio Mitsuyama, Hidetoshi Onodera	Variability and Soft-Error Resilience in Dependable VLSI Platform.	ATS	2014	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Che-Wei Kao, Katherine Shu-Min Li	Improving Output Compaction Efficiency with High Observability Scan Chains.	ATS	2014	DBLP DOI BibTeX RDF
1	Yun Cheng, Huawei Li 0001, Xiaowei Li 0001	An On-Line Timing Error Detection Method for Silicon Debug.	ATS	2014	DBLP DOI BibTeX RDF
1	Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue	Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units.	ATS	2014	DBLP DOI BibTeX RDF

Publications at "ATS"( http://dblp.L3S.de/Venues/ATS )