|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 382 occurrences of 260 keywords
|
|
|
Results
Found 861 publication records. Showing 859 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Aibin Yan, Zijie Zhai, Lele Wang 0011, Jixiang Zhang 0007, Ningning Cui, Tianming Ni, Xiaoqing Wen |
Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: IEEE International Test Conference in Asia, ITC-Asia 2021, Shanghai, China, August 18-20, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-1334-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen |
A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021., pp. 301-306, 2021, ACM, 978-1-4503-8393-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard 0001 |
Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021., pp. 307-312, 2021, ACM, 978-1-4503-8393-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Peiyi Zhao, Zisong Wang, Congyi Zhu, Tom Springer, Jacob Anabi, Yinshui Xia, Lingli Wang |
Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Songyan Wang, Xiaomei Fan, Zhihua Zhu, Yingtao Zhang, Ruike Chen, Juin Jei Liou |
A LVTSCR-Based Compact Structure for Latch-up Immune. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Sandeep Kumar, Atin Mukherjee 0001 |
A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1609-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Zhenxing Chang, Aijiao Cui, Ziming Wang, Gang Qu 0001 |
Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 22nd International Symposium on Quality Electronic Design, ISQED 2021, Santa Clara, CA, USA, April 7-9, 2021, pp. 244-250, 2021, IEEE, 978-1-7281-7641-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Gaeryun Sung, Jaeduk Han |
High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 377-378, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Jérôme Folla Kamdem, Wembe Tafo Evariste, Essimbi Zobo Bernard, Maria Liz Crespo, Andres Cicuttin |
A Compact 20GHz Dynamic Latch Comparator in 65nm CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSD ![In: 18th International Multi-Conference on Systems, Signals & Devices, SSD 2021, Monastir, Tunisia, March 22-25, 2021, pp. 1177-1181, 2021, IEEE, 978-1-6654-1493-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Mahesh Kumawat, Abhishek Kumar Upadhyay, Sanjay Sharma, Ravi Kumar 0006, Gaurav Singh, Santosh Kumar Vishvakarma |
An improved current mode logic latch for high-speed applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Commun. Syst. ![In: Int. J. Commun. Syst. 33(13), 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Xiangfeng Feng, Yuanjie Hu, Chaoping Lai, Jie Cui 0004, Zhili Chen, Kohei Miyase, Xiaoqing Wen |
Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Aerosp. Electron. Syst. ![In: IEEE Trans. Aerosp. Electron. Syst. 56(2), pp. 1163-1171, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Zhelong Xu, Kang Yang, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen |
A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Aerosp. Electron. Syst. ![In: IEEE Trans. Aerosp. Electron. Syst. 56(4), pp. 2666-2676, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Kuan-Chieh Chao, Jung-Chin Lai, Terng-Yin Hsu |
All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 42082-42096, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Qiang Li, Xiaohui Su, Jing Guo 0004, Chunhua Qi |
Self-Recovery Tolerance Latch Design Based on the Radiation Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 220152-220164, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Nan Zhang, Xiaohui Su, Jing Guo 0004 |
Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 126582-126590, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Suraj Pattanaik |
A novel approach to design a digital clock triggered modified pulse latch for 16-bit shift register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Intell. Def. Support Syst. ![In: Int. J. Intell. Def. Support Syst. 6(1), pp. 21-34, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Adam Watkins, Spyros Tragoudas |
Radiation Hardened Latch Designs for Double and Triple Node Upsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 8(3), pp. 616-626, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Yuanjie Hu, Jie Cui 0004, Zhili Chen, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen |
Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 69(6), pp. 789-799, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar 0006, Gaurav Singh, Santosh Kumar Vishvakarma |
A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(7), pp. 2050110:1-2050110:14, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Bing Li, Shuai Chen, Kai Wang |
An improved PAAs countermeasure based on permutation tables and latch PUF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 63(3), 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Sanjay Vidhyadharan, Surya Shankar Dan, Ramakant Yadav, Simhadri Hariprasad |
An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 104, pp. 104879, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Yong Ma, Yongjian Yu, Jian Lu, Qiaoyun Zou, Huibin Zhang |
Effect of manufacturing technics on the microstructure and temperature-affected electrical performance of D-type latch devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 99, pp. 104757, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Joseph Sweeney, Mohammed Zackriya V, Samuel Pagliarini, Lawrence T. Pileggi |
Latch-Based Logic Locking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2005.10649, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
16 | Yuta Yamamoto, Kazuteru Namba |
Complete Double Node Upset Tolerant Latch Using C-Element. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 103-D(10), pp. 2125-2132, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Yibo Jiang, Hui Bi 0003, Wei Zhao, Chen Shi, Xiaolei Wang |
Latch-Up Immune Bi-Direction ESD Protection Clamp for Push-Pull RF Power Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 103-C(4), pp. 194-196, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Yan Li 0084, Xu Cheng 0002, Chiyu Tan, Jun Han 0003, Yuanfu Zhao, Liang Wang 0024, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng |
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(9), pp. 1619-1623, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Yafei Ling, Jie Cui 0004, Zhili Chen, Zhengfeng Huang, Jie Song, Patrick Girard 0001, Xiaoqing Wen |
Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3), pp. 879-890, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang |
Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(10), pp. 2119-2123, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Siddharth R. K., Y. Jaya Satyanarayana, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni |
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. ![In: IEEE Trans. Circuits Syst. 67-II(12), pp. 2918-2922, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Jing Guo 0004, Shanshan Liu 0001, Lei Zhu 0004, Fabrizio Lombardi |
Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(6), pp. 1925-1935, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Saki Tajima, Masao Yanagisawa, Youhua Shi |
Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(6), pp. 1114-1118, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Xinchao Shang, Minyi Lu, Chengjun Wu, Yiming Xiang, Jiaming Xu, Weiwei Shan |
A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. ![In: IEEE Trans. Circuits Syst. 67-I(11), pp. 3933-3943, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Joonyeong Kim, Byung-Kil Han, Dongbum Pyo, Semin Ryu, Hanbyeol Kim, Dong-Soo Kwon |
Braille Display for Portable Device Using Flip-Latch Structured Electromagnetic Actuator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Haptics ![In: IEEE Trans. Haptics 13(1), pp. 59-65, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel |
Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, pp. 574-579, 2020, IEEE, 978-3-9819263-4-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Zeeshan Ali, Makwana Harshit R, Shalabh Gupta |
A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020, Glasgow, Scotland, UK, November 23-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6044-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Zhiyang Qu, Lubin Hang, Huiyu Deng, Xiaobo Huang, Mingyuan Wang 0002, Xiaojie Huang, Zhe Liu, Yong Chen, Yong Hua, Jinliang Du |
Control System of Single-drive Double-branch Electric Vehicle Door Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RICAI ![In: RICAI 2020: 2nd International Conference on Robotics, Intelligent Control and Artificial Intelligence, Shanghai, China, October, 2020, pp. 440-444, 2020, ACM, 978-1-4503-8830-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Borui Wu, Lubin Hang, Xiaojie Huang, Sulong Li, Xiaobo Huang, Mingyuan Wang 0002, Chuanlei Zhong, Zhiyang Qu |
Double Loops Mechanism with Multi-Mode Motion Applied in The Vehicle Door Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RICAI ![In: RICAI 2020: 2nd International Conference on Robotics, Intelligent Control and Artificial Intelligence, Shanghai, China, October, 2020, pp. 69-73, 2020, ACM, 978-1-4503-8830-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Chuanlei Zhong, Lubin Hang, Mingyuan Wang 0002, Sulong Li, Xiaobo Huang, Xiaojie Huang, Zhe Liu, Yong Chen |
Research on A Spatial Compliant Mechanism for the Power Release Branch in Vehicle Side Door Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RICAI ![In: RICAI 2020: 2nd International Conference on Robotics, Intelligent Control and Artificial Intelligence, Shanghai, China, October, 2020, pp. 435-439, 2020, ACM, 978-1-4503-8830-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Abdulhadi Shoufan |
SR Latch: The Wrong Introduction to Digital Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Joseph Sweeney, V. Mohammed Zackriya, Samuel Pagliarini, Lawrence T. Pileggi |
Latch-Based Logic Locking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2020, San Jose, CA, USA, December 7-11, 2020, pp. 132-141, 2020, IEEE, 978-1-7281-7405-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Ziwei Li, Wenbin He, Fan Ye 0001, Junyan Ren |
A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020, Ha Long, Vietnam, December 8-10, 2020, pp. 39-42, 2020, IEEE, 978-1-7281-9396-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui 0004, Zuobin Ying, Patrick Girard 0001, Xiaoqing Wen |
HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang |
Latch Clustering for Timing-Power Co-Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Hanwool Jeong, Juhyun Park, Seung Chul Song, Seong-Ook Jung |
Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(8), pp. 2304-2315, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Chaudhry Indra Kumar, Anand Bulusu |
High performance energy efficient radiation hardened latch for low voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 66, pp. 119-127, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Deok Gyoon Chung, Joonhwan Kim, Donghoon Baek, Joonyeong Kim, Dong-Soo Kwon |
Shape-Locking Mechanism of Flexible Joint Using Mechanical Latch With Electromagnetic Force. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Robotics Autom. Lett. ![In: IEEE Robotics Autom. Lett. 4(3), pp. 2661-2668, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Huimei Cheng, Hsiao-Lun Wang, Minghe Zhang, Dylan Hand, Peter A. Beerel |
Automatic Retiming of Two-Phase Latch-Based Resilient Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7), pp. 1305-1316, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Xixi Dai, Haibin Wang, Jiamin Chu, Zhi Liu 0004, Li Cai, Kang Yan |
A Single Event Upset Resilient Latch Design with Single Node Upset Immunity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 35(6), pp. 909-916, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Chaudhry Indra Kumar, Arvind Kumar Sharma, Rajendra Partap, Anand Bulusu |
An energy-efficient variation aware self-correcting latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 84, pp. 67-78, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Cody Mitchell, Mitchell R. Hunt, Fat D. Ho |
Retention characteristics of a nonvolatile latch utilizing a ferroelectric transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 84, pp. 122-128, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Jinwook Jung, Gi-Joon Nam, Woohyun Chung, Youngsoo Shin |
Integrated Latch Placement and Cloning for Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 24(2), pp. 22:1-22:17, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Huimei Cheng, Yichen Gu, Peter A. Beerel |
Automatic Conversion from Flip-flop to 3-phase Latch-based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1906.10666, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
16 | Mir Muntasir Hossain, Satyendra N. Biswas |
Analysis and Design of a 32nm FinFET Dynamic Latch Comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1910.00098, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
16 | Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya |
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3), pp. 1231-1244, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Dhruv Patel 0002, Adam Neale, Derek Wright, Manoj Sachdev |
Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7), pp. 2519-2532, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Kang Yang, Zhengfeng Huang, Jiliang Zhang 0002, Jie Cui 0004, Xiangsheng Fang, Maoxiang Yi, Xiaoqing Wen |
A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 66-II(2), pp. 287-291, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Jianwei Jiang 0001, Yiran Xu, Wenyi Zhu, Jun Xiao, Shichang Zou |
Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3), pp. 967-977, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao 0007, Xuan Li, Junning Chen, Xuan Zeng 0001, Xiangdong Hu |
A single event upset tolerant latch with parallel nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 16(11), pp. 20190208, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Chun-Cheng Chen, Ming-Dou Ker |
Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2019, Monterey, CA, USA, March 31 - April 4, 2019, pp. 1-4, 2019, IEEE, 978-1-5386-9504-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva |
Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2019, Monterey, CA, USA, March 31 - April 4, 2019, pp. 1-4, 2019, IEEE, 978-1-5386-9504-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Yuanjie Hu, Jie Song, Xiaoqing Wen |
Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, pp. 1679-1684, 2019, IEEE, 978-3-9819263-2-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Daniel Townley, Khaled N. Khasawneh, Dmitry Ponomarev 0001, Nael B. Abu-Ghazaleh, Lei Yu 0001 |
LATCH: A Locality-Aware Taint CHecker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019., pp. 969-982, 2019, ACM, 978-1-4503-6938-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu |
STAHL: A Novel Scan-Test-Aware Hardened Latch Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 24th IEEE European Test Symposium, ETS 2019, Baden-Baden, Germany, May 27-31, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1173-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa |
A light-weight implementation of latch-based true random number generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: 15th International Wireless Communications & Mobile Computing Conference, IWCMC 2019, Tangier, Morocco, June 24-28, 2019, pp. 901-906, 2019, IEEE, 978-1-5386-7747-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, Patrick Girard 0001, Xiaoqing Wen |
Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 28th IEEE Asian Test Symposium, ATS 2019, Kolkata, India, December 10-13, 2019, pp. 43-48, 2019, IEEE, 978-1-7281-2695-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Fabián Leonardo Cabrera, Fernando Rangel de Sousa, Héctor Pettenghi |
Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 10th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2019, Armenia, Colombia, February 24-27, 2019, pp. 61-64, 2019, IEEE, 978-1-7281-0453-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Ambika Prasad Shah, Michael Waltl |
Low Cost and High Performance Radiation Hardened Latch Design for Reliable Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, pp. 197-200, 2019, IEEE, 978-1-7281-0996-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Zhaochen Yin, Walter Audoglio, Marco Grassi, Piero Malcovati, Edoardo Bonizzoni |
Performance Comparison of a Strong-Arm Latch in Different Ultra-Scaled Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, pp. 274-277, 2019, IEEE, 978-1-7281-0996-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Athanasios T. Ramkaj, Michiel S. J. Steyaert, Filip Tavernier |
A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, September 23-26, 2019, pp. 167-170, 2019, IEEE, 978-1-7281-1550-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Emanuele Abbatessa, Davide Dente, Sergio Saponara |
Integrated Simulation Environment for Co-design/Verification of Mechanic, Electronic and Control of Automotive E-Drives: The Smart-Latch Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ApplePies ![In: Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2019, Pisa, Italy, 11-13 September 2019, pp. 413-424, 2019, Springer, 978-3-030-37276-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Sulong Li, Lubin Hang, Mingyuan Wang 0002, Lele Bai, Xiaobo Huang, Huiyu Deng, Zhe Liu, Yong Chen, Yong Hua, Jinliang Du |
Research on Four-bar Linkage with Variable Axis Torsion Spring for Vehicle Latch Lock/Unlock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RICAI ![In: RICAI 2019: International Conference on Robotics, Intelligent Control and Artificial Intelligence, Shanghai, China, 20-22 September, 2019., pp. 153-158, 2019, ACM, 978-1-4503-7298-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Xu Su, Lubin Hang, Hui Guo, Mingyuan Wang 0002, Zhe Liu, Yong Chen, Yong Hua, Jinliang Du |
Simulation Research of Gear Recovery Noise in Electric Opening Branch with the Vehicle Door Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RICAI ![In: RICAI 2019: International Conference on Robotics, Intelligent Control and Artificial Intelligence, Shanghai, China, 20-22 September, 2019., pp. 122-126, 2019, ACM, 978-1-4503-7298-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001, Vivek De, Sanu Mathew |
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, pp. 32-, 2019, IEEE, 978-4-86348-720-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Troy Bryant, Taewook Kim, Nima Maghari |
A Self-Reset Transconductance Integrating Leakage Latch (STILL) for Ultra-Low Power Sensor Interfacing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Zhiyuan Song, Aibin Yan, Jie Cui 0004, Zhili Chen, Xuejun Li, Xiaoqing Wen, Chaoping Lai, Zhengfeng Huang, Huaguo Liang |
A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019, pp. 139-144, 2019, IEEE, 978-1-7281-4718-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Pingshun Ma, Yongzhen Chen, Jiangfeng Wu |
A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019, pp. 1-3, 2019, IEEE, 978-1-7281-0735-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Muneeb Sulthan, Shubhajit Roy Chowdury, Rajnish Garg, Alok Tripathi |
Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers, pp. 532-540, 2019, Springer, 978-981-32-9766-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Wei Wang 0177, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins |
A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(10), pp. 2783-2794, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta |
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(7), pp. 1902-1912, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Amir Ardakani, Shahriar B. Shokouhi, Arash Reyhani-Masoleh |
Improving performance of FPGA-based SR-latch PUF using Transient Effect Ring Oscillator and programmable delay lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 62, pp. 371-381, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Mitesh Limachia, Dixit Vyas, Rajesh Amratlal Thakker, Nikhil Kothari |
Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 62, pp. 258-269, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi |
A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7), pp. 1025-1034, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Leïla Khanfir, Jaouhar Mouine |
Design optimisation procedure for digital mismatch compensation in latch comparators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 12(6), pp. 726-734, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Ramin Razmdideh, Mohsen Saneei |
Low-power, latch-based multistage time-to-digital converter in 65 nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 46(6), pp. 1264-1271, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Aravinda Koithyar, T. K. Ramesh 0001 |
A faster phase frequency detector using transmission gate-based latch for the reduced response time of the PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 46(4), pp. 842-854, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Nima Shahpari, Mehdi Habibi |
A rail-to-rail low-power latch comparator with time domain bulk-tuned offset cancellation for low-voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 46(11), pp. 1968-1984, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Vijay Savani, N. M. Devashrayee |
Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 74, pp. 116-126, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Joy Arulraj, Justin J. Levandoski, Umar Farooq Minhas, Per-Åke Larson |
BzTree: A High-Performance Latch-free Range Index for Non-Volatile Memory. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. VLDB Endow. ![In: Proc. VLDB Endow. 11(5), pp. 553-565, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Haibin Wang, Xixi Dai, Yangsheng Wang, Issam Nofal, Li Cai, Zicai Shen, Wanxiu Sun, Jinshun Bi, Bo Li 0051, Gang Guo, Li Chen 0001, Sang H. Baeg |
A single event upset tolerant latch design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 88-90, pp. 909-913, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Oh-Yong Jung, Hyun-Gi Seok, Anjana Dissanayake, Sang-Gug Lee 0001 |
A 45-µW, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(11), pp. 1579-1583, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Dianpeng Lin, Yiran Xu, Xiaoyun Li, Xin Xie, Jianwei Jiang 0001, Jiangchuan Ren, Huilong Zhu, Zhengxuan Zhang, Shichang Zou |
A novel self-recoverable and triple nodes upset resilience DICE latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(19), pp. 20180753, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Yuanqing Li, Anselm Breitenreiter, Marko S. Andjelkovic, Oliver Schrape, Milos Krstic |
Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2018, Budapest, Hungary, April 25-27, 2018, pp. 9-14, 2018, IEEE, 978-1-5386-5754-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Mohammed Al-Qadasi, Abdullah Alshehri 0003, Abdullah S. Almansouri, Talal Al-Attar, Hossein Fariborzi |
A High Speed Dynamic StrongARM Latch Comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 540-541, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Karim Ali 0004, Fei Li 0015, Sunny Y. H. Lua, Chun-Huat Heng |
Area and Energy Efficient Diode Based Spin Orbit Torque Non-Volatile Latch Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 615-618, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Mahabub Hasan Mahalat, Nikhil Ugale, Rohit Shahare, Bibhash Sen |
Design of Latch based Configurable Ring Oscillator PUF Targeting Secure FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, pp. 261-266, 2018, IEEE, 978-1-5386-4756-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Milova Paul, Boeila Sampath Kumar, Harald Gossner, Mayank Shrivastava |
Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 3, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Krzysztof Domanski |
Latch-up in FinFET technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 2, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Kyung-Il Do, Byung-Seok Lee, Hee-Guk Chae, Jeong-Ju Seo, Yong-Seo Koo |
A New Low Trigger SCR with Latch up Immunity for 5V Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EECS ![In: 2nd European Conference on Electrical Engineering and Computer Science, EECS 2018, Bern, Switzerland, December 20-22, 2018, pp. 524-527, 2018, IEEE, 978-1-7281-1929-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Zhengfeng Huang, Yangyang Zhang, Zian Su, Huaguo Liang, Huijie Yao, Tianming Ni |
A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018, pp. 121-126, 2018, IEEE, 978-1-5386-9466-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Kenneth Lamar, Ramin Izadpanah, Jim M. Brandt, Damian Dechev |
An Efficient Latch-free Database Index Based on Multi-dimensional Lists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: 37th IEEE International Performance Computing and Communications Conference, IPCCC 2018, Orlando, FL, USA, November 17-19, 2018, pp. 1-2, 2018, IEEE, 978-1-5386-6808-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
Displaying result #301 - #400 of 859 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ >>] |
|