Search results for "D-latch"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Aibin Yan, Zijie Zhai, Lele Wang 0011, Jixiang Zhang 0007, Ningning Cui, Tianming Ni, Xiaoqing Wen	Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing.	ITC-Asia	2021	DBLP DOI BibTeX RDF
16	Aibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen	A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments.	ACM Great Lakes Symposium on VLSI	2021	DBLP DOI BibTeX RDF
16	Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard 0001	Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits.	ACM Great Lakes Symposium on VLSI	2021	DBLP DOI BibTeX RDF
16	Peiyi Zhao, Zisong Wang, Congyi Zhu, Tom Springer, Jacob Anabi, Yinshui Xia, Lingli Wang	Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch.	ASICON	2021	DBLP DOI BibTeX RDF
16	Songyan Wang, Xiaomei Fan, Zhihua Zhu, Yingtao Zhang, Ruike Chen, Juin Jei Liou	A LVTSCR-Based Compact Structure for Latch-up Immune.	ASICON	2021	DBLP DOI BibTeX RDF
16	Sandeep Kumar, Atin Mukherjee 0001	A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design.	DFT	2021	DBLP DOI BibTeX RDF
16	Zhenxing Chang, Aijiao Cui, Ziming Wang, Gang Qu 0001	Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs.	ISQED	2021	DBLP DOI BibTeX RDF
16	Gaeryun Sung, Jaeduk Han	High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology.	ISOCC	2021	DBLP DOI BibTeX RDF
16	Jérôme Folla Kamdem, Wembe Tafo Evariste, Essimbi Zobo Bernard, Maria Liz Crespo, Andres Cicuttin	A Compact 20GHz Dynamic Latch Comparator in 65nm CMOS Process.	SSD	2021	DBLP DOI BibTeX RDF
16	Mahesh Kumawat, Abhishek Kumar Upadhyay, Sanjay Sharma, Ravi Kumar 0006, Gaurav Singh, Santosh Kumar Vishvakarma	An improved current mode logic latch for high-speed applications.	Int. J. Commun. Syst.	2020	DBLP DOI BibTeX RDF
16	Aibin Yan, Xiangfeng Feng, Yuanjie Hu, Chaoping Lai, Jie Cui 0004, Zhili Chen, Kohei Miyase, Xiaoqing Wen	Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments.	IEEE Trans. Aerosp. Electron. Syst.	2020	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhelong Xu, Kang Yang, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen	A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications.	IEEE Trans. Aerosp. Electron. Syst.	2020	DBLP DOI BibTeX RDF
16	Kuan-Chieh Chao, Jung-Chin Lai, Terng-Yin Hsu	All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier.	IEEE Access	2020	DBLP DOI BibTeX RDF
16	Qiang Li, Xiaohui Su, Jing Guo 0004, Chunhua Qi	Self-Recovery Tolerance Latch Design Based on the Radiation Mechanism.	IEEE Access	2020	DBLP DOI BibTeX RDF
16	Nan Zhang, Xiaohui Su, Jing Guo 0004	Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology.	IEEE Access	2020	DBLP DOI BibTeX RDF
16	Suraj Pattanaik	A novel approach to design a digital clock triggered modified pulse latch for 16-bit shift register.	Int. J. Intell. Def. Support Syst.	2020	DBLP DOI BibTeX RDF
16	Adam Watkins, Spyros Tragoudas	Radiation Hardened Latch Designs for Double and Triple Node Upsets.	IEEE Trans. Emerg. Top. Comput.	2020	DBLP DOI BibTeX RDF
16	Aibin Yan, Yuanjie Hu, Jie Cui 0004, Zhili Chen, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen	Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment.	IEEE Trans. Computers	2020	DBLP DOI BibTeX RDF
16	Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar 0006, Gaurav Singh, Santosh Kumar Vishvakarma	A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
16	Bing Li, Shuai Chen, Kai Wang	An improved PAAs countermeasure based on permutation tables and latch PUF.	Sci. China Inf. Sci.	2020	DBLP DOI BibTeX RDF
16	Sanjay Vidhyadharan, Surya Shankar Dan, Ramakant Yadav, Simhadri Hariprasad	An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
16	Yong Ma, Yongjian Yu, Jian Lu, Qiaoyun Zou, Huibin Zhang	Effect of manufacturing technics on the microstructure and temperature-affected electrical performance of D-type latch devices.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
16	Joseph Sweeney, Mohammed Zackriya V, Samuel Pagliarini, Lawrence T. Pileggi	Latch-Based Logic Locking.	CoRR	2020	DBLP BibTeX RDF
16	Yuta Yamamoto, Kazuteru Namba	Complete Double Node Upset Tolerant Latch Using C-Element.	IEICE Trans. Inf. Syst.	2020	DBLP DOI BibTeX RDF
16	Yibo Jiang, Hui Bi 0003, Wei Zhao, Chen Shi, Xiaolei Wang	Latch-Up Immune Bi-Direction ESD Protection Clamp for Push-Pull RF Power Amplifier.	IEICE Trans. Electron.	2020	DBLP DOI BibTeX RDF
16	Yan Li 0084, Xu Cheng 0002, Chiyu Tan, Jun Han 0003, Yuanfu Zhao, Liang Wang 0024, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng	A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
16	Aibin Yan, Yafei Ling, Jie Cui 0004, Zhili Chen, Zhengfeng Huang, Jie Song, Patrick Girard 0001, Xiaoqing Wen	Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
16	Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang	Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
16	Siddharth R. K., Y. Jaya Satyanarayana, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni	A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
16	Jing Guo 0004, Shanshan Liu 0001, Lei Zhu 0004, Fabrizio Lombardi	Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
16	Saki Tajima, Masao Yanagisawa, Youhua Shi	Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
16	Xinchao Shang, Minyi Lu, Chengjun Wu, Yiming Xiang, Jiaming Xu, Weiwei Shan	A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
16	Joonyeong Kim, Byung-Kil Han, Dongbum Pyo, Semin Ryu, Hanbyeol Kim, Dong-Soo Kwon	Braille Display for Portable Device Using Flip-Latch Structured Electromagnetic Actuator.	IEEE Trans. Haptics	2020	DBLP DOI BibTeX RDF
16	Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel	Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs.	DATE	2020	DBLP DOI BibTeX RDF
16	Zeeshan Ali, Makwana Harshit R, Shalabh Gupta	A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC).	ICECS	2020	DBLP DOI BibTeX RDF
16	Zhiyang Qu, Lubin Hang, Huiyu Deng, Xiaobo Huang, Mingyuan Wang 0002, Xiaojie Huang, Zhe Liu, Yong Chen, Yong Hua, Jinliang Du	Control System of Single-drive Double-branch Electric Vehicle Door Latch.	RICAI	2020	DBLP DOI BibTeX RDF
16	Borui Wu, Lubin Hang, Xiaojie Huang, Sulong Li, Xiaobo Huang, Mingyuan Wang 0002, Chuanlei Zhong, Zhiyang Qu	Double Loops Mechanism with Multi-Mode Motion Applied in The Vehicle Door Latch.	RICAI	2020	DBLP DOI BibTeX RDF
16	Chuanlei Zhong, Lubin Hang, Mingyuan Wang 0002, Sulong Li, Xiaobo Huang, Xiaojie Huang, Zhe Liu, Yong Chen	Research on A Spatial Compliant Mechanism for the Power Release Branch in Vehicle Side Door Latch.	RICAI	2020	DBLP DOI BibTeX RDF
16	Abdulhadi Shoufan	SR Latch: The Wrong Introduction to Digital Memory.	ISCAS	2020	DBLP DOI BibTeX RDF
16	Joseph Sweeney, V. Mohammed Zackriya, Samuel Pagliarini, Lawrence T. Pileggi	Latch-Based Logic Locking.	HOST	2020	DBLP DOI BibTeX RDF
16	Ziwei Li, Wenbin He, Fan Ye 0001, Junyan Ren	A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier.	APCCAS	2020	DBLP DOI BibTeX RDF
16	Aibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui 0004, Zuobin Ying, Patrick Girard 0001, Xiaoqing Wen	HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications.	DAC	2020	DBLP DOI BibTeX RDF
16	Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang	Latch Clustering for Timing-Power Co-Optimization.	DAC	2020	DBLP DOI BibTeX RDF
16	Hanwool Jeong, Juhyun Park, Seung Chul Song, Seong-Ook Jung	Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
16	Chaudhry Indra Kumar, Anand Bulusu	High performance energy efficient radiation hardened latch for low voltage applications.	Integr.	2019	DBLP DOI BibTeX RDF
16	Deok Gyoon Chung, Joonhwan Kim, Donghoon Baek, Joonyeong Kim, Dong-Soo Kwon	Shape-Locking Mechanism of Flexible Joint Using Mechanical Latch With Electromagnetic Force.	IEEE Robotics Autom. Lett.	2019	DBLP DOI BibTeX RDF
16	Huimei Cheng, Hsiao-Lun Wang, Minghe Zhang, Dylan Hand, Peter A. Beerel	Automatic Retiming of Two-Phase Latch-Based Resilient Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
16	Xixi Dai, Haibin Wang, Jiamin Chu, Zhi Liu 0004, Li Cai, Kang Yan	A Single Event Upset Resilient Latch Design with Single Node Upset Immunity.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
16	Chaudhry Indra Kumar, Arvind Kumar Sharma, Rajendra Partap, Anand Bulusu	An energy-efficient variation aware self-correcting latch.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
16	Cody Mitchell, Mitchell R. Hunt, Fat D. Ho	Retention characteristics of a nonvolatile latch utilizing a ferroelectric transistor.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
16	Jinwook Jung, Gi-Joon Nam, Woohyun Chung, Youngsoo Shin	Integrated Latch Placement and Cloning for Timing Optimization.	ACM Trans. Design Autom. Electr. Syst.	2019	DBLP DOI BibTeX RDF
16	Huimei Cheng, Yichen Gu, Peter A. Beerel	Automatic Conversion from Flip-flop to 3-phase Latch-based Designs.	CoRR	2019	DBLP BibTeX RDF
16	Mir Muntasir Hossain, Satyendra N. Biswas	Analysis and Design of a 32nm FinFET Dynamic Latch Comparator.	CoRR	2019	DBLP BibTeX RDF
16	Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya	Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
16	Dhruv Patel 0002, Adam Neale, Derek Wright, Manoj Sachdev	Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
16	Aibin Yan, Kang Yang, Zhengfeng Huang, Jiliang Zhang 0002, Jie Cui 0004, Xiangsheng Fang, Maoxiang Yi, Xiaoqing Wen	A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
16	Jianwei Jiang 0001, Yiran Xu, Wenyi Zhu, Jun Xiao, Shichang Zou	Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
16	Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao 0007, Xuan Li, Junning Chen, Xuan Zeng 0001, Xiangdong Hu	A single event upset tolerant latch with parallel nodes.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
16	Chun-Cheng Chen, Ming-Dou Ker	Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process.	IRPS	2019	DBLP DOI BibTeX RDF
16	Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva	Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.	IRPS	2019	DBLP DOI BibTeX RDF
16	Aibin Yan, Yuanjie Hu, Jie Song, Xiaoqing Wen	Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications.	DATE	2019	DBLP DOI BibTeX RDF
16	Daniel Townley, Khaled N. Khasawneh, Dmitry Ponomarev 0001, Nael B. Abu-Ghazaleh, Lei Yu 0001	LATCH: A Locality-Aware Taint CHecker.	MICRO	2019	DBLP DOI BibTeX RDF
16	Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu	STAHL: A Novel Scan-Test-Aware Hardened Latch Design.	ETS	2019	DBLP DOI BibTeX RDF
16	Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa	A light-weight implementation of latch-based true random number generator.	IWCMC	2019	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, Patrick Girard 0001, Xiaoqing Wen	Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications.	ATS	2019	DBLP DOI BibTeX RDF
16	Fabián Leonardo Cabrera, Fernando Rangel de Sousa, Héctor Pettenghi	Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behavior.	LASCAS	2019	DBLP DOI BibTeX RDF
16	Ambika Prasad Shah, Michael Waltl	Low Cost and High Performance Radiation Hardened Latch Design for Reliable Circuits.	ICECS	2019	DBLP DOI BibTeX RDF
16	Zhaochen Yin, Walter Audoglio, Marco Grassi, Piero Malcovati, Edoardo Bonizzoni	Performance Comparison of a Strong-Arm Latch in Different Ultra-Scaled Technologies.	ICECS	2019	DBLP DOI BibTeX RDF
16	Athanasios T. Ramkaj, Michiel S. J. Steyaert, Filip Tavernier	A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS.	ESSCIRC	2019	DBLP DOI BibTeX RDF
16	Emanuele Abbatessa, Davide Dente, Sergio Saponara	Integrated Simulation Environment for Co-design/Verification of Mechanic, Electronic and Control of Automotive E-Drives: The Smart-Latch Case Study.	ApplePies	2019	DBLP DOI BibTeX RDF
16	Sulong Li, Lubin Hang, Mingyuan Wang 0002, Lele Bai, Xiaobo Huang, Huiyu Deng, Zhe Liu, Yong Chen, Yong Hua, Jinliang Du	Research on Four-bar Linkage with Variable Axis Torsion Spring for Vehicle Latch Lock/Unlock.	RICAI	2019	DBLP DOI BibTeX RDF
16	Xu Su, Lubin Hang, Hui Guo, Mingyuan Wang 0002, Zhe Liu, Yong Chen, Yong Hua, Jinliang Du	Simulation Research of Gear Recovery Noise in Electric Opening Branch with the Vehicle Door Latch.	RICAI	2019	DBLP DOI BibTeX RDF
16	Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001, Vivek De, Sanu Mathew	A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
16	Troy Bryant, Taewook Kim, Nima Maghari	A Self-Reset Transconductance Integrating Leakage Latch (STILL) for Ultra-Low Power Sensor Interfacing.	ISCAS	2019	DBLP DOI BibTeX RDF
16	Zhiyuan Song, Aibin Yan, Jie Cui 0004, Zhili Chen, Xuejun Li, Xiaoqing Wen, Chaoping Lai, Zhengfeng Huang, Huaguo Liang	A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells.	ITC-Asia	2019	DBLP DOI BibTeX RDF
16	Pingshun Ma, Yongzhen Chen, Jiangfeng Wu	A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS.	ASICON	2019	DBLP DOI BibTeX RDF
16	Muneeb Sulthan, Shubhajit Roy Chowdury, Rajnish Garg, Alok Tripathi	Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop.	VDAT	2019	DBLP DOI BibTeX RDF
16	Wei Wang 0177, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins	A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
16	Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta	A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
16	Amir Ardakani, Shahriar B. Shokouhi, Arash Reyhani-Masoleh	Improving performance of FPGA-based SR-latch PUF using Transient Effect Ring Oscillator and programmable delay lines.	Integr.	2018	DBLP DOI BibTeX RDF
16	Mitesh Limachia, Dixit Vyas, Rajesh Amratlal Thakker, Nikhil Kothari	Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology.	Integr.	2018	DBLP DOI BibTeX RDF
16	Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi	A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
16	Leïla Khanfir, Jaouhar Mouine	Design optimisation procedure for digital mismatch compensation in latch comparators.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
16	Ramin Razmdideh, Mohsen Saneei	Low-power, latch-based multistage time-to-digital converter in 65 nm CMOS technology.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
16	Aravinda Koithyar, T. K. Ramesh 0001	A faster phase frequency detector using transmission gate-based latch for the reduced response time of the PLL.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
16	Nima Shahpari, Mehdi Habibi	A rail-to-rail low-power latch comparator with time domain bulk-tuned offset cancellation for low-voltage applications.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
16	Vijay Savani, N. M. Devashrayee	Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
16	Joy Arulraj, Justin J. Levandoski, Umar Farooq Minhas, Per-Åke Larson	BzTree: A High-Performance Latch-free Range Index for Non-Volatile Memory. (PDF / PS)	Proc. VLDB Endow.	2018	DBLP DOI BibTeX RDF
16	Haibin Wang, Xixi Dai, Yangsheng Wang, Issam Nofal, Li Cai, Zicai Shen, Wanxiu Sun, Jinshun Bi, Bo Li 0051, Gang Guo, Li Chen 0001, Sang H. Baeg	A single event upset tolerant latch design.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
16	Oh-Yong Jung, Hyun-Gi Seok, Anjana Dissanayake, Sang-Gug Lee 0001	A 45-µW, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
16	Dianpeng Lin, Yiran Xu, Xiaoyun Li, Xin Xie, Jianwei Jiang 0001, Jiangchuan Ren, Huilong Zhu, Zhengxuan Zhang, Shichang Zou	A novel self-recoverable and triple nodes upset resilience DICE latch.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
16	Yuanqing Li, Anselm Breitenreiter, Marko S. Andjelkovic, Oliver Schrape, Milos Krstic	Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle.	DDECS	2018	DBLP DOI BibTeX RDF
16	Mohammed Al-Qadasi, Abdullah Alshehri 0003, Abdullah S. Almansouri, Talal Al-Attar, Hossein Fariborzi	A High Speed Dynamic StrongARM Latch Comparator.	MWSCAS	2018	DBLP DOI BibTeX RDF
16	Karim Ali 0004, Fei Li 0015, Sunny Y. H. Lua, Chun-Huat Heng	Area and Energy Efficient Diode Based Spin Orbit Torque Non-Volatile Latch Design.	MWSCAS	2018	DBLP DOI BibTeX RDF
16	Mahabub Hasan Mahalat, Nikhil Ugale, Rohit Shahare, Bibhash Sen	Design of Latch based Configurable Ring Oscillator PUF Targeting Secure FPGA.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
16	Milova Paul, Boeila Sampath Kumar, Harald Gossner, Mayank Shrivastava	Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability.	IRPS	2018	DBLP DOI BibTeX RDF
16	Krzysztof Domanski	Latch-up in FinFET technologies.	IRPS	2018	DBLP DOI BibTeX RDF
16	Kyung-Il Do, Byung-Seok Lee, Hee-Guk Chae, Jeong-Ju Seo, Yong-Seo Koo	A New Low Trigger SCR with Latch up Immunity for 5V Application.	EECS	2018	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Yangyang Zhang, Zian Su, Huaguo Liang, Huijie Yao, Tianming Ni	A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE.	ATS	2018	DBLP DOI BibTeX RDF
16	Kenneth Lamar, Ramin Izadpanah, Jim M. Brandt, Damian Dechev	An Efficient Latch-free Database Index Based on Multi-dimensional Lists.	IPCCC	2018	DBLP DOI BibTeX RDF