Search results for "DDECS"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman 0001, Debesh K. Das	Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits.	DDECS	2015	DBLP DOI BibTeX RDF
1	Dusan N. Grujic, Mihajlo Bozovic, Milan Savic	BSIM4 to PSP Model Conversion for Passive Mixer IM3 Simulation.	DDECS	2015	DBLP DOI BibTeX RDF
1	Tobias Koal, Stefan Scharoba, Heinrich Theodor Vierhaus	Combining Correction of Delay Faults and Transient Faults.	DDECS	2015	DBLP DOI BibTeX RDF
1	I-Che Chen, John P. Hayes	Low-Area and High-Speed Approximate Matrix-Vector Multiplier.	DDECS	2015	DBLP DOI BibTeX RDF
1	Peter Malík	High Throughput Floating-Point Dividers Implemented in FPGA.	DDECS	2015	DBLP DOI BibTeX RDF
1	Ondrej Novák, Jiri Jenícek, Martin Rozkovec	LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs.	DDECS	2015	DBLP DOI BibTeX RDF
1	Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou	PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing.	DDECS	2015	DBLP DOI BibTeX RDF
1	Milan Babic, Milos Krstic	A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates.	DDECS	2015	DBLP DOI BibTeX RDF
1	Hong-Yi Huang, Gene Fe P. Palencia, Da-Kai Chen, Wei-Hsuan Huang	Triangular Modulation Using Switched-Capacitor Scheme for Spread-Spectrum Clocking.	DDECS	2015	DBLP DOI BibTeX RDF
1	Dominik Macko, Katarína Jelemenská, Pavel Cicák	Power-Management Specification in SystemC.	DDECS	2015	DBLP DOI BibTeX RDF
1	Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar	New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams.	DDECS	2015	DBLP DOI BibTeX RDF
1	Martin Krcma, Jan Kastil, Zdenek Kotásek	Mapping Trained Neural Networks to FPNNs.	DDECS	2015	DBLP DOI BibTeX RDF
1	Nebojsa Pjevalica, Milos Nikolic 0004, Ivan Kastelan	Analog Circuitry for BLDC Motor Magnetic Saturation Diagnostic.	DDECS	2015	DBLP DOI BibTeX RDF
1	Thomas Hollstein, Siavoosh Payandeh Azad, Thilo Kogge, Haoyuan Ying, Klaus Hofmann	NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip.	DDECS	2015	DBLP DOI BibTeX RDF
1	Lukás Nagy, Viera Stopjaková, Alexander Satka	Design of In AlN/GaN Heterostructure-Based Logic Cells.	DDECS	2015	DBLP DOI BibTeX RDF
1	Andrzej Grodzicki, Witold A. Pleskacz	A Low Ripple Current Mode Voltage Doubler.	DDECS	2015	DBLP DOI BibTeX RDF
1	Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek	FPGA Prototyping and Accelerated Verification of ASIPs.	DDECS	2015	DBLP DOI BibTeX RDF
1	Ioana Mot, Oana Boncalo, Alexandru Amaricai	Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques.	DDECS	2015	DBLP DOI BibTeX RDF
1	Hans G. Kerkhoff, Hassan Ebrahimi	Intermittent Resistive Faults in Digital CMOS Circuits.	DDECS	2015	DBLP DOI BibTeX RDF
1	Shuichi Sato, Satoshi Ohtake	A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model.	DDECS	2015	DBLP DOI BibTeX RDF
1	Vasileios Gerakis, Fontounasios Christos, Alkis A. Hatzopoulos	Modeling the Coupling through Substrate for Frequencies up to 100GHz.	DDECS	2015	DBLP DOI BibTeX RDF
1	Stefan Kristofík, Marcel Baláz, Mária Fischerová	Generic Self Repair Architecture with On-Line Fault Diagnosis.	DDECS	2015	DBLP DOI BibTeX RDF
1	Mikhail Glukhikh, Mikhail J. Moiseev	Fast Simulation of SystemC Synthesizable Subset.	DDECS	2015	DBLP DOI BibTeX RDF
1	Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus (eds.)	18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015	DDECS	2015	DBLP BibTeX RDF
1	Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang	A Synchronous Mirror Delay with Duty-Cycle Tunable Technology.	DDECS	2015	DBLP DOI BibTeX RDF
1	Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors.	DDECS	2015	DBLP DOI BibTeX RDF
1	Sneana Stefanovski, Milka M. Potrebic, Dejan Toic, Zoran Stamenkovic	A Novel Compact Dual-Band Bandpass Waveguide Filter.	DDECS	2015	DBLP DOI BibTeX RDF
1	Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler	Requirement Phrasing Assistance Using Automatic Quality Assessment.	DDECS	2015	DBLP DOI BibTeX RDF
1	Miroslav Siebert, Elena Gramatová	Parameterized Critical Path Selection for Delay Fault Testing.	DDECS	2015	DBLP DOI BibTeX RDF
1	Lukasz Lopacinski, Jörg Nolte, Steffen Büchner 0002, Marcin Brzozowski, Rolf Kraemer	Design and Implementation of an Adaptive Algorithm for Hybrid Automatic Repeat Request.	DDECS	2015	DBLP DOI BibTeX RDF
1	Nikolay N. Prokopenko, Nikolay V. Butyrlagin, Sergei G. Krutchinsky, Evgeniy A. Zhebrun, Alexey E. Titov	Microwave Selective Amplifiers with High Asymptotic Attenuation in the Range of Subresonance Frequencies.	DDECS	2015	DBLP DOI BibTeX RDF
1	Niels Thole, Heinz Riener, Görschwin Fey	Equivalence Checking on System Level Using a Priori Knowledge.	DDECS	2015	DBLP DOI BibTeX RDF
1	Vladimir Petrovic, Milos Krstic	Design Flow for Radhard TMR Flip-Flops.	DDECS	2015	DBLP DOI BibTeX RDF
1	Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko	Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit.	DDECS	2015	DBLP DOI BibTeX RDF
1	Nils Przigoda, Robert Wille, Rolf Drechsler	Contradiction Analysis for Inconsistent Formal Models.	DDECS	2015	DBLP DOI BibTeX RDF
1	Rados Dabic, Sasa Jednak, Ilija Adzic, Dusko Stanic, Aleksandar Mijatovic, Stanislav Vuckovic	Direct Test Methodology for HDL Verification.	DDECS	2015	DBLP DOI BibTeX RDF
1	Muhammed Ceylan Morgül, Mustafa Altun	Synthesis and Optimization of Switching Nanoarrays.	DDECS	2015	DBLP DOI BibTeX RDF
1	Daniel Arbet, Gabriel Nagy, Martin Kovác, Viera Stopjaková	Fully Differential Difference Amplifier for Low-Noise Applications.	DDECS	2015	DBLP DOI BibTeX RDF
1	Tetsuya Matsumura, Aoi Kurokawa, Kousuke Imamura, Yoshio Matsuda	A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm.	DDECS	2015	DBLP DOI BibTeX RDF
1	Goran Panic, Zoran Stamenkovic	Activity Profiling and Power Estimation for Embedded Wireless Sensor Node Design.	DDECS	2015	DBLP DOI BibTeX RDF
1	Krzysztof Marcinek, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz	Implementation of the ADELITE Microcontroller for Biomedical Applications.	DDECS	2015	DBLP DOI BibTeX RDF
1	Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier	TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms.	DDECS	2015	DBLP DOI BibTeX RDF
1	Maciej Moskala, Patryk Kloczko, Marek Cieplucha, Witold A. Pleskacz	UVM-based Verification of Bluetooth Low Energy Controller.	DDECS	2015	DBLP DOI BibTeX RDF
1	Syed Saif Abrar, Maksim Jenihhin, Jaan Raik	SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores.	DDECS	2015	DBLP DOI BibTeX RDF
1	Spyridon Nikolaidis 0001	Modeling CMOS Gates Using Equivalent Inverters.	DDECS	2015	DBLP DOI BibTeX RDF
1	Woo-Rham Bae, Deog-Kyoon Jeong, Byoung-Joo Yoo	A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology.	DDECS	2014	DBLP DOI BibTeX RDF
1	Viktor Pus, Lukas Kekely, Jan Korenek	Design methodology of configurable high performance packet parser for FPGA.	DDECS	2014	DBLP DOI BibTeX RDF
1	Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda	The LSI implementation of a memory based field programmable device for MCU peripherals.	DDECS	2014	DBLP DOI BibTeX RDF
1	Grzegorz Pastuszak	FPGA architectures of the quantization and the dequantization for video encoders.	DDECS	2014	DBLP DOI BibTeX RDF
1	Omar Abdelmalek, David Hély, Vincent Beroulle	Emulation based fault injection on UHF RFID transponder.	DDECS	2014	DBLP DOI BibTeX RDF
1	Jing Ning, Klaus Hofmann	A 120V high voltage DAC array for a tunable antenna in communication system.	DDECS	2014	DBLP DOI BibTeX RDF
1	Salma Hesham, Mohamed A. Abd El Ghany, Klaus Hofmann	High throughput architecture for the Advanced Encryption Standard Algorithm.	DDECS	2014	DBLP DOI BibTeX RDF
1	Raimund Ubar, Dmitri Mironov	Lower bounds of the size of Shared Structurally Synthesized BDDs.	DDECS	2014	DBLP DOI BibTeX RDF
1	Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard 0001, P. Debaud, S. Guilhot	Test and diagnosis of power switches.	DDECS	2014	DBLP DOI BibTeX RDF
1	Panagiotis Chaourani, Spyridon Nikolaidis 0001	A unified CMOS inverter model for planar and FinFET nanoscale technologies.	DDECS	2014	DBLP DOI BibTeX RDF
1	Piotr Maj	Mismatch effects and their correction in large area ASICs.	DDECS	2014	DBLP DOI BibTeX RDF
1	Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi	An intra-cell defect grading tool.	DDECS	2014	DBLP DOI BibTeX RDF
1	Hafiz ul Asad, Kevin D. Jones, Frédéric Surre	Verifying robust frequency domain properties of non linear oscillators using SMT.	DDECS	2014	DBLP DOI BibTeX RDF
1	Dominik Macko, Katarína Jelemenská	Self-managing power management unit.	DDECS	2014	DBLP DOI BibTeX RDF
1	Albert Au, Artur Pogiel, Janusz Rajski, Piotr Sydow, Jerzy Tyszer, Justyna Zawada	Quality assurance in memory built-in self-test tools.	DDECS	2014	DBLP DOI BibTeX RDF
1	Milan Dvorak, Jan Korenek	Low latency book handling in FPGA for high frequency trading.	DDECS	2014	DBLP DOI BibTeX RDF
1	Stefano Pettazzi, Andrew Plews, Anatoly Rudenko, Ahmed Nejim	Development of 3D space partitioning and design rule check for smart system solutions.	DDECS	2014	DBLP DOI BibTeX RDF
1	Petr Fiser, Jan Schmidt, Jiri Balcarek	Sources of bias in EDA tools and its influence.	DDECS	2014	DBLP DOI BibTeX RDF
1	Andrzej Abramowski, Grzegorz Pastuszak	A double-path intra prediction architecture for the hardware H.265/HEVC encoder.	DDECS	2014	DBLP DOI BibTeX RDF
1	Andrzej Wielgus	Heuristic algorithm of two-level minimization of fuzzy logic functions.	DDECS	2014	DBLP DOI BibTeX RDF
1	Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel	Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce.	DDECS	2014	DBLP DOI BibTeX RDF
1	Lukas Miculka, Zdenek Kotásek	Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA.	DDECS	2014	DBLP DOI BibTeX RDF
1	A. Mehdaoui, J. Pagazani, G. Schropfer, Gaëlle Lissorgues	SiP design flow and 3D DRC for MEMS.	DDECS	2014	DBLP DOI BibTeX RDF
1	Pawel Dabal, Ryszard Pelka	A study on fast pipelined pseudo-random number generator based on chaotic logistic map.	DDECS	2014	DBLP DOI BibTeX RDF
1	Juraj Brenkus, Viera Stopjaková, Daniel Arbet, Gábor Gyepes, Libor Majer	A novel impedance calculation method and its time efficiency evaluation.	DDECS	2014	DBLP DOI BibTeX RDF
1	Jürgen Maier 0002, Andreas Steininger	Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic.	DDECS	2014	DBLP DOI BibTeX RDF
1	Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada	Burst-pulse Generator based on transmission line toward sub-MMW.	DDECS	2014	DBLP DOI BibTeX RDF
1	Nam-Khanh Dang, Xuan-Tu Tran, Alain Merirot	An efficient hardware architecture for inter-prediction in H.264/AVC encoders.	DDECS	2014	DBLP DOI BibTeX RDF
1	Domenico Bertoncelli, Pasquale Caianiello	Customer return detection with features selection.	DDECS	2014	DBLP DOI BibTeX RDF
1	Tomasz Garbolino	Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections.	DDECS	2014	DBLP DOI BibTeX RDF
1	Steffen Ostendorff, Jorge H. Meza Escobar, Heinz-Dietrich Wuttke, Thomas Sasse, Sebastian Richter	Modeling timing constraints for automatic generation of embedded test instruments.	DDECS	2014	DBLP DOI BibTeX RDF
1	Andrzej Grodzicki, Witold A. Pleskacz	Multistage low ripple charge pump.	DDECS	2014	DBLP DOI BibTeX RDF
1	Marco Gaudesi, S. Saleem, Ernesto Sánchez 0001, Matteo Sonza Reorda, E. Tanowe	On the in-field test of Branch Prediction Units using the correlated predictor mechanism.	DDECS	2014	DBLP DOI BibTeX RDF
1	Tomás Závodník, Lukas Kekely, Viktor Pus	CRC based hashing in FPGA using DSP blocks.	DDECS	2014	DBLP DOI BibTeX RDF
1	Martin Krammer, Michael Karner, Anton Fuchs	System design for enhanced forward-engineering possibilities of safety critical embedded systems.	DDECS	2014	DBLP DOI BibTeX RDF
1	Panagiotis Sismanoglou, Dimitris Nikolos	Test data compression based on reuse and bit-flipping of parts of dictionary entries.	DDECS	2014	DBLP DOI BibTeX RDF
1	Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang	A low supply voltage synchronous mirror delay with quadrature phase output.	DDECS	2014	DBLP DOI BibTeX RDF
1	Vlastimil Kosar, Jan Korenek	On NFA-split architecture optimizations.	DDECS	2014	DBLP DOI BibTeX RDF
1		17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014	DDECS	2014	DBLP BibTeX RDF
1	Ronaldo Rodrigues Ferreira, Thomas Klotz, Thilo Vörtler, Jean da Rolt, Gabriel L. Nazar, Álvaro Freitas Moreira, Luigi Carro, Karsten Einwich	Reliable execution of statechart-generated correct embedded software under soft errors.	DDECS	2014	DBLP DOI BibTeX RDF
1	Pavel Fiala, Richard Linhart	Efficient VHDL implementation of symbol synchronization for software radio based on FPGA.	DDECS	2014	DBLP DOI BibTeX RDF
1	Mikolaj Roszkowski, Grzegorz Pastuszak	FPGA design of the computation unit for the semi-global stereo matching algorithm.	DDECS	2014	DBLP DOI BibTeX RDF
1	Lufei Shen, Ferdinand Keil, Klaus Hofmann	Stabilization methods for integrated high voltage charge pumps.	DDECS	2014	DBLP DOI BibTeX RDF
1	Andrej Kincel, Marcel Baláz	Case study: BISR for a processor multiplier.	DDECS	2014	DBLP DOI BibTeX RDF
1	Tariq Bashir Ahmad, Maciej J. Ciesielski	Fast time-parallel C-based event-driven RTL simulation.	DDECS	2014	DBLP DOI BibTeX RDF
1	Harish Balasubramaniam, Klaus Hofmann	Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators.	DDECS	2014	DBLP DOI BibTeX RDF
1	Marcel Baláz, Stefan Kristofík, Mária Fischerová	Generic built-in self-repair architectures for SoC logic cores.	DDECS	2014	DBLP DOI BibTeX RDF
1	Peter Malík	Dedicated hardware architecture for object tracking preprocessing implemented in FPGA.	DDECS	2014	DBLP DOI BibTeX RDF
1	Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta 0001, Hafizur Rahaman 0001, Rolf Drechsler	Optimizing DD-based synthesis of reversible circuits using negative control lines.	DDECS	2014	DBLP DOI BibTeX RDF
1	Vasileios Gerakis, Christina Avdikou, Alexandros Liolios, Alkis A. Hatzopoulos	Modeling and analysis of cracked through silicon via (TSV) interconnections.	DDECS	2014	DBLP DOI BibTeX RDF
1	Jan Malburg, Niklas Krafczyk, Görschwin Fey	Automatically connecting hardware blocks via light-weight matching techniques.	DDECS	2014	DBLP DOI BibTeX RDF
1	Lukas Kekely, Martin Zádník, Jirí Matousek 0002, Jan Korenek	Fast lookup for dynamic packet filtering in FPGA.	DDECS	2014	DBLP DOI BibTeX RDF
1	Pranab Roy, Hafizur Rahaman 0001, Parthasarathi Dasgupta	A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips.	DDECS	2014	DBLP DOI BibTeX RDF
1	Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada	Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits.	DDECS	2014	DBLP DOI BibTeX RDF
1	Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Online testing of many-core systems in the Dark Silicon era.	DDECS	2014	DBLP DOI BibTeX RDF

Publications at "DDECS"( http://dblp.L3S.de/Venues/DDECS )