Search results for "DMA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Stein Kristiansen, Morten Lindeberg, Daniel Rodríguez-Fernández, Thomas Plagemann	On the forwarding capability of mobile handhelds for video streaming over MANETs.	MobiHeld	2010	DBLP DOI BibTeX RDF	performance evaluation, MANETs, video streaming, handhelds
12	Qasim Ali 0001, Samuel P. Midkiff, Vijay S. Pai	Modeling advanced collective communication algorithms on cell-based systems.	PPoPP	2010	DBLP DOI BibTeX RDF	modeling, algorithms, collective communication
12	Romulo Goncalves, Martin L. Kersten	The Data Cyclotron query processing scheme.	EDBT	2010	DBLP DOI BibTeX RDF
12	Derek Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, Josep Torrellas	Two hardware-based approaches for deterministic multiprocessor replay.	Commun. ACM	2009	DBLP DOI BibTeX RDF
12	Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu	32-bit floating-point FPGA gaussian elimination.	FPGA	2009	DBLP DOI BibTeX RDF	fpga., floating-point, gaussian elimination
12	Nalini Vasudevan, Stephen A. Edwards	Celling SHIM: compiling deterministic concurrency to a heterogeneous multicore.	SAC	2009	DBLP DOI BibTeX RDF	SHIM, parallelism, compiler, concurrency, cell processor
12	Akiyoshi Wakatani	Implementation of Recurrence Calculation on a Heterogeneous Multicore Processor.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
12	Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang 0006, Cristiano Pereira	Offline symbolic analysis for multi-processor execution replay.	MICRO	2009	DBLP DOI BibTeX RDF	multi-processor replay, shared-memory dependencies, SMT solver
12	Yasuharu Katsuno, Yuji Watanabe, Michiharu Kudo, Eiji Okamoto	A Pluggable Domain Management Approach for Building Practical Distributed Coalitions.	ARES	2009	DBLP DOI BibTeX RDF
12	Xu Guo 0001, Patrick Schaumont	Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform.	ARC	2009	DBLP DOI BibTeX RDF
12	Maciej Wielgosz, Ernest Jamro, Kazimierz Wiatr	Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function.	ARC	2009	DBLP DOI BibTeX RDF	HPRC (High Performance Reconfigurable Computing), exponent function, FPGA
12	Joseph Hassoun	Resiliency in Elemental Computing.	ARC	2009	DBLP DOI BibTeX RDF
12	Vipin Sachdeva, Douglas M. Freimuth, Chris Mueller	Evaluating the Jaccard-Tanimoto Index on Multi-core Architectures.	ICCS (1)	2009	DBLP DOI BibTeX RDF
12	James R. Green, Hanan Mahmoud, Michel Dumontier	Modeling tryptic digestion on the Cell BE processor.	CCECE	2009	DBLP DOI BibTeX RDF
12	Lee W. Howes, Anton Lokhmotov, Alastair F. Donaldson, Paul H. J. Kelly	Deriving Efficient Data Movement from Decoupled Access/Execute Specifications.	HiPEAC	2009	DBLP DOI BibTeX RDF
12	Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva, José Marinho	Parallel LDPC Decoding on the Cell/B.E. Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
12	Jianhui Yue, Yifeng Zhu, Zhao Cai	An Energy-Oriented Evaluation of Buffer Cache Algorithms Using Parallel I/O Workloads.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
12	Tomás Martínek, Martin Kosek	NetCOPE: Platform for Rapid Development of Network Applications.	DDECS	2008	DBLP DOI BibTeX RDF
12	Jaejin Lee, Sangmin Seo, Chihun Kim, Junghyun Kim, Posung Chun, Zehra Sura, Jungwon Kim, Sangyong Han	COMIC: a coherent shared memory interface for cell be.	PACT	2008	DBLP DOI BibTeX RDF	heterogeneous multicores, software shared virtual memory, OpenMP, software distributed shared memory, Cell BE
12	José L. Abellán, Juan Fernández 0001, Manuel E. Acacio	CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE.	PDP	2008	DBLP DOI BibTeX RDF
12	Patrice Gerin, Xavier Guerin, Frédéric Pétrot	Efficient Implementation of Native Software Simulation for MPSoC.	DATE	2008	DBLP DOI BibTeX RDF
12	Enzo Baccarelli, Mauro Biagi, Cristian Pelizzoni, Nicola Cordeschi	Generalized Access for MIMO Cognitive Radios.	ICC	2008	DBLP DOI BibTeX RDF
12	Tamas Malek, Tomás Martínek, Jan Korenek	GICS: Generic interconnection system.	FPL	2008	DBLP DOI BibTeX RDF
12	Alastair F. Donaldson, Paul Keir, Anton Lokhmotov	Compile-Time and Run-Time Issues in an Auto-Parallelisation System for the Cell BE Processor.	Euro-Par Workshops	2008	DBLP DOI BibTeX RDF
12	Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Petrini	High-speed string searching against large dictionaries on the Cell/B.E. Processor.	IPDPS	2008	DBLP DOI BibTeX RDF
12	David A. Bader, Sulabh Patel	High performance MPEG-2 software decoder on the cell broadband engine.	IPDPS	2008	DBLP DOI BibTeX RDF
12	Meilian Xu, Parimala Thulasiraman	Finite-difference time-domain on the cell/B.E. processor.	IPDPS	2008	DBLP DOI BibTeX RDF
12	Sameer Kumar 0001, Gábor Dózsa, Gheorghe Almási 0001, Philip Heidelberger, Dong Chen 0005, Mark Giampapa, Michael Blocksome, Ahmad Faraj, Jeff Parker, Joe Ratterman, Brian E. Smith, Charles Archer	The deep computing messaging framework: generalized scalable message passing on the blue gene/P supercomputer.	ICS	2008	DBLP DOI BibTeX RDF	application programmer interface, parallel computing, MPI, message passing, collective communication, sockets, active messages, blue gene
12	Khaled Z. Ibrahim, François Bodin	Implementing Wilson-Dirac operator on the cell broadband engine.	ICS	2008	DBLP DOI BibTeX RDF	SIMD computer architecture, lattice qcd calculations, multi-core, MPSoC, cell broadband engine, data-parallel computing
12	Tong Chen, Haibo Lin, Tao Zhang	Orchestrating data transfer for the cell/B.E. processor.	ICS	2008	DBLP DOI BibTeX RDF	software controlled cache, multi-core system, memory coherence
12	José L. Abellán, Juan Fernández 0001, Manuel E. Acacio	Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades.	ICCS (1)	2008	DBLP DOI BibTeX RDF
12	Valentina Salapura	Scaling up next generation supercomputers.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	scalability of systems, chip multiprocessors (cmp), multicore, coherence protocols, blue gene
12	Heiner Litz, Holger Fröning, Mondrian Nüssle, Ulrich Brüning 0001	VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers.	ICPP	2008	DBLP DOI BibTeX RDF
12	Yinglong Xia, Viktor K. Prasanna	Parallel exact inference on the cell broadband engine processor.	SC	2008	DBLP DOI BibTeX RDF
12	Jonathan M. McCune, Bryan Parno, Adrian Perrig, Michael K. Reiter, Hiroshi Isozaki	Flicker: an execution infrastructure for tcb minimization.	EuroSys	2008	DBLP DOI BibTeX RDF	late launch, secure execution, trusted computing
12	Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang 0003	Memory System Design for a Multi-core Processor.	CISIS	2008	DBLP DOI BibTeX RDF
12	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
12	Ke Ning, David R. Kaeli	Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF	embedded systems, power-aware, external memory, media processor, bus arbitration
12	Li Zhao 0002, Laxmi N. Bhuyan, Ravi R. Iyer 0001, Srihari Makineni, Donald Newell	Hardware Support for Accelerating Data Movement in Server Platform.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Copy engine, performance evaluation, TCP/IP, hardware acceleration, servers
12	Théodore Marescaux, Erik Brockmeyer, Henk Corporaal	The Impact of Higher Communication Layers on NoC Supported MP-SoCs.	NOCS	2007	DBLP DOI BibTeX RDF
12	Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, Nikolaos S. Voros	Data Structure Exploration of Dynamic Applications.	PACT	2007	DBLP DOI BibTeX RDF
12	Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis G. Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis	Prototyping Efficient Interprocessor Communication Mechanisms.	ICSAMOS	2007	DBLP DOI BibTeX RDF
12	Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumit Ahuja, Sandeep K. Shukla	VT Matrix Multiply Design for MEMOCODE '07.	MEMOCODE	2007	DBLP DOI BibTeX RDF
12	Mitsunori Kubo, Fumio Terauchi, Hiroyuki Aoki	Two Vibration Modes of a Human Body Sitting on a Car Seat- The Relationship Between Riding Discomfort Affected by the Material Properties of the Seat Cushion and the Two Vibration Modes.	HCI (12)	2007	DBLP DOI BibTeX RDF	Riding Discomfort, Vibration Mode, Human Model
12	M. K. Velamati, Arun Kumar 0004, Naresh Jayam, Ganapathy Senthilkumar, Pallav K. Baruah, Raghunath Sharma, Shakti Kapoor, Ashok Srinivasan	Optimization of Collective Communication in Intra-cell MPI.	HiPC	2007	DBLP DOI BibTeX RDF	heterogeneous multicore processor, MPI, Cell Processor
12	Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita	Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier".	ASP-DAC	2007	DBLP DOI BibTeX RDF
12	Weitang Song, Xiaojun Qiao	A Regression Model of Dry Matter Accumulation for Solar Greenhouse Cucumber.	CCTA	2007	DBLP DOI BibTeX RDF	cucumber, dry matter accumulation, effective temperature accumulation, effective light intensity accumulation, regression model
12	Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt	Improving External Memory Access for Avalon Systems on Programmable Chips..	FPL	2007	DBLP DOI BibTeX RDF
12	Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell	Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine.	FPL	2007	DBLP DOI BibTeX RDF
12	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events.	ISPASS	2007	DBLP DOI BibTeX RDF	power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
12	David A. Bader, Virat Agarwal, Kamesh Madduri	On the Design and Analysis of Irregular Algorithms on the Cell Processor: A Case Study of List Ranking.	IPDPS	2007	DBLP DOI BibTeX RDF
12	Christopher Claus, Florian Helmut Müller, Johannes Zeppenfeld, Walter Stechele	A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration.	IPDPS	2007	DBLP DOI BibTeX RDF
12	Dong Wang, Xiaowen Chen, Shuming Chen, Xing Fang, Shuwei Sun	FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
12	Fong Pong, Nian-Feng Tzeng, Koray Öner, Chun Ning, Kwong-Tak Chui, Manoj Ekbote, Yanping Lu	Communication performance of a modular high-bandwidth multiprocessor system.	ICPADS	2007	DBLP DOI BibTeX RDF
12	Kevin K. O'Brien	Techniques for code and data management in the local stores of the cell processor.	CASES	2007	DBLP DOI BibTeX RDF	invited talk
12	Murali Krishna, Arun Kumar 0004, Naresh Jayam, Ganapathy Senthilkumar, Pallav K. Baruah, Raghunath Sharma, Shakti Kapoor, Ashok Srinivasan	A Synchronous Mode MPI Implementation on the Cell BETM Architecture.	ISPA	2007	DBLP DOI BibTeX RDF
12	Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, Taj Muhammad Khan	Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor.	ISPA	2007	DBLP DOI BibTeX RDF
12	Nikhil Bansal 0003, Kanishka Lahiri, Anand Raghunathan	Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Karthikeyan Vaidyanathan, Lei Chai, Wei Huang 0003, Dhabaleswar K. Panda 0001	Efficient asynchronous memory copy operations on multi-core systems and I/OAT.	CLUSTER	2007	DBLP DOI BibTeX RDF
12	Michael Kistler, Michael Perrone, Fabrizio Petrini	Cell Multiprocessor Communication Network: Built for Speed.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Cell Broadband Engine processor, multiprocessor communication network
12	Guilin Qi, Weiru Liu, David A. Bell	A revision-based approach to handling inconsistency in description logics.	Artif. Intell. Rev.	2006	DBLP DOI BibTeX RDF	Semantic web, Knowledge representation, Description logics, Stratification, Inconsistency handling
12	Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf	Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications.	ICSAMOS	2006	DBLP DOI BibTeX RDF
12	Qing K. Zhu, Paige Kolze	Metal Fix and Power Network Repair for SOC.	ISVLSI	2006	DBLP DOI BibTeX RDF
12	Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga	Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise.	ASP-DAC	2006	DBLP DOI BibTeX RDF
12	Sirish A. Kondi, Yoginder S. Dandass	Scanning workstation memory for malicious codes using dedicated coprocessors.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	FPGA, intrusion detection, coprocessor, signature matching
12	Yee-Lin Lai, Kai Lung Hui	Internet opt-in and opt-out: investigating the roles of frames, defaults and privacy concerns.	CPR	2006	DBLP DOI BibTeX RDF	opt-in, opt-out, privacy concern, frames, information privacy, defaults
12	Vanderlei Bonato, José A. M. de Holanda, Eduardo Marques	An Embedded Multi-camera System for Simultaneous Localization and Mapping.	ARC	2006	DBLP DOI BibTeX RDF
12	Liu Feng, Guo Rui, Shi Shu, Cheng Xu	HW/SW Co-Design and Implementation of Multi-Standard Video Decoding.	ESTIMedia	2006	DBLP DOI BibTeX RDF
12	Peng Xue, Surendar Chandra	Revisiting multimedia streaming in mobile ad hoc networks.	NOSSDAV	2006	DBLP DOI BibTeX RDF	MANET, resource management, multimedia streaming
12	Yuan Zhao, Ken Kennedy	Dependence-Based Code Generation for a CELL Processor.	LCPC	2006	DBLP DOI BibTeX RDF
12	Songping Mai, Kun Yang, Wenli Lan, Chun Zhang, Zhihua Wang 0001	An open-source based DSP with enhanced multimedia-processing capacity for embedded applications.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Hai Jin 0001, Minghu Zhang, Pengliu Tan	Lightweight Messages: True Zero-Copy Communication for Commodity Gigabit Ethernet.	EUC Workshops	2006	DBLP DOI BibTeX RDF
12	Hongfeng Zhu, Tianhua Liu, Chuansheng Zhou, Guiran Chang	Research and Implementation of Zero-Copy Technology Based on Device Driver in Linux.	IMSCCS (2)	2006	DBLP DOI BibTeX RDF
12	Manuel Koschuch, Joachim Lechner, Andreas Weitzer, Johann Großschädl, Alexander Szekely, Stefan Tillich, Johannes Wolkerstorfer	Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller.	CHES	2006	DBLP DOI BibTeX RDF
12	Andrés Ortiz 0001, Julio Ortega Lopera, Antonio F. Díaz, Alberto Prieto	Protocol Offload Evaluation Using Simics.	CLUSTER	2006	DBLP DOI BibTeX RDF
12	Nathan L. Binkert, Ali G. Saidi, Steven K. Reinhardt	Integrated network interfaces for high-bandwidth TCP/IP.	ASPLOS	2006	DBLP DOI BibTeX RDF	TCP/IP performance, network, interfaces, zero-copy
12	Kun Yang, Chun Zhang, Zhihua Wang 0001	Design of Adaptive Deblocking Filter for H.264/AVC Decoder SOC.	APCCAS	2006	DBLP DOI BibTeX RDF
12	Jung L. Lee, Myung Hoon Sunwoo	Implementation of a Wireless Multimedia DSP Chip for Mobile Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	multimedia, DSP, instruction
12	Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, Steven K. Reinhardt	Performance Analysis of System Overheads in TCP/IP Workloads.	IEEE PACT	2005	DBLP DOI BibTeX RDF
12	Alexandre E. Eichenberger, Kathryn M. O'Brien, Kevin O'Brien, Peng Wu 0001, Tong Chen 0001, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind	Optimizing Compiler for the CELL Processor.	IEEE PACT	2005	DBLP DOI BibTeX RDF
12	Chul Kim, A. M. Rassau, Mike Myung-Ok Lee	3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
12	Cristinel Ababei, Hushrav Mogal, Kia Bazargan	3D FPGAs: placement, routing, and architecture evaluation (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
12	Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu	Design and test of a scalable security processor.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	H. Peter Hofstee, Michael N. Day	Hardware and software architectures for the CELL processor.	CODES+ISSS	2005	DBLP DOI BibTeX RDF
12	Moonseok Kang, Wonyong Sung	Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processor.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
12	Kiyofumi Tanaka	Casablanca II: Implementation of a Real-Time RISC.	ASAP	2005	DBLP DOI BibTeX RDF
12	Ke Ning, David R. Kaeli	Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.	HiPEAC	2005	DBLP DOI BibTeX RDF	embedded systems, Power-aware, external memory, media processor, bus arbitration
12	Satish Narayanasamy, Gilles Pokam, Brad Calder	BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging.	ISCA	2005	DBLP DOI BibTeX RDF
12	Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Mazin S. Yousif, Chita R. Das	Exploiting NIC Memory for Improving Cluster-Based Webserver Performance.	CLUSTER	2005	DBLP DOI BibTeX RDF
12	Dror Goldenberg, Michael Kagan, Ran Ravid, Michael S. Tsirkin	Transparently Achieving Superior Socket Performance Using Zero Copy Socket Direct Protocol over 20Gb/s InfiniBand Links.	CLUSTER	2005	DBLP DOI BibTeX RDF
12	Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch	HIBRID-SOC: a multi-core architecture for image and video applications.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF
12	Paul Willmann, Michael Brogioli, Vijay S. Pai	Spinach: a liberty-based simulator for programmable network interface architectures.	LCTES	2004	DBLP DOI BibTeX RDF	programmable network interfaces, simulation, embedded systems
12	Francois Labonte, Peter R. Mattson, William Thies, Ian Buck, Christos Kozyrakis, Mark Horowitz	The Stream Virtual Machine.	IEEE PACT	2004	DBLP DOI BibTeX RDF
12	Maria Athanasaki, Evangelos Koukis, Nectarios Koziris	Scheduling of Tiled Nested Loops onto a Cluster with a Fixed Number of SMP Nodes.	PDP	2004	DBLP DOI BibTeX RDF
12	Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis	A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design.	DATE	2004	DBLP DOI BibTeX RDF
12	Ke Ning, David R. Kaeli	Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems.	PACS	2004	DBLP DOI BibTeX RDF	Embedded System, Power-Aware, External Memory, Media Processor, Bus Arbitration
12	Xiaojun Yang, Lili Guo, Peiheng Zhang, Ninghui Sun	Design of System Area Network Interface Card Based on Intel IOP310.	ICESS	2004	DBLP DOI BibTeX RDF
12	Esam El-Araby, Mohamed Taher, Kris Gaj, Tarek A. El-Ghazawi, David Caliga, Nikitas A. Alexandridis	System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications.	IPDPS	2004	DBLP DOI BibTeX RDF
12	Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen	A compact DSP core with static floating-point unit & its microcode generation.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	DSP core, digital signal processor, floating-point units
12	Ozgur Celebican, Tajana Simunic Rosing, Vincent John Mooney III	Energy estimation of peripheral devices in embedded systems.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	audio, device drivers, energy estimation, software optimization