Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Lana Josipovic, Andrea Guerrieri, Paolo Ienne	Speculative Dataflow Circuits.	FPGA	2019	DBLP DOI BibTeX RDF
1	Aimee Coughlin, Greg Cusack, Jack Wampler, Eric Keller, Eric Wustrow	Breaking the Trust Dependence on Third Party Processes for Reconfigurable Secure Hardware.	FPGA	2019	DBLP DOI BibTeX RDF
1	Minghua Shen, Nong Xiao	Parrot: A More Effective Parallel Routing Approach to FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Andrew M. Keller, Michael J. Wirthlin	Impact of Soft Errors on Large-Scale FPGA Cloud Computing.	FPGA	2019	DBLP DOI BibTeX RDF
1	Gurshaant Singh Malik, Nachiket Kapre	Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control.	FPGA	2019	DBLP DOI BibTeX RDF
1	Zhucheng Tang, Guojie Luo, Ming Jiang 0001	FTConv: FPGA Acceleration for Transposed Convolution Layers in Deep Neural Networks.	FPGA	2019	DBLP DOI BibTeX RDF
1	Tushar Garg, Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre	HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Caiwen Ding, Shuo Wang 0009, Ning Liu 0007, Kaidi Xu, Yanzhi Wang, Yun Liang 0001	REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Anastasiia Kucherenko, Stefan Nikolic 0001, Paolo Ienne	On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure.	FPGA	2019	DBLP DOI BibTeX RDF
1	Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz	Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Dallon Glick, Jesse Grigg, Brent E. Nelson, Michael J. Wirthlin	Maverick: A Stand-alone CAD Flow for Xilinx 7-Series FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual	Scalable High Performance SDN Switch Architecture on FPGA for Core Networks.	FPGA	2019	DBLP DOI BibTeX RDF
1	Zheming Jin, Hal Finkel	Nuclear Reactor Simulations on OpenCL FPGA Platform.	FPGA	2019	DBLP DOI BibTeX RDF
1	Kees A. Vissers	Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP).	FPGA	2019	DBLP DOI BibTeX RDF
1	Wuxi Li, Mehrdad E. Dehkordi, Stephen Yang, David Z. Pan	Simultaneous Placement and Clock Tree Construction for Modern FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang	Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System.	FPGA	2019	DBLP DOI BibTeX RDF
1	Jiafeng Xie, Chiou-Yng Lee	Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity.	FPGA	2019	DBLP DOI BibTeX RDF
1	Maciej Besta, Marc Fischer, Tal Ben-Nun, Johannes de Fine Licht, Torsten Hoefler	Substream-Centric Maximum Matchings on FPGA.	FPGA	2019	DBLP DOI BibTeX RDF
1	Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides	EASY: Efficient Arbiter SYnthesis from Multi-threaded Code.	FPGA	2019	DBLP DOI BibTeX RDF
1	Lansong Diao, Zhao Jiang, Hao Liang, Chang'an Ye, Kai Chen 0008, Li Ding, Shunli Dou, Meng Sun, Lixue Xia, Jiansong Zhang, Wei Lin 0016	PAI-FCNN: FPGA Based CNN Inference System.	FPGA	2019	DBLP DOI BibTeX RDF
1	Martin Hardieck, Martin Kumm, Konrad Möller, Peter Zipf	Reconfigurable Convolutional Kernels for Neural Networks on FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Brian Gaide, Ygal Arbel	Network-on-Chip Programmable Platform in VersalTM ACAP Architecture.	FPGA	2019	DBLP DOI BibTeX RDF
1	Katie Lim, Jonathan Balkind, David Wentzlaff	JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores.	FPGA	2019	DBLP DOI BibTeX RDF
1	Jyotikrishna Dass, Yashwardhan Narawane, Rabi N. Mahapatra, Vivek Sarin	FPGA-based Distributed Edge Training of SVM.	FPGA	2019	DBLP DOI BibTeX RDF
1	Chia-Wei Chang, Zi-Qi Zhong, Jing-Jia Liou	A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis.	FPGA	2019	DBLP DOI BibTeX RDF
1	Tom J. Mannos, Brian Dziki, Moslema Sharif	Fault Testing a Synthesizable Embedded Processor at Gate Level using UltraScale FPGA Emulation.	FPGA	2019	DBLP DOI BibTeX RDF
1	Ke Zhang 0017, Yisong Chang, Mingyu Chen 0001, Yungang Bao, Zhiwei Xu 0002	Engaging Heterogeneous FPGAs in the Cloud.	FPGA	2019	DBLP DOI BibTeX RDF
1	Thaddeus Koehn, Peter Athanas	Scheduling Data in Neural Network Applications.	FPGA	2019	DBLP DOI BibTeX RDF
1	Cheng Fu, Shilin Zhu, Hao Su 0001, Ching-En Lee, Jishen Zhao	Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA.	FPGA	2019	DBLP DOI BibTeX RDF
1	Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang 0022, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang	HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.	FPGA	2019	DBLP DOI BibTeX RDF
1	Zachary Sherer, Eric Finnerty, Yan Luo, Hang Liu 0001	Software Hardware Co-Optimized BFS on FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang 0022	Rapid Cycle-Accurate Simulator for High-Level Synthesis.	FPGA	2019	DBLP DOI BibTeX RDF
1	Sandeep Dutta, Adnan Yunus, Artem Marisov, Matt Menezes, Somayeh Rahimipour	Visual System Integrator: Invited Tutorial.	FPGA	2019	DBLP DOI BibTeX RDF
1	Carl-Johannes Johnsen, Kenneth Skovhede	Building FPGA State Machines from Sequential Code.	FPGA	2019	DBLP DOI BibTeX RDF
1	Venkat Konda	Flat FPGA Fabrics Derived from 2D-Benes-BFT-Pyramid Networks with Optimizations and Enhancements.	FPGA	2019	DBLP DOI BibTeX RDF
1	Yazhu Lan, Qingli Guo, Guohe Zhang, Yuanchao Xu 0002, Kent W. Nixon, Hai Helen Li, Yiran Chen 0001	Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting.	FPGA	2019	DBLP DOI BibTeX RDF
1	Tianqi Gao, Rob A. Rutenbar	A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference.	FPGA	2019	DBLP DOI BibTeX RDF
1	Juan Escobedo, Mingjie Lin	Optimizing Order-Associative Kernel Computation with Joint Memory Banking and Data Reuse.	FPGA	2019	DBLP DOI BibTeX RDF
1	Shijie Cao, Chen Zhang 0001, Zhuliang Yao, Wencong Xiao, Lanshun Nie, De-chen Zhan, Yunxin Liu, Ming Wu 0007, Lintao Zhang	Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity.	FPGA	2019	DBLP DOI BibTeX RDF
1	Shulin Zeng, Yujun Lin 0001, Shuang Liang 0010, Junlong Kang, Dongliang Xie, Yi Shan, Song Han 0003, Yu Wang 0002, Huazhong Yang	A Fine-Grained Sparse Accelerator for Multi-Precision DNN.	FPGA	2019	DBLP DOI BibTeX RDF
1	Ephrem Wu, Xiaoqian Zhang, David Berman, Inkeun Cho, John Thendean	Compute-Efficient Neural-Network Acceleration.	FPGA	2019	DBLP DOI BibTeX RDF
1	Konstantinos Maragos 0001, George Lentaris, Dimitrios Soudris, Vasilis F. Pavlidis	PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Daniel Rozhko, Paul Chow	The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Anping He, Jinlin Zhang, Lvying Yu, Pengfei Li, Lian Li	How to Accelerate FPGA Application in an Asynchronous Way?	FPGA	2019	DBLP DOI BibTeX RDF
1	Kaiyuan Guo, Shuang Liang 0010, Jincheng Yu, Xuefei Ning, Wenshuo Li, Yu Wang 0002, Huazhong Yang	Compressed CNN Training with FPGA-based Accelerator.	FPGA	2019	DBLP DOI BibTeX RDF
1	Javier M. Duarte, Song Han 0003, Philip C. Harris, Sergo Jindariani, Edward Kreinar, Benjamin Kreis, Vladimir Loncar, Jennifer Ngadiuba, Maurizio Pierini, Dylan S. Rankin, Ryan A. Rivera, Sioni Summers, Nhan Tran, Zhenbin Wu	Fast Inference of Deep Neural Networks for Real-time Particle Physics Applications.	FPGA	2019	DBLP DOI BibTeX RDF
1	Liqiang Lu, Yun Liang 0001, Ruirui Huang, Wei Lin 0016, Xiaoyuan Cui, Jiansong Zhang	Speedy: An Accelerator for Sparse Convolutional Neural Networks on FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Sahand Salamat, Mohsen Imani, Behnam Khaleghi, Tajana Rosing	F5-HD: Fast Flexible FPGA-based Framework for Refreshing Hyperdimensional Computing.	FPGA	2019	DBLP DOI BibTeX RDF
1	Hongzheng Chen, Minghua Shen	A Deep-Reinforcement-Learning-Based Scheduler for High-Level Synthesis.	FPGA	2019	DBLP DOI BibTeX RDF
1	Zhiyuan Shao, Ruoshi Li, Diqing Hu, Xiaofei Liao, Hai Jin 0001	Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching.	FPGA	2019	DBLP DOI BibTeX RDF
1	Michael P. Kapralos, John A. Chandy	HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion.	FPGA	2019	DBLP DOI BibTeX RDF
1	Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer	Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture.	FPGA	2019	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato	An FPGA-based Fine Tuning Accelerator for a Sparse CNN.	FPGA	2019	DBLP DOI BibTeX RDF
1	George Provelengios, Chethan Ramesh, Shivukumar B. Patil, Ken Eguro, Russell Tessier, Daniel E. Holcomb	Characterization of Long Wire Data Leakage in Deep Submicron FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Xuechao Wei, Yun Liang 0001, Peng Zhang 0007, Cody Hao Yu, Jason Cong	Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment.	FPGA	2019	DBLP DOI BibTeX RDF
1	Mikhail Asiatici, Paolo Ienne	Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Jialiang Zhang, Jing Li 0073	Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization.	FPGA	2019	DBLP DOI BibTeX RDF
1	Elham Azari, Aykut Dengi, Sarma B. K. Vrudhula	An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing.	FPGA	2019	DBLP DOI BibTeX RDF
1	Dan Cristian Turicu, Octavian Cret, Lucia Vacariu	Storage Mirroring for Bare-Metal Systems on FPGA Devices.	FPGA	2019	DBLP DOI BibTeX RDF
1	Chen Chen, Jun Xia, Wenmin Yang, Kang Li, Zhilei Chai	A PYNQ-compliant Online Platform for Zynq-based DNN Developers.	FPGA	2019	DBLP DOI BibTeX RDF
1	Dario Korolija, Mirjana Stojilovic	Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform.	FPGA	2019	DBLP DOI BibTeX RDF
1	Yao Chen 0008, Jiong He, Xiaofan Zhang 0001, Cong Hao, Deming Chen	Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs.	FPGA	2019	DBLP DOI BibTeX RDF
1	Lu Jing, Jun Liu, FuHai Yu	A Deep Learning Inference Accelerator Based on Model Compression on FPGA.	FPGA	2019	DBLP DOI BibTeX RDF
1	Venkat Konda	Hierarchical FPGA Fabrics using 2D-Benes-BFT-Pyramid Network Layouts with Optimizations.	FPGA	2019	DBLP DOI BibTeX RDF
1	Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton	On-chip FPGA Debug Instrumentation for Machine Learning Applications.	FPGA	2019	DBLP DOI BibTeX RDF
1	Shenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter A. Milder	A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs.	FPGA	2018	DBLP DOI BibTeX RDF
1	Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong	A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.	FPGA	2018	DBLP DOI BibTeX RDF
1	Ning Mao, Zhihong Huang, Xing Wei, He Zhao, Xinkai Di, Le Yu, Haigang Yang	A Self-adaptation Method of Fitting Convolutional Neural Network into FPGA: Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Jason Cong, Zhenman Fang, Yao Hu, Di Wu 0010	K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Stephen M. Williams, Mingjie Lin	Architecture and Circuit Design of an All-Spintronic FPGA.	FPGA	2018	DBLP DOI BibTeX RDF
1	Minghua Shen, Jiaxi Zhang 0001, Nong Xiao, Guojie Luo	BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Wenyi Feng, Jonathan W. Greene, Alan Mishchenko	Improving FPGA Performance with a S44 LUT Structure.	FPGA	2018	DBLP DOI BibTeX RDF
1	Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Hamid Reza Zohouri, Artur Podobas, Satoshi Matsuoka	Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL.	FPGA	2018	DBLP DOI BibTeX RDF
1	Chin Hau Hoo, Akash Kumar 0001	ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling.	FPGA	2018	DBLP DOI BibTeX RDF
1	Kenichi Koizumi, Kei Hiraki, Mary Inaba	Continuous Skyline Computation Accelerator with Parallelizing Dominance Relation Calculations: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Ho-Cheung Ng, Shuanglong Liu, Wayne Luk	ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development.	FPGA	2018	DBLP DOI BibTeX RDF
1	Minghua Shen, Wentai Zhang 0001, Nong Xiao, Guojie Luo	Towards Serial-Equivalent Parallel Routing for FPGAs: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Zheming Jin, Kazutomo Yoshii	Optimizations of Sequence Alignment on FPGA: A Case Study of Extended Sequence Alignment (Abstact Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang 0002, Jingxian Xu, Shaochong Zhang	Understanding Performance Differences of FPGAs and GPUs: (Abtract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Juexiao Su, Lei He 0001	Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Shuanglong Liu, Xinyu Niu, Wayne Luk	A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only.	FPGA	2018	DBLP DOI BibTeX RDF
1	Soheil Mohajer, Zhiheng Wang 0002, Kia Bazargan	Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data.	FPGA	2018	DBLP DOI BibTeX RDF
1	Hanqing Zeng, Ren Chen, Chi Zhang 0022, Viktor K. Prasanna	A Framework for Generating High Throughput CNN Implementations on FPGAs.	FPGA	2018	DBLP DOI BibTeX RDF
1	Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li 0073	Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform.	FPGA	2018	DBLP DOI BibTeX RDF
1	Juan Escobedo, Mingjie Lin	Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing Kernels.	FPGA	2018	DBLP DOI BibTeX RDF
1	Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek	Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.	FPGA	2018	DBLP DOI BibTeX RDF
1	Luka Daoud, Muhammad Kamran Latif, Nader Rafla 0001	SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	François Serre, Markus Püschel	Memory-Efficient Fast Fourier Transform on Streaming Data by Fusing Permutations.	FPGA	2018	DBLP DOI BibTeX RDF
1	Fady Hussein, Luka Daoud, Nader Rafla 0001	HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Yankang Du, Qinrang Liu, Shuai Wei, Chen Gao	Software-Defined FPGA-Based Accelerator for Deep Convolutional Neural Networks: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang	Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA.	FPGA	2018	DBLP DOI BibTeX RDF
1	Oluseyi A. Ayorinde, He Qi, Benton H. Calhoun	FGC: A Tool-flow for Generating and Configuring Custom FPGAs(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois	P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs.	FPGA	2018	DBLP DOI BibTeX RDF
1	Nachiket Kapre, Tushar Krishna	FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Jan Dürre, Dario Paradzik, Holger Blume	A HOG-based Real-time and Multi-scale Pedestrian Detector Demonstration System on FPGA.	FPGA	2018	DBLP DOI BibTeX RDF
1	Nan Ding 0001, Wei Zhang 0199, Yanhua Ma, Zhenguo Gao	Software/Hardware Co-design for Multichannel Scheduling in IEEE 802.11p MLME: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Daisuke Suzuki, Takahiro Hanyu	Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Yuze Chi, Peipei Zhou 0001, Jason Cong	An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang	Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs.	FPGA	2018	DBLP DOI BibTeX RDF

Publications at "FPGA"( http://dblp.L3S.de/Venues/FPGA )