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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 197 occurrences of 123 keywords
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Results
Found 450 publication records. Showing 450 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge |
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 7(4), pp. 17:1-17:18, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Abbas Rahimi, Mostafa E. Salehi, Siamak Mohammadi, Sied Mehdi Fakhraie |
Low-energy GALS NoC with FIFO - Monitoring dynamic voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 42(6), pp. 889-896, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Xin Fan 0003, Milos Krstic, Christoph Wolf, Eckhard Grass |
GALS Design for On-chip Ground Bounce Suppression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 17th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2011, Cornell University, Ithaca, New York, USA, 27-29 April 2011, pp. 43-52, 2011, IEEE Computer Society, 978-0-7695-4383-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Hemanth Prabhu, Sherine Thomas, Joachim Neves Rodrigues, Thomas Olsson 0001, Anders Carlsson |
A GALS ASIC implementation from a CAL dataflow description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, pp. 1-4, 2011, IEEE, 978-1-4577-0514-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Hala A. Farouk, Mahmoud T. El-Hadidi, Ahmed A. El Farag |
GALS-Based LPSP: Implementation of a Novel Architecture for Low Power High Performance Security Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 25th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2011, Anchorage, Alaska, USA, 16-20 May 2011 - Workshop Proceedings, pp. 542-550, 2011, IEEE, 978-1-61284-425-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Avinash Malik, Alain Girault, Zoran Salcic |
A GALS Language for Dynamic Distributed and Reactive Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 11th International Conference on Application of Concurrency to System Design, ACSD 2011, Newcastle Upon Tyne, UK, 20-24 June, 2011, pp. 173-182, 2011, IEEE Computer Society, 978-0-7695-4387-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | |
Notice of Violation of IEEE Publication PrinciplesDelayed Latching for Data Synchronization in GALS SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICETET ![In: 4th International Conference on Emerging Trends in Engineering and Technology, ICETET 2011, Mauritius, November 18-20, 2011, pp. 247-252, 2011, IEEE Computer Society, 978-0-7695-4561-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Jean-Michel Chabloz, Ahmed Hemani |
A GALS Network-on-Chip based on rationally-related frequencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011, pp. 12-18, 2011, IEEE Computer Society, 978-1-4577-1953-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Zhiyi Yu, Zewen Shi, Xiaoyang Zeng |
Fault tolerant computing for stream DSP applications using GALS multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 2305-2308, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Milos Krstic, Xin Fan 0003, Eckhard Grass, Christoph Heer, Birgit Sanders, Luca Benini, Mohammad Reza Kakoee, Alessandro Strano, Davide Bertozzi |
Moonrake chip - GALS demonstrator in 40 nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: 2011 International Symposium on System on Chip, SoC 2011, Tampere, Finland, October 31 - November 2, 2011, pp. 9-13, 2011, IEEE, 978-1-4577-0671-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi |
Mesochronous NoC technology for power-efficient GALS MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INA-OCMC@HiPEAC ![In: Proceedings of the Fifth International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC '11, Heraklion, Greece, January 23, 2011, pp. 27-30, 2011, ACM, 978-1-4503-0272-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Zhiyi Yu, Bevan M. Baas |
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(5), pp. 750-762, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Avinash Malik, Zoran Salcic, Partha S. Roop, Alain Girault |
SystemJ: A GALS language for system level design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Lang. Syst. Struct. ![In: Comput. Lang. Syst. Struct. 36(4), pp. 317-344, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas |
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6), pp. 897-910, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad |
Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10), pp. 2696-2707, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Mehdi Sedighi, Sam Farrokhi |
GALS system optimization using retiming concept. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 7(3), pp. 209-215, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Carlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira 0001, Isabel C. Teixeira, José C. Silva, Pedro Lousã, João Varela |
Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, pp. 72-77, 2010, IEEE Computer Society, 978-1-4244-6612-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin |
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 43-50, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Carles Hernández 0001, Antoni Roca 0001, Federico Silla, José Flich, José Duato |
Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 35-42, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Mohammad Fattah, Abdurrahman Manian, Abbas Rahimi, Siamak Mohammadi |
A High Throughput Low Power FIFO Used for GALS NoC Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2010, 5-7 July 2010, Lixouri Kefalonia, Greece, pp. 333-338, 2010, IEEE Computer Society, 978-0-7695-4076-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi |
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 679-684, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Yvain Thonnart, Pascal Vivet, Fabien Clermidy |
A fully-asynchronous low-power framework for GALS NoC integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 33-38, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Tim Kranich, Mladen Berekovic |
NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France, pp. 53-59, 2010, IEEE Computer Society, 978-0-7695-4171-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Wei-Tsun Sun, Zoran Salcic, Avinash Malik |
LibGALS: a library for GALS systems design and modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 107-112, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres |
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010, pp. 115-120, 2010, ACM, 978-1-4503-0152-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Duan Wei, Fan Qi Fei, Huang Kun, Zhang Ge |
VB-DVFS: A new algorithm for power efficiency of CMP with GALS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pp. 297-300, 2010, IEEE, 978-1-4244-8155-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Xin Fan 0003, Milos Krstic, Christoph Wolf, Eckhard Grass |
A GALS FFT processor with clock modulation for low-EMI applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010, pp. 273-278, 2010, IEEE Computer Society, 978-1-4244-6967-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Alessandro Strano, Carles Hernández 0001, Federico Silla, Davide Bertozzi |
Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: 2010 International Symposium on System on Chip, SoC 2010, Tampere, September 29-30, 2010, pp. 43-48, 2010, IEEE, 978-1-4244-8279-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Yuan-Teng Chang, Wei-Che Chen, Hung-Yue Tsai, Wei-Min Cheng, Chang-Jiu Chen, Fu-Chiung Cheng |
A low-latency GALS interface implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 1183-1186, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Rafael Iankowski Soares |
Arquitetura GALS pipeline para criptografia robusta a ataques DPA e DEMA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2010 |
RDF |
|
20 | Shufan Yang, Stephen B. Furber, Yebin Shi, Luis A. Plana |
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fundam. Informaticae ![In: Fundam. Informaticae 95(1), pp. 53-72, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Milos Krstic, Xin Fan 0003, Eckhard Grass, Frank K. Gürkaynak |
GALS for Bursty Data Transfer based on Clock Coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMGALS@DATE ![In: Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, FMGALS@DATE 2009, Nice, France, April 24, 2009, pp. 103-113, 2009, Elsevier. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | David Kinniment |
Synchronization and Arbitration in GALS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMGALS@DATE ![In: Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, FMGALS@DATE 2009, Nice, France, April 24, 2009, pp. 85-101, 2009, Elsevier. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Kenneth S. Stevens, Daniel Gebhardt, JunBok You, Yang Xu 0036, Vikas S. Vij, Shomit Das, Krishnaji Desai |
The Future of Formal Methods and GALS Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMGALS@DATE ![In: Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, FMGALS@DATE 2009, Nice, France, April 24, 2009, pp. 115-134, 2009, Elsevier. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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20 | Zhiyi Yu, Bevan M. Baas |
High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 17(1), pp. 66-79, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | René Gagné, Jean Belzile, Claude Thibeault |
From synchronous to GALS: A new architecture for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 40(11), pp. 1657-1666, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Anh Thien Tran, Dean Truong, Bevan M. Baas |
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings, pp. 214-223, 2009, IEEE Computer Society, 978-1-4244-4142-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Tomasz Król, Milos Krstic, Xin Fan 0003, Eckhard Grass |
Modeling and Reducing EMI in GALS and Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers, pp. 146-155, 2009, Springer, 978-3-642-11801-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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20 | Yvain Thonnart, Edith Beigné, Pascal Vivet |
Design and Implementation of a GALS Adapter for ANoC Based Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 15th IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, USA, May 17-20, 2009, pp. 13-22, 2009, IEEE Computer Society, 978-1-4244-3933-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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20 | Jian Wu, Steve B. Furber, Jim D. Garside |
A Programmable Adaptive Router for a GALS Parallel System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 15th IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, USA, May 17-20, 2009, pp. 23-31, 2009, IEEE Computer Society, 978-1-4244-3933-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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20 | Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli |
sFPGA2 - A scalable GALS FPGA architecture and design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic, pp. 314-319, 2009, IEEE, 978-1-4244-3892-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Xin Fan 0003, Milos Krstic, Eckhard Grass |
Analysis and optimization of pausible clocking based GALS design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 27th International Conference on Computer Design, ICCD 2009, Lake Tahoe, CA, USA, October 4-7, 2009, pp. 358-365, 2009, IEEE Computer Society, 978-1-4244-5029-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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20 | Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas |
A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 996-999, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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20 | Xuguang Guan, Duan Zhou, Yintang Yang, Zhangming Zhu |
A GALS Delay-insensitive Self-timed Wrapper for Network on Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACCS ![In: 2009 Pacific-Asia Conference on Circuits, Communications and Systems, PACCS 2009, Chengdu, China, 16-17 May 2009, pp. 265-268, 2009, IEEE Computer Society, 978-0-7695-3614-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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20 | Xuguang Guan, Duan Zhou, Dan Wang, Yintang Yang, Zhangming Zhu |
A Novel GALS Single-Track Protocol Asynchronous Communication Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACCS ![In: 2009 Pacific-Asia Conference on Circuits, Communications and Systems, PACCS 2009, Chengdu, China, 16-17 May 2009, pp. 269-272, 2009, IEEE Computer Society, 978-0-7695-3614-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Ning Wu, Fen Ge, Fei Wu |
Design of a GALS Wrapper for Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSIE (3) ![In: CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31 - April 2, 2009, Los Angeles, California, USA, 7 Volumes, pp. 592-595, 2009, IEEE Computer Society, 978-0-7695-3507-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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20 | Linlin Zhang, Virginie Fresse, Anne-Claire Legrand, Mohammed A. S. Khalid |
GALS NoC architectures on FPGA dedicated to multispectral image applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 17th European Signal Processing Conference, EUSIPCO 2009, Glasgow, Scotland, UK, August 24-28, 2009, pp. 978-982, 2009, IEEE, 978-161-7388-76-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
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20 | Abbas Sheibanyrad, Alain Greiner |
Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 41(1), pp. 17-26, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Myeong-Hoon Oh, Seongwoon Kim |
Low Static Powered Asynchronous Data Transfer for GALS System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 91-D(4), pp. 1189-1192, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Javier D. Garcia-Lasheras |
Efficient implementation of GALS systems over commercial synchronous FPGAs: a new approach ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/0802.3441, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
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20 | Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans |
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, pp. 347-352, 2008, IEEE Computer Society, 978-0-7695-3170-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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20 | Shufan Yang, Steve B. Furber, Yebin Shi, Luis A. Plana |
An admission control system for QoS provision on a best-effort GALS interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 8th International Conference on Application of Concurrency to System Design (ACSD 2008), Xi'an, China, June 23-27, 2008, pp. 200-207, 2008, IEEE, 978-1-4244-1838-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Avinash Malik, Zoran Salcic, Partha S. Roop |
Tandem virtual machine - An efficient execution platform for GALS language SystemJ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 13th Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008, Hsinchu, China, August 4-6, 2008, pp. 1-8, 2008, IEEE Computer Society, 978-1-4244-2682-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Syed Suhaib, Bijoy Antony Jose, Sandeep K. Shukla, Deepak Mathaikutty |
Formal Transformation of a KPN Specification to a GALS Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2008, September 23-25, 2008, Stuttgart, Germany, Proceedings, pp. 84-89, 2008, IEEE, 978-1-4244-2265-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Niranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam |
Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 351-356, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Heikki Kariniemi, Jari Nurmi |
Micronmesh for fault-tolerant GALS Multiprocessors on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: 2008 IEEE International Symposium on System-on-Chip, SOC 2008, Tampere, Finland, November 5-6, 2008, pp. 1-8, 2008, IEEE, 978-1-4244-2541-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | JunBok You, Yang Xu 0036, Hosuk Han, Kenneth S. Stevens |
Performance Evaluation of Elastic GALS Interfaces and Network Fabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMGALS@MEMOCODE ![In: Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design, FMGALS@MEMOCODE 2007, Nice, France, May 29, 2007, pp. 17-32, 2007, Elsevier. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla |
Dataflow Architectures for GALS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMGALS@MEMOCODE ![In: Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design, FMGALS@MEMOCODE 2007, Nice, France, May 29, 2007, pp. 33-50, 2007, Elsevier. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Sohini Dasgupta, Alex Yakovle |
Comparative analysis of GALS clocking schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 1(2), pp. 59-69, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Tejpal Singh, Alexander Taubin |
A Highly Scalable GALS Crossbar Using Token Ring Arbitration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 464-472, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
crossbar design, scalability, latency, arbitration, token rings |
20 | Ivan Miro Panades, Alain Greiner |
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 83-94, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Abbas Sheibanyrad, Alain Greiner |
Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2007 International Conference on Embedded Systems & Applications, USA 2007, June 25-28, 2007, Las Vegas, Nevada, USA, pp. 27-33, 2007, CSREA Press, 1-60132-052-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
20 | Samuel Evain, Jean-Philippe Diguet, Dominique Houzet |
NoC Design Flow for TDMA and QoS Management in a GALS Context. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2006, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad |
A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nano-Net ![In: 1st International ICST Conference on Nano-Networks, Nano-Net 2006, Lausanne, Switzerland, September 14-16, 2006, pp. 1-5, 2006, IEEE, 1-4244-0391-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Giuseppe Campobello, Marco Castano, Carmine Ciofi, Daniele Mangano |
GALS networks on chip: a new solution for asynchronous delay-insensitive links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 160-165, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Zhiyi Yu, Bevan M. Baas |
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, pp. 174-179, 2006, IEEE, 978-0-7803-9707-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla |
A Trace Based Framework for Validation of SoC Designs with GALS Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006, pp. 247-250, 2006, IEEE, 0-7803-9781-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Sohini Dasgupta, Alex Yakovlev |
Modeling And Performance Analysis of GALS architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: International Symposium on System-on-Chip, SoC 2006, Tampere, Finland, November 13-16, 2006, pp. 1-4, 2006, IEEE, 1-4244-0621-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Frank Kagan Gürkaynak |
GALS system design: side channel attack secure cryptographic accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
RDF |
|
20 | Frederic Doucet, Massimiliano Menarini, Ingolf H. Krüger, Rajesh K. Gupta 0001, Jean-Pierre Talpin |
A Verification Approach for GALS Integration of Synchronous Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMGALS@MEMOCODE ![In: Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, FMGALS@MEMOCODE 2005, Verona, Italy, July 15, 2005, pp. 105-131, 2005, Elsevier. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner |
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMGALS@MEMOCODE ![In: Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, FMGALS@MEMOCODE 2005, Verona, Italy, July 15, 2005, pp. 133-149, 2005, Elsevier. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | David S. Bormann |
GALS Test Chip on 130nm Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMGALS@MEMOCODE ![In: Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, FMGALS@MEMOCODE 2005, Verona, Italy, July 15, 2005, pp. 29-40, 2005, Elsevier. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Koushik Niyogi, Diana Marculescu |
Speed and voltage selection for GALS systems based on voltage/frequency islands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 292-297, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin |
GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 299-304, 2005, IEEE, 0-7803-9362-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Yongkang Zhu, David H. Albonesi, Alper Buyuktosunoglu |
A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2005, March 20-22, 2005, Austin, Texas, USA, Proceedings, pp. 42-53, 2005, IEEE Computer Society, 0-7803-8965-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Arun Vijayaraghavan, M. Kannan, R. Seshasayanan |
Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005, pp. 143-152, 2005, CSREA Press, 1-932415-54-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
20 | Koushik Niyogi, Diana Marculescu |
System level power and performance modeling of GALS point-to-point communication interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 381-386, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
mixed clock FIFO, pausible clock, power modeling, globally asynchronous locally synchronous |
20 | Tobias Bjerregaard, Shankar Mahadevan, Rasmus Grøndahl Olsen, Jens Sparsø |
An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2005 International Symposium on System-on-Chip, Tampere, Finland, November 15-17, 2005, pp. 171-174, 2005, IEEE, 0-7803-9294-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Aristides Efthymiou, John Bainbridge, Douglas A. Edwards |
Adding Testability to an Asynchronous Interconnect for GALS SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 20-23, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Scott F. Smith 0002 |
Performance of a GALS Single-Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA '04, June 21-24, 2004, Las Vegas, Nevada, USA, Volume 1, pp. 449-454, 2004, CSREA Press, 1-892512-23-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
20 | Shengxian Zhuang, Weidong Li, Jonas Carlsson, Kent Palmkvist, Lars Wanhammar |
Asynchronous data communication with low power for GALS systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, pp. 753-756, 2002, IEEE, 0-7803-7596-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Chong H. Lee, Douglas V. Hall, Marek A. Perkowski, David S. Jun |
Self-repairable GALs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 47(2), pp. 119-135, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Greg Garvey, Brenda Laurel, Rob Tow, Joan I. Staveley, Allucquère Rosanne Stone |
Grids, guys and gals: are you oppressed by the Cartesian coordinate system? (panel session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGGRAPH ![In: Proceedings of the 22nd Annual Conference on Computer Graphics and Interactive Techniques, SIGGRAPH 1995, Los Angeles, CA, USA, August 6-11, 1995, pp. 503-505, 1995, ACM, 0-89791-701-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Daniel Gebhardt, JunBok You, Kenneth S. Stevens |
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 115-122, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
network, CAD, SoC, topology, asynchronous, floorplan, router, EDA, NoC, GALS |
19 | Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi |
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 51-58, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asynchronous interconnect, NoC, GALS, on-chip networks |
19 | Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das |
Coordinated power management of voltage islands in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: SIGMETRICS 2010, Proceedings of the 2010 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, New York, New York, USA, 14-18 June 2010, pp. 359-360, 2010, ACM, 978-1-4503-0038-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
chip multiprocessors (CMP), control theory, GALs, DVFs |
19 | Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 267-276, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs) |
19 | Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes |
Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 24-29, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
floating point hardware, GALS design, FPGA, prototyping, embedded processor |
19 | Dumitru Potop-Butucaru, Robert de Simone, Yves Sorel, Jean-Pierre Talpin |
From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Ninth International Conference on Application of Concurrency to System Design, ACSD 2009, Augsburg, Germany, 1-3 July 2009, pp. 42-51, 2009, IEEE Computer Society, 978-0-7695-3697-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
synchronous specification, asynchronous implementation, weak endochrony, GALS |
19 | Josefa Díaz, José Ignacio Hidalgo, Francisco Fernández 0001, Oscar Garnica, Sonia López |
Improving SMT performance: an application of genetic algorithms to configure resizable caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO (Companion) ![In: Genetic and Evolutionary Computation Conference, GECCO 2009, Proceedings, Montreal, Québec, Canada, July 8-12, 2009, Companion Material, pp. 2029-2034, 2009, ACM, 978-1-60558-505-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reconfigurable caches, genetic algorithms, optimization, caches memories, simultaneous multithreading, gals, adaptive caches |
19 | Emre Tuncer, Jordi Cortadella, Luciano Lavagno |
Enabling adaptability through elastic clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 8-10, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power design, GALS, desynchronization, adaptive voltage scaling |
19 | Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli |
Composing heterogeneous reactive systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(4), pp. 43:1-43:36, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
correct-by-construction design, reactive systems, Compositionality, models of computation, GALS |
19 | Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach |
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 149-158, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous |
19 | Luis A. Plana, John Bainbridge, Steve B. Furber, Sean Salisbury, Yebin Shi, Jian Wu |
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 215-216, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Synchonizer, source-address routing, GALS, Bandwidth aggregation |
19 | Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung |
AsAP: A Fine-Grained Many-Core Platform for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(2), pp. 34-45, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MIMD processors, GALS networking, embedded systems, multiprocessors, digital signal processing, microarchitecture, special-purpose and application-based systems |
19 | Dumitru Potop-Butucaru, Robert de Simone, Yves Sorel |
Necessary and sufficient conditions for deterministic desynchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 7th ACM & IEEE International conference on Embedded software, EMSOFT 2007, September 30 - October 3, 2007, Salzburg, Austria, pp. 124-133, 2007, ACM, 978-1-59593-825-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
endochrony, execution machine, reaction to signal absence, correctness, determinism, GALS, desynchronization, kahn process network |
19 | Jean-Pierre Talpin, Paul Le Guernic |
An algebraic theory for behavioral modeling and protocol synthesis in system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 28(2), pp. 131-151, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
GALS design, Process algebra, Synchrony, Compositional modeling |
19 | Tobias Bjerregaard, Shankar Mahadevan |
A survey of research and practices of Network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 38(1), pp. 1, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions |
19 | Marco Zennaro, Raja Sengupta |
Distributing synchronous programs using bounded queues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings, pp. 325-334, 2005, ACM, 1-59593-091-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
distributed synchronous programs, globally asynchronous locally synchronous architecture, GALS, Simulink |
19 | Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli |
Tag machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings, pp. 255-263, 2005, ACM, 1-59593-091-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
distributed deployment, heterogeneous reactive systems, GALS, tagged systems |
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