Search results for "GALS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge	SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip.	ACM J. Emerg. Technol. Comput. Syst.	2011	DBLP DOI BibTeX RDF
20	Abbas Rahimi, Mostafa E. Salehi, Siamak Mohammadi, Sied Mehdi Fakhraie	Low-energy GALS NoC with FIFO - Monitoring dynamic voltage scaling.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
20	Xin Fan 0003, Milos Krstic, Christoph Wolf, Eckhard Grass	GALS Design for On-chip Ground Bounce Suppression.	ASYNC	2011	DBLP DOI BibTeX RDF
20	Hemanth Prabhu, Sherine Thomas, Joachim Neves Rodrigues, Thomas Olsson 0001, Anders Carlsson	A GALS ASIC implementation from a CAL dataflow description.	NORCHIP	2011	DBLP DOI BibTeX RDF
20	Hala A. Farouk, Mahmoud T. El-Hadidi, Ahmed A. El Farag	GALS-Based LPSP: Implementation of a Novel Architecture for Low Power High Performance Security Processors.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
20	Avinash Malik, Alain Girault, Zoran Salcic	A GALS Language for Dynamic Distributed and Reactive Programs.	ACSD	2011	DBLP DOI BibTeX RDF
20		Notice of Violation of IEEE Publication PrinciplesDelayed Latching for Data Synchronization in GALS SOC.	ICETET	2011	DBLP DOI BibTeX RDF
20	Jean-Michel Chabloz, Ahmed Hemani	A GALS Network-on-Chip based on rationally-related frequencies.	ICCD	2011	DBLP DOI BibTeX RDF
20	Zhiyi Yu, Zewen Shi, Xiaoyang Zeng	Fault tolerant computing for stream DSP applications using GALS multi-core processors.	ISCAS	2011	DBLP DOI BibTeX RDF
20	Milos Krstic, Xin Fan 0003, Eckhard Grass, Christoph Heer, Birgit Sanders, Luca Benini, Mohammad Reza Kakoee, Alessandro Strano, Davide Bertozzi	Moonrake chip - GALS demonstrator in 40 nm CMOS technology.	SoC	2011	DBLP DOI BibTeX RDF
20	Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi	Mesochronous NoC technology for power-efficient GALS MPSoCs.	INA-OCMC@HiPEAC	2011	DBLP DOI BibTeX RDF
20	Zhiyi Yu, Bevan M. Baas	A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
20	Avinash Malik, Zoran Salcic, Partha S. Roop, Alain Girault	SystemJ: A GALS language for system level design.	Comput. Lang. Syst. Struct.	2010	DBLP DOI BibTeX RDF
20	Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas	A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
20	Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad	Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
20	Mehdi Sedighi, Sam Farrokhi	GALS system optimization using retiming concept.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
20	Carlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira 0001, Isabel C. Teixeira, José C. Silva, Pedro Lousã, João Varela	Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems.	DDECS	2010	DBLP DOI BibTeX RDF
20	Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin	A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors.	NOCS	2010	DBLP DOI BibTeX RDF
20	Carles Hernández 0001, Antoni Roca 0001, Federico Silla, José Flich, José Duato	Improving the Performance of GALS-Based NoCs in the Presence of Process Variation.	NOCS	2010	DBLP DOI BibTeX RDF
20	Mohammad Fattah, Abdurrahman Manian, Abbas Rahimi, Siamak Mohammadi	A High Throughput Low Power FIFO Used for GALS NoC Buffers.	ISVLSI	2010	DBLP DOI BibTeX RDF
20	Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi	Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.	DATE	2010	DBLP DOI BibTeX RDF
20	Yvain Thonnart, Pascal Vivet, Fabien Clermidy	A fully-asynchronous low-power framework for GALS NoC integration.	DATE	2010	DBLP DOI BibTeX RDF
20	Tim Kranich, Mladen Berekovic	NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems.	DSD	2010	DBLP DOI BibTeX RDF
20	Wei-Tsun Sun, Zoran Salcic, Avinash Malik	LibGALS: a library for GALS systems design and modeling.	ASP-DAC	2010	DBLP DOI BibTeX RDF
20	Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres	A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks.	SBCCI	2010	DBLP DOI BibTeX RDF
20	Duan Wei, Fan Qi Fei, Huang Kun, Zhang Ge	VB-DVFS: A new algorithm for power efficiency of CMP with GALS.	ICECS	2010	DBLP DOI BibTeX RDF
20	Xin Fan 0003, Milos Krstic, Christoph Wolf, Eckhard Grass	A GALS FFT processor with clock modulation for low-EMI applications.	ASAP	2010	DBLP DOI BibTeX RDF
20	Alessandro Strano, Carles Hernández 0001, Federico Silla, Davide Bertozzi	Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip.	SoC	2010	DBLP DOI BibTeX RDF
20	Yuan-Teng Chang, Wei-Che Chen, Hung-Yue Tsai, Wei-Min Cheng, Chang-Jiu Chen, Fu-Chiung Cheng	A low-latency GALS interface implementation.	APCCAS	2010	DBLP DOI BibTeX RDF
20	Rafael Iankowski Soares	Arquitetura GALS pipeline para criptografia robusta a ataques DPA e DEMA.		2010	RDF
20	Shufan Yang, Stephen B. Furber, Yebin Shi, Luis A. Plana	A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect.	Fundam. Informaticae	2009	DBLP DOI BibTeX RDF
20	Milos Krstic, Xin Fan 0003, Eckhard Grass, Frank K. Gürkaynak	GALS for Bursty Data Transfer based on Clock Coupling.	FMGALS@DATE	2009	DBLP DOI BibTeX RDF
20	David Kinniment	Synchronization and Arbitration in GALS.	FMGALS@DATE	2009	DBLP DOI BibTeX RDF
20	Kenneth S. Stevens, Daniel Gebhardt, JunBok You, Yang Xu 0036, Vikas S. Vij, Shomit Das, Krishnaji Desai	The Future of Formal Methods and GALS Design.	FMGALS@DATE	2009	DBLP DOI BibTeX RDF
20	Zhiyi Yu, Bevan M. Baas	High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
20	René Gagné, Jean Belzile, Claude Thibeault	From synchronous to GALS: A new architecture for FPGAs.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
20	Anh Thien Tran, Dean Truong, Bevan M. Baas	A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network.	NOCS	2009	DBLP DOI BibTeX RDF
20	Tomasz Król, Milos Krstic, Xin Fan 0003, Eckhard Grass	Modeling and Reducing EMI in GALS and Synchronous Systems.	PATMOS	2009	DBLP DOI BibTeX RDF
20	Yvain Thonnart, Edith Beigné, Pascal Vivet	Design and Implementation of a GALS Adapter for ANoC Based Architectures.	ASYNC	2009	DBLP DOI BibTeX RDF
20	Jian Wu, Steve B. Furber, Jim D. Garside	A Programmable Adaptive Router for a GALS Parallel System.	ASYNC	2009	DBLP DOI BibTeX RDF
20	Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli	sFPGA2 - A scalable GALS FPGA architecture and design methodology.	FPL	2009	DBLP DOI BibTeX RDF
20	Xin Fan 0003, Milos Krstic, Eckhard Grass	Analysis and optimization of pausible clocking based GALS design.	ICCD	2009	DBLP DOI BibTeX RDF
20	Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas	A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors.	ISCAS	2009	DBLP DOI BibTeX RDF
20	Xuguang Guan, Duan Zhou, Yintang Yang, Zhangming Zhu	A GALS Delay-insensitive Self-timed Wrapper for Network on Chips.	PACCS	2009	DBLP DOI BibTeX RDF
20	Xuguang Guan, Duan Zhou, Dan Wang, Yintang Yang, Zhangming Zhu	A Novel GALS Single-Track Protocol Asynchronous Communication Circuits.	PACCS	2009	DBLP DOI BibTeX RDF
20	Ning Wu, Fen Ge, Fei Wu	Design of a GALS Wrapper for Network on Chip.	CSIE (3)	2009	DBLP DOI BibTeX RDF
20	Linlin Zhang, Virginie Fresse, Anne-Claire Legrand, Mohammed A. S. Khalid	GALS NoC architectures on FPGA dedicated to multispectral image applications.	EUSIPCO	2009	DBLP BibTeX RDF
20	Abbas Sheibanyrad, Alain Greiner	Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures.	Integr.	2008	DBLP DOI BibTeX RDF
20	Myeong-Hoon Oh, Seongwoon Kim	Low Static Powered Asynchronous Data Transfer for GALS System.	IEICE Trans. Inf. Syst.	2008	DBLP DOI BibTeX RDF
20	Javier D. Garcia-Lasheras	Efficient implementation of GALS systems over commercial synchronous FPGAs: a new approach	CoRR	2008	DBLP BibTeX RDF
20	Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans	Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques.	ISVLSI	2008	DBLP DOI BibTeX RDF
20	Shufan Yang, Steve B. Furber, Yebin Shi, Luis A. Plana	An admission control system for QoS provision on a best-effort GALS interconnect.	ACSD	2008	DBLP DOI BibTeX RDF
20	Avinash Malik, Zoran Salcic, Partha S. Roop	Tandem virtual machine - An efficient execution platform for GALS language SystemJ.	ACSAC	2008	DBLP DOI BibTeX RDF
20	Syed Suhaib, Bijoy Antony Jose, Sandeep K. Shukla, Deepak Mathaikutty	Formal Transformation of a KPN Specification to a GALS Implementation.	FDL	2008	DBLP DOI BibTeX RDF
20	Niranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam	Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures.	ISLPED	2008	DBLP DOI BibTeX RDF
20	Heikki Kariniemi, Jari Nurmi	Micronmesh for fault-tolerant GALS Multiprocessors on FPGA.	SoC	2008	DBLP DOI BibTeX RDF
20	JunBok You, Yang Xu 0036, Hosuk Han, Kenneth S. Stevens	Performance Evaluation of Elastic GALS Interfaces and Network Fabric.	FMGALS@MEMOCODE	2007	DBLP DOI BibTeX RDF
20	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla	Dataflow Architectures for GALS.	FMGALS@MEMOCODE	2007	DBLP DOI BibTeX RDF
20	Sohini Dasgupta, Alex Yakovle	Comparative analysis of GALS clocking schemes.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
20	Tejpal Singh, Alexander Taubin	A Highly Scalable GALS Crossbar Using Token Ring Arbitration.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	crossbar design, scalability, latency, arbitration, token rings
20	Ivan Miro Panades, Alain Greiner	Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures.	NOCS	2007	DBLP DOI BibTeX RDF
20	Abbas Sheibanyrad, Alain Greiner	Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures.	ESA	2007	DBLP BibTeX RDF
20	Samuel Evain, Jean-Philippe Diguet, Dominique Houzet	NoC Design Flow for TDMA and QoS Management in a GALS Context.	EURASIP J. Embed. Syst.	2006	DBLP DOI BibTeX RDF
20	Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad	A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach.	Nano-Net	2006	DBLP DOI BibTeX RDF
20	Giuseppe Campobello, Marco Castano, Carmine Ciofi, Daniele Mangano	GALS networks on chip: a new solution for asynchronous delay-insensitive links.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
20	Zhiyi Yu, Bevan M. Baas	Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles.	ICCD	2006	DBLP DOI BibTeX RDF
20	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla	A Trace Based Framework for Validation of SoC Designs with GALS Systems.	SoCC	2006	DBLP DOI BibTeX RDF
20	Sohini Dasgupta, Alex Yakovlev	Modeling And Performance Analysis of GALS architectures.	SoC	2006	DBLP DOI BibTeX RDF
20	Frank Kagan Gürkaynak	GALS system design: side channel attack secure cryptographic accelerators.		2006	RDF
20	Frederic Doucet, Massimiliano Menarini, Ingolf H. Krüger, Rajesh K. Gupta 0001, Jean-Pierre Talpin	A Verification Approach for GALS Integration of Synchronous Components.	FMGALS@MEMOCODE	2005	DBLP DOI BibTeX RDF
20	Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner	Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC.	FMGALS@MEMOCODE	2005	DBLP DOI BibTeX RDF
20	David S. Bormann	GALS Test Chip on 130nm Process.	FMGALS@MEMOCODE	2005	DBLP DOI BibTeX RDF
20	Koushik Niyogi, Diana Marculescu	Speed and voltage selection for GALS systems based on voltage/frequency islands.	ASP-DAC	2005	DBLP DOI BibTeX RDF
20	Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin	GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips.	FPL	2005	DBLP DOI BibTeX RDF
20	Yongkang Zhu, David H. Albonesi, Alper Buyuktosunoglu	A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity.	ISPASS	2005	DBLP DOI BibTeX RDF
20	Arun Vijayaraghavan, M. Kannan, R. Seshasayanan	Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency.	CDES	2005	DBLP BibTeX RDF
20	Koushik Niyogi, Diana Marculescu	System level power and performance modeling of GALS point-to-point communication interfaces.	ISLPED	2005	DBLP DOI BibTeX RDF	mixed clock FIFO, pausible clock, power modeling, globally asynchronous locally synchronous
20	Tobias Bjerregaard, Shankar Mahadevan, Rasmus Grøndahl Olsen, Jens Sparsø	An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip.	SoC	2005	DBLP DOI BibTeX RDF
20	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards	Adding Testability to an Asynchronous Interconnect for GALS SoC.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
20	Scott F. Smith 0002	Performance of a GALS Single-Chip Multiprocessor.	PDPTA	2004	DBLP BibTeX RDF
20	Shengxian Zhuang, Weidong Li, Jonas Carlsson, Kent Palmkvist, Lars Wanhammar	Asynchronous data communication with low power for GALS systems.	ICECS	2002	DBLP DOI BibTeX RDF
20	Chong H. Lee, Douglas V. Hall, Marek A. Perkowski, David S. Jun	Self-repairable GALs.	J. Syst. Archit.	2001	DBLP DOI BibTeX RDF
20	Greg Garvey, Brenda Laurel, Rob Tow, Joan I. Staveley, Allucquère Rosanne Stone	Grids, guys and gals: are you oppressed by the Cartesian coordinate system? (panel session).	SIGGRAPH	1995	DBLP DOI BibTeX RDF
19	Daniel Gebhardt, JunBok You, Kenneth S. Stevens	Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs.	NOCS	2010	DBLP DOI BibTeX RDF	network, CAD, SoC, topology, asynchronous, floorplan, router, EDA, NoC, GALS
19	Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi	Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs.	NOCS	2010	DBLP DOI BibTeX RDF	asynchronous interconnect, NoC, GALS, on-chip networks
19	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das	Coordinated power management of voltage islands in CMPs.	SIGMETRICS	2010	DBLP DOI BibTeX RDF	chip multiprocessors (CMP), control theory, GALs, DVFs
19	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs)
19	Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area.	ReConFig	2009	DBLP DOI BibTeX RDF	floating point hardware, GALS design, FPGA, prototyping, embedded processor
19	Dumitru Potop-Butucaru, Robert de Simone, Yves Sorel, Jean-Pierre Talpin	From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations.	ACSD	2009	DBLP DOI BibTeX RDF	synchronous specification, asynchronous implementation, weak endochrony, GALS
19	Josefa Díaz, José Ignacio Hidalgo, Francisco Fernández 0001, Oscar Garnica, Sonia López	Improving SMT performance: an application of genetic algorithms to configure resizable caches.	GECCO (Companion)	2009	DBLP DOI BibTeX RDF	reconfigurable caches, genetic algorithms, optimization, caches memories, simultaneous multithreading, gals, adaptive caches
19	Emre Tuncer, Jordi Cortadella, Luciano Lavagno	Enabling adaptability through elastic clocks.	DAC	2009	DBLP DOI BibTeX RDF	low power design, GALS, desynchronization, adaptive voltage scaling
19	Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli	Composing heterogeneous reactive systems.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	correct-by-construction design, reactive systems, Compositionality, models of computation, GALS
19	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.	NOCS	2008	DBLP DOI BibTeX RDF	NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
19	Luis A. Plana, John Bainbridge, Steve B. Furber, Sean Salisbury, Yebin Shi, Jian Wu	An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.	NOCS	2008	DBLP DOI BibTeX RDF	Synchonizer, source-address routing, GALS, Bandwidth aggregation
19	Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung	AsAP: A Fine-Grained Many-Core Platform for DSP Applications.	IEEE Micro	2007	DBLP DOI BibTeX RDF	MIMD processors, GALS networking, embedded systems, multiprocessors, digital signal processing, microarchitecture, special-purpose and application-based systems
19	Dumitru Potop-Butucaru, Robert de Simone, Yves Sorel	Necessary and sufficient conditions for deterministic desynchronization.	EMSOFT	2007	DBLP DOI BibTeX RDF	endochrony, execution machine, reaction to signal absence, correctness, determinism, GALS, desynchronization, kahn process network
19	Jean-Pierre Talpin, Paul Le Guernic	An algebraic theory for behavioral modeling and protocol synthesis in system design.	Formal Methods Syst. Des.	2006	DBLP DOI BibTeX RDF	GALS design, Process algebra, Synchrony, Compositional modeling
19	Tobias Bjerregaard, Shankar Mahadevan	A survey of research and practices of Network-on-chip.	ACM Comput. Surv.	2006	DBLP DOI BibTeX RDF	Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions
19	Marco Zennaro, Raja Sengupta	Distributing synchronous programs using bounded queues.	EMSOFT	2005	DBLP DOI BibTeX RDF	distributed synchronous programs, globally asynchronous locally synchronous architecture, GALS, Simulink
19	Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli	Tag machines.	EMSOFT	2005	DBLP DOI BibTeX RDF	distributed deployment, heterogeneous reactive systems, GALS, tagged systems