Search results for "RISC"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Seon Ha, Minsang Yu, Hyungon Moon, Jongeun Lee	Kernel Code Integrity Protection at the Physical Address Level on RISC-V.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Ruoshi Li, Ping Peng, Zhiyuan Shao, Hai Jin 0001, Ran Zheng	Evaluating RISC-V Vector Instruction Set Architecture Extension with Computer Vision Workloads.	J. Comput. Sci. Technol.	2023	DBLP DOI BibTeX RDF
13	Sankatali Venkateswarlu, Subrat Mishra, Herman Oprins, Bjorn Vermeersch, Moritz Brunion, Jun-Han Han, Mircea R. Stan, Dwaipayan Biswas, Pieter Weckx, Francky Catthoor	Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
13	Bruno Sá, Luca Valente, José Martins, Davide Rossi, Luca Benini, Sandro Pinto 0001	CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
13	Shaopu Han, Yanfeng Jiang	RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
13	Zahra Azad, Guowei Yang, Rashmi Agrawal 0001, Daniel Petrisko, Michael Bedford Taylor, Ajay Joshi	RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
13	Demyana Emil, Mohammed Hamdy, Gihan Nagib	Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processor.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
13	Manolis Marazakis, Stelios Louloudakis	RISER: The First All-European RISC-V Cloud Server Infrastructure.	ERCIM News	2023	DBLP BibTeX RDF
13	Satyam Shukla, Utkarsh, Md Azam, Kailash Chandra Ray	An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
13	Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini	Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini	Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Xin Zheng 0001, Junwei Wu, Xian Lin, Huaien Gao, Shuting Cai, Xiaoming Xiong	Hardware/Software Co-Design of Cryptographic SoC Based on RISC-V Virtual Prototype.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro	RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
13	Alban Gruin, Thomas Carle, Christine Rochange, Hugues Cassé, Pascal Sainrat	MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
13	Thai-Ha Tran, Ba-Anh Dao, Trong-Thuc Hoang, Van-Phuc Hoang, Cong-Kha Pham	Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
13	Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham	A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment.	Comput. Electr. Eng.	2023	DBLP DOI BibTeX RDF
13	Mate Kovac, Leon Dragic, Branimir Malnar, Francesco Minervini, Oscar Palomar, Carlos Rojas, Mauro Olivieri, Josip Knezovic, Mario Kovac	FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
13	Loo Tung Lun, Mohamad Khairi Ishak, Khalid Ammar	Design and implementation of secure boot architecture on RISC-V using FPGA.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
13	Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre	Experimental EMFI detection on a RISC-V core using the Trace Verifier solution.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
13	Stavros Kalapothas, Manolis Galetakis, Georgios Flamis, Fotis C. Plessas, Paris Kitsos	A Survey on RISC-V-Based Machine Learning Ecosystem.	Inf.	2023	DBLP DOI BibTeX RDF
13	Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou 0001, Bei Yu 0001	McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
13	Sebin Shaji Philip, Roberto Passerone, Kasim Sinan Yildirim, Davide Brunelli	Intermittent Computing Emulation of Ultralow-Power Processors: Evaluation of Backup Strategies for RISC-V.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
13	Guilherme Álvaro R. M. Esmeraldo, Robson Gonçalves Fechine Feitosa, Edna Natividade da Silva Barros, Eduardo Carlos P. da S. Proto, Harley Macedo de Mello, Edson Barbosa Lisboa, Esdras L. Bispo Jr., Gustavo Augusto Lima de Campos	Uma Abordagem para Ensino-Aprendizado de Projetos de Sistemas Computacionais com Utilização do Simulador CompSim com Suporte à Arquitetura RISC-V.	Revista Brasileira de Informática na Educ.	2023	DBLP DOI BibTeX RDF
13	Hai Jin 0001, Zhuo He, Weizhong Qiang	SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V.	ACM Trans. Archit. Code Optim.	2023	DBLP DOI BibTeX RDF
13	Francesco Minervini, Oscar Palomar, Osman S. Unsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González 0004, Jonnatan Mendoza, Iván Vargas, César Hernández, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrián Cristal	Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.	ACM Trans. Archit. Code Optim.	2023	DBLP DOI BibTeX RDF
13	Tailin Liang, Lei Wang, Shaobo Shi, John Glossner, Xiaotong Zhang 0002	TCX: A RISC Style Tensor Computing Extension and a Programmable Tensor Processor.	ACM Trans. Embed. Comput. Syst.	2023	DBLP DOI BibTeX RDF
13	Qiang Li, Jun Tao 0001, Jun Han 0003	SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Chun-Chieh Yang, Yi-Ru Chen, Hui-Hsin Liao, Yuan-Ming Chang, Jenq-Kuen Lee	Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
13	Ravi Sahita, Atish Patra, Vedvyas Shanbhogue, Samuel Ortiz, Andrew Bresticker, Dylan Reid, Atul Khare, Rajnesh Kanwal	CoVE: Towards Confidential Computing on RISC-V Platforms.	CoRR	2023	DBLP DOI BibTeX RDF
13	Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini	ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.	CoRR	2023	DBLP DOI BibTeX RDF
13	Georg Rutishauser, Robin Hunziker, Alfio Di Mauro, Sizhen Bian, Luca Benini, Michele Magno	ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control Applications.	CoRR	2023	DBLP DOI BibTeX RDF
13	Gianluca Mittone, Nicolò Tonci, Robert Birke, Iacopo Colonnelli, Doriana Medic, Andrea Bartolini, Roberto Esposito, Emanuele Parisi, Francesco Beneventi, Mirko Polato, Massimo Torquati, Luca Benini, Marco Aldinucci	Experimenting with Emerging ARM and RISC-V Systems for Decentralised Machine Learning.	CoRR	2023	DBLP DOI BibTeX RDF
13	Takahiro Fukumori, Taito Ishida, Yoichi Yamashita	RISC: A Corpus for Shout Type Classification and Shout Intensity Prediction.	CoRR	2023	DBLP DOI BibTeX RDF
13	Michael Rogenmoser, Luca Benini	Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm.	CoRR	2023	DBLP DOI BibTeX RDF
13	Bruno Sá, Luca Valente, José Martins, Davide Rossi, Luca Benini, Sandro Pinto 0001	CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration.	CoRR	2023	DBLP DOI BibTeX RDF
13	Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti 0001	DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training.	CoRR	2023	DBLP DOI BibTeX RDF
13	Sonia Rani Gupta, Nikela Papadopoulou, Miquel Pericàs	Challenges and Opportunities in the Co-design of Convolutions and RISC-V Vector Processors.	CoRR	2023	DBLP DOI BibTeX RDF
13	Bryce Adern, Zachary Susskind, Brendan Sweeney	Adding Explicit Load-Acquire and Store-Release Instructions to the RISC-V ISA.	CoRR	2023	DBLP DOI BibTeX RDF
13	Geraldine Shirley Nicholas, Dhruvakumar Vikas Aklekar, Bhavin Thakar, Fareena Saqib	Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V.	CoRR	2023	DBLP DOI BibTeX RDF
13	Gonzalo Gomez-Sanchez, Aaron Call, Xavier Teruel, Lorena Alonso, Ignasi Moran, Miguel Angel Perez, David Torrents, Josep Lluís Berral	Challenges and Opportunities for RISC-V Architectures towards Genomics-based Workloads.	CoRR	2023	DBLP DOI BibTeX RDF
13	Valentin Le Fèvre, Marc Casas	Optimization of SpGEMM with Risc-V vector instructions.	CoRR	2023	DBLP DOI BibTeX RDF
13	Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria	Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference.	CoRR	2023	DBLP DOI BibTeX RDF
13	Jonas Kühne, Michele Magno, Luca Benini	Parallelizing Optical Flow Estimation on an Ultra-Low Power RISC-V Cluster for Nano-UAV Navigation.	CoRR	2023	DBLP DOI BibTeX RDF
13	MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference.	CoRR	2023	DBLP DOI BibTeX RDF
13	Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti 0001, Davide Rossi	A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks.	CoRR	2023	DBLP DOI BibTeX RDF
13	Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini	Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.	CoRR	2023	DBLP DOI BibTeX RDF
13	Valentin Volokitin, Evgeny Kozinov, Valentina Kustikova, Alexey Liniov, Iosif B. Meyerov	Case Study for Running Memory-Bound Kernels on RISC-V CPUs.	CoRR	2023	DBLP DOI BibTeX RDF
13	Vasileios Titopoulos, K. Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos	IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications.	CoRR	2023	DBLP DOI BibTeX RDF
13	Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David	BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU.	CoRR	2023	DBLP DOI BibTeX RDF
13	Jia-Hui Su, Chen-Hua Lu, Jenq-Kuen Lee, Andrea Coluccio, Fabrizio Riente, Marco Vacca, Marco Ottavi, Kuan-Hsun Chen	Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures.	CoRR	2023	DBLP DOI BibTeX RDF
13	Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta, Filippo Mantovani	Short reasons for long vectors in HPC CPUs: a study based on RISC-V.	CoRR	2023	DBLP DOI BibTeX RDF
13	Ju-Hung Li, Jhih-Kuan Lin, Yung-Cheng Su, Chi-Wei Chu, Lai-Tak Kuok, Hung-Ming Lai, Chao-Lin Lee, Jenq-Kuen Lee	SIMD Everywhere Optimization from ARM NEON to RISC-V Vector Extensions.	CoRR	2023	DBLP DOI BibTeX RDF
13	Valentin Volokitin, Evgenii Vasiliev, Evgeny Kozinov, Valentina Kustikova, Alexei Liniov, Yury Rodimkov, Alexander Sysoyev, Iosif B. Meyerov	Improved vectorization of OpenCV algorithms for RISC-V CPUs.	CoRR	2023	DBLP DOI BibTeX RDF
13	Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini	Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.	CoRR	2023	DBLP DOI BibTeX RDF
13	Zahra Azad, Guowei Yang, Rashmi Agrawal, Daniel Petrisko, Michael B. Taylor, Ajay Joshi	RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption.	CoRR	2023	DBLP DOI BibTeX RDF
13	Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino	Towards a RISC-V Open Platform for Next-generation Automotive ECUs.	CoRR	2023	DBLP DOI BibTeX RDF
13	Longwei Huang, Chao Fang, Qiong Li, Jun Lin 0001, Zhongfeng Wang 0001	A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge.	CoRR	2023	DBLP DOI BibTeX RDF
13	Michael Rogenmoser, Yvan Tortorella, Davide Rossi, Francesco Conti 0001, Luca Benini	Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space.	CoRR	2023	DBLP DOI BibTeX RDF
13	Marti Alonso, David Andreu 0003, Ramon Canal, Stefano Di Carlo, Cristiano Pegoraro Chenet, Juanjo Costa, Andreu Girones, Dimitris Gizopoulos, Vasileios Karakostas, Beatriz Otero, George Papadimitriou 0001, Eva Rodríguez, Alessandro Savino	Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective.	CoRR	2023	DBLP DOI BibTeX RDF
13	Joseph K. L. Lee, Maurice Jamieson, Nick Brown 0002	Backporting RISC-V Vector assembly.	CoRR	2023	DBLP DOI BibTeX RDF
13	Siddesh D. Patil, Premraj V. Jadhav, Sidharth Sankhe	32-Bit RISC-V CPU Core on Logisim.	CoRR	2023	DBLP DOI BibTeX RDF
13	Jordan Morris, Ashur Rafiev, Graeme M. Bragg, Mark Vousden, David B. Thomas, Alex Yakovlev, Andrew Brown	An Event-Driven Approach To Genotype Imputation On A Custom RISC-V FPGA Cluster.	CoRR	2023	DBLP DOI BibTeX RDF
13	David Beauchemin, Richard Khoury	RISC: Generating Realistic Synthetic Bilingual Insurance Contract.	CoRR	2023	DBLP DOI BibTeX RDF
13	Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Giorgos Ieronymakis, Nikos Dimou, Vassilis Papaefstathiou, Jesús Labarta	Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study.	CoRR	2023	DBLP DOI BibTeX RDF
13	Nick Brown 0002, Maurice Jamieson, Joseph K. L. Lee	Experiences of running an HPC RISC-V testbed.	CoRR	2023	DBLP DOI BibTeX RDF
13	Francesco Conti 0001, Gianna Paulin, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing.	CoRR	2023	DBLP DOI BibTeX RDF
13	Federico Rossi 0003, Marco Cococcioni, Roger Ferrer Ibáñez, Jesús Labarta, Filippo Mantovani, Marc Casas, Emanuele Ruffaldi, Sergio Saponara	Compressed Real Numbers for AI: a case-study using a RISC-V CPU.	CoRR	2023	DBLP DOI BibTeX RDF
13	Alexander Walsemann, Michael Karagounis, Alexander Stanitzki, Dietmar Tutsch	STRV - A radiation hard RISC-V microprocessor for high-energy physics applications.	CoRR	2023	DBLP DOI BibTeX RDF
13	Yonghae Kim, Anurag Kar, Jaewon Lee, Jaekyu Lee, Hyesoon Kim	RV-CURE: A RISC-V Capability Architecture for Full Memory Safety.	CoRR	2023	DBLP DOI BibTeX RDF
13	Marwan Shaban, Adam J. Rocke	Optimized Real-Time Assembly in a RISC Simulator.	CoRR	2023	DBLP DOI BibTeX RDF
13	Alex Saveau	Branch Prediction in Hardcaml for a RISC-V 32im CPU.	CoRR	2023	DBLP DOI BibTeX RDF
13	Joseph K. L. Lee, Maurice Jamieson, Nick Brown 0002, Ricardo Jesus	Test-driving RISC-V Vector hardware for HPC.	CoRR	2023	DBLP DOI BibTeX RDF
13	Jan Wichelmann, Christopher Peredy, Florian Sieck, Anna Pätschke, Thomas Eisenbarth 0001	MAMBO-V: Dynamic Side-Channel Leakage Analysis on RISC-V.	CoRR	2023	DBLP DOI BibTeX RDF
13	Eymen Ünay, Bora Inan, Emrecan Yigit	Supporting Custom Instructions with the LLVM Compiler for RISC-V Processor.	CoRR	2023	DBLP DOI BibTeX RDF
13	Robert Balas, Alessandro Ottaviano, Luca Benini	CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers.	CoRR	2023	DBLP DOI BibTeX RDF
13	Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini	Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency.	CoRR	2023	DBLP DOI BibTeX RDF
13	Arpan Suravi Prasad, Moritz Scherer, Francesco Conti 0001, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini	Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine.	CoRR	2023	DBLP DOI BibTeX RDF
13	Aggelos Arelakis, José-María Arnau, Josep Lluis Berral, Aaron Call, Ramon Canal, Stefano Di Carlo, Juan José Costa, Dimitris Gizopoulos, Vasileios Karakostas, Francesco Lubrano, Konstantinos Nikas, Yiannis Nikolakopoulos, Beatriz Otero, George Papadimitriou 0001, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Daniel Raho, Alvise Rigo, Eva Rodríguez, Alessandro Savino, Alberto Scionti, Nikolaos Tampouratzis, Antonio J. Torregrosa	Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services.	CoRR	2023	DBLP DOI BibTeX RDF
13	Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr 0001, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich	A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI.	CoRR	2023	DBLP DOI BibTeX RDF
13	Patrick Diehl, Gregor Daiß, Steven R. Brandt, Alireza Kheirkhahan, Hartmut Kaiser, Christopher Taylor, John Leidel	Evaluating HPX and Kokkos on RISC-V using an Astrophysics Application Octo-Tiger.	CoRR	2023	DBLP DOI BibTeX RDF
13	Ferdinand Gruber, Maximilian Bandle, Alexis Engelke, Thomas Neumann 0001, Jana Giceva	Bringing Compiling Databases to RISC Architectures. (PDF / PS)	Proc. VLDB Endow.	2023	DBLP DOI BibTeX RDF
13	Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Claudio Monteleone	Extending the NOEL-V Platform with a RISC-V Vector Processor for Space Applications.	J. Aerosp. Inf. Syst.	2023	DBLP DOI BibTeX RDF
13	Constantino Gómez, Filippo Mantovani, Erich Focht, Marc Casas	HPCG on long-vector architectures: Evaluation and optimization on NEC SX-Aurora and RISC-V.	Future Gener. Comput. Syst.	2023	DBLP DOI BibTeX RDF
13	Hao Cheng 0009, Johann Großschädl, Ben Marshall, Dan Page, Thinh Hung Pham	RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2023	DBLP DOI BibTeX RDF
13	Konstantina Miteloudi, Joppe W. Bos, Olivier Bronchain, Björn Fay, Joost Renes	PQ.V.ALU.E: Post-Quantum RISC-V Custom ALU Extensions on Dilithium and Kyber.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
13	Davide Bove, Julian Funk	Basic secure services for standard RISC-V architectures.	Comput. Secur.	2023	DBLP DOI BibTeX RDF
13	Pengfei Guo, Yingjian Yan, Junjie Wang, Jingxin Zhong, Yanjiang Liu, Jinsong Xu	Towards a metrics suite for evaluating cache side-channel vulnerability: Case studies on an open-source RISC-V processor.	Comput. Secur.	2023	DBLP DOI BibTeX RDF
13	Víctor Jiménez, Mario Rodríguez, Marc Domínguez, Josep Sans, Ivan Diaz, Luca Valente, Vito Luca Guglielmi, Josue V. Quiroga, R. Ignacio Genovese, Nehir Sönmez, Oscar Palomar, Miquel Moretó	Functional Verification of a RISC-V Vector Accelerator.	IEEE Des. Test	2023	DBLP DOI BibTeX RDF
13	Jihye Lee, Whijin Kim, Ji-Hoon Kim	A Programmable Crypto-Processor for National Institute of Standards and Technology Post-Quantum Cryptography Standardization Based on the RISC-V Architecture.	Sensors	2023	DBLP DOI BibTeX RDF
13	Ingo Hoyer, Alexander Utz, André Lüdecke, Holger Kappert, Maurice Rohr, Christoph Hoog Antink, Karsten Seidl	Design of Hardware Accelerators for Optimized and Quantized Neural Networks to Detect Atrial Fibrillation in Patch ECG Device with RISC-V.	Sensors	2023	DBLP DOI BibTeX RDF
13	Chang Liu, Yan-Jun Wu, Jing-Zheng Wu, Chen Zhao	A buffer overflow detection and defense method based on RISC-V instruction set extension.	Cybersecur.	2023	DBLP DOI BibTeX RDF
13	Bo Zhao, Minghui Yin, Weihua Zhang, Hongwei Liu, Zhiqiang Li	Design of a variable precision CORDIC coprocessor for RISC-V architecture based on FinFET process.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
13	Niraj N. Sharma, Riya Jain, Mohana Madhumita Pokkuluri, Sachin B. Patkar, Rainer Leupers, Rishiyur S. Nikhil, Farhad Merchant	CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism.	J. Syst. Archit.	2023	DBLP DOI BibTeX RDF
13	Veysel Harun Sahin	Turna: a control flow graph reconstruction tool for RISC-V architecture.	Computing	2023	DBLP DOI BibTeX RDF
13	Marco Angioli, Marcello Barbirotta, Antonio Mastrandrea, Saeid Jamili, Mauro Olivieri	Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor.	PRIME	2023	DBLP DOI BibTeX RDF
13	Nithin Ravani Nanjundaswamy, Gregor Nitsche, Frank Poppen, Kim Grüttner	RISC-V Timing-Instructions for Open Time-Triggered Architectures.	DSN-W	2023	DBLP DOI BibTeX RDF
13	Pegdwende Romaric Nikiema, Angeliki Kritikakou, Marcello Traiola, Olivier Sentieys	Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors.	DSN-S	2023	DBLP DOI BibTeX RDF
13	Julian Haase, Muhammad Ali 0010, Diana Göhringer	Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to Simulation and Modeling.	SAMOS	2023	DBLP DOI BibTeX RDF
13	Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini	Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.	SAMOS	2023	DBLP DOI BibTeX RDF
13	William Fornaciari, Federico Reghenzani, Federico Terraneo, Davide Baroffio, Cecilia Metra, Martin Omaña 0001, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Robert Birke, Iacopo Colonnelli, Gianluca Mittone, Marco Aldinucci, Gabriele Mencagli, Francesco Iannone, Filippo Palombi, Giuseppe Zummo, Daniele Cesarini, Federico Tesser	RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters.	SAMOS	2023	DBLP DOI BibTeX RDF