Search results for "SEU"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Karine Castellani-Coulié, Jean-Michel Portal, Gilles Micolau, Hassen Aziza	Analysis of SEU parameters for the study of SRAM cells reliability under radiation.	LATW	2011	DBLP DOI BibTeX RDF
19	Gilles Micolau, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal	Impact of SEU configurations on a SRAM cell response at circuit level.	LATW	2011	DBLP DOI BibTeX RDF
19	Xinrui Zhang, Liguang Chen, Liyun Wang, Jian Wang 0036, Jinmei Lai	The design and verification of SEU-hardened configurable DFF.	ASICON	2011	DBLP DOI BibTeX RDF
19	Riadul Islam, Seyed Ebrahim Esmaeili, Thouhidul Islam	A high performance clock precharge SEU hardened flip-flop.	ASICON	2011	DBLP DOI BibTeX RDF
19	Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita	SEU tolerant SRAM cell.	ISQED	2011	DBLP DOI BibTeX RDF
19	Flávia Goulart Mota Garcia Rosa	A disseminação da produção científica da Universidade Federal da Bahia através da implantação do seu repositório institucional: uma política de acesso aberto.		2011	RDF
19	Kazuteru Namba, Takashi Ikeda, Hideo Ito	Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
19	Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera	An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity.	IEICE Trans. Electron.	2010	DBLP DOI BibTeX RDF
19	Uros Legat, Anton Biasizzo, Franc Novak	Automated SEU fault emulation using partial FPGA reconfiguration.	DDECS	2010	DBLP DOI BibTeX RDF
19	Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita	SEU tolerant SRAM for FPGA applications.	FPT	2010	DBLP DOI BibTeX RDF
19	Sohan Purohit, David Harrington, Martin Margala	An area efficient design methodology for SEU tolerant digital circuits.	ISCAS	2010	DBLP DOI BibTeX RDF
19	Sebastià A. Bota, Gabriel Torrens, Bartomeu Alorda, Jaume Verd, Jaume Segura 0001	Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories.	IOLTS	2010	DBLP DOI BibTeX RDF
19	Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato	A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation.	SoCC	2010	DBLP DOI BibTeX RDF
19	Vladimir Trujillo-Olaya, John M. Espinosa-Duran, Jaime Velasco-Medina, Raoul Velazco	Dependability validation of a cryptoprocessor to SEU effects.	LATW	2010	DBLP DOI BibTeX RDF
19	Srikanth V. Devarapalli, Payman Zarkesh-Ha, Steven C. Suddarth	SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements.	DFT	2010	DBLP DOI BibTeX RDF
19	Jong Kiun Kiet, Tan Jun Pin, Ang Boon Jin	A fast CRAM SEU error detection scheme for FPGAs.	APCCAS	2010	DBLP DOI BibTeX RDF
19	Luiz Carlos Pinto da Costa Júnior	Ações coletivas com mídias livres: uma interpretação gramsciana de seu programa político.		2010	RDF
19	Shahin Golshan, Eli Bozorgzadeh	SEU-aware resource binding for modular redundancy based designs on FPGAs.	DATE	2009	DBLP DOI BibTeX RDF
19	Alireza Rohani, Hamid R. Zarandi	A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs.	ReConFig	2009	DBLP DOI BibTeX RDF	Dependability, FPGA-Test
19	Xabier Iturbe, Mikel Azkarate-askasua, Imanol Martinez, Jon Pérez 0001, Armando Astarloa	A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
19	Niccolò Battezzati, Filomena Decuzzi, Massimo Violante, Michel Briet	Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs.	IOLTS	2009	DBLP DOI BibTeX RDF
19	Guillaume Hubert, Raoul Velazco, Paul Peronnard	A generic platform for remote accelerated tests and high altitude SEU experiments on advanced ICs: Correlation with MUSCA SEP3 calculations.	IOLTS	2009	DBLP DOI BibTeX RDF
19	Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou	SRAM cell design using tri-state devices for SEU protection.	IOLTS	2009	DBLP DOI BibTeX RDF
19		Selective Triple Modular Redundancy for Single Event Upset (SEU) Mitigation.	AHS	2009	DBLP DOI BibTeX RDF
19	Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena, B. Lestriez, Luis Berrojo	Study of SEU effects in a Turbo Decoder Bit Error Rate.	LATW	2009	DBLP DOI BibTeX RDF
19	Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano	Error Correction Codes for SEU and SEFI Tolerant Memory Systems.	DFT	2009	DBLP DOI BibTeX RDF
19	Bradley F. Dutton, Mustafa Ali, Charles E. Stroud, John Sunwoo	Embedded Processor Based Fault Injection and SEU Emulation for FPGAs.	ESA	2009	DBLP BibTeX RDF
19	Bradley F. Dutton, Charles E. Stroud	Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs.	ESA	2009	DBLP BibTeX RDF
19	Eliane Elias Ferreira dos Santos	Estrutura Cognitiva para Tecnologias Educacionais Construtivistas ECoTEC e seu Instrumento de Otimização Web-ECoTEC.		2009	RDF
19	Alireza Ejlali, Seyed Ghassem Miremadi	Error propagation analysis using FPGA-based SEU-fault injection.	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
19	Toshimasa Funaki, Toshinori Sato	Formulating MITF for a Multicore Processor with SEU Tolerance.	DSD	2008	DBLP DOI BibTeX RDF
19	Jirí Kvasnicka, Pavel Kubalík, Hana Kubátová	Experimental SEU Impact on Digital Design Implemented in FPGAs.	DSD	2008	DBLP DOI BibTeX RDF
19	Costas Argyrides, Fabian Vargas 0001, Marlon Moraes, Dhiraj K. Pradhan	Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement.	IOLTS	2008	DBLP DOI BibTeX RDF
19	Shi-Jie Wen, Dan Alexandrescu, Renaud Perez	A Systematical Method of Quantifying SEU FIT.	IOLTS	2008	DBLP DOI BibTeX RDF
19	Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou	SRAM Cell Design Protected from SEU Upsets.	IOLTS	2008	DBLP DOI BibTeX RDF
19	Hamid R. Zarandi, Seyed Ghassem Miremadi	A SEU-protected cache memory-based on variable associativity of sets.	Reliab. Eng. Syst. Saf.	2007	DBLP DOI BibTeX RDF
19	Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego	An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.	DDECS	2007	DBLP DOI BibTeX RDF
19	Cristiana Bolchini, Fabio Salice, Marco D. Santambrogio	Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs.	ERSA	2007	DBLP BibTeX RDF
19	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan	Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
19	Drew C. Ness, Christian J. Hescott, David J. Lilja	Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations.	NANOARCH	2007	DBLP DOI BibTeX RDF
19	Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube	A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.	DFT	2007	DBLP DOI BibTeX RDF
19	Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio	TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs.	DFT	2007	DBLP DOI BibTeX RDF
19	Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota	Evaluation of SEU and crosstalk effects in network-on-chip switches.	SBCCI	2006	DBLP DOI BibTeX RDF	network-on-chip, crosstalk, single-event upset
19	T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani	SEU Mitigation Techniques for Microprocessor Control Logic.	EDCC	2006	DBLP DOI BibTeX RDF
19	Maico Cassel, Fernanda Lima Kastensmidt	Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
19	P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis	A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
19	Arthur Pereira Frantz, Fernanda Lima Kastensmidt	SEU Effects Evaluation on a NoC Router Architecture.	LATW	2006	DBLP BibTeX RDF
19	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
19	Michel Pignol	How to Cope with SEU/SET at System Level?.	IOLTS	2005	DBLP DOI BibTeX RDF
19	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	Efficient Estimation of SEU Effects in SRAM-Based FPGAs.	IOLTS	2005	DBLP DOI BibTeX RDF
19	Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert	Evaluation of SET and SEU Effects at Multiple Abstraction Levels.	IOLTS	2005	DBLP DOI BibTeX RDF
19	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF	Complex Logic Blocks, Routing Errors, Vertex Coloring problem, Fault Tolerance, Field Programmable Gate Arrays, Graph Theory, Single Event Upset
19	William Heidergott	SEU tolerant device, circuit and processor design.	DAC	2005	DBLP DOI BibTeX RDF	error detection and correction coding, radiation effects, soft error rate, fault tolerant systems, single event upset, fault masking, temporal redundancy, modular redundancy, fault avoidance
19	Marcelo Magalhães Foohs	Representação gráfica do tempo: efeito de gráficos na compreensão e retenção dos significados do Present Perfect e do seu contraste com o Simple Past.		2005	RDF
19	Romain Desplats, S. Petit, Sana Rezgui, Carl Carmichael, Pascal Fouillat, Dean Lewis	Investigation of SEU sensitivity of Xilinx Virtex II FPGA by pulsed laser fault injections.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
19	Régis Leveugle, Abdelaziz Ammari	Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow.	DATE	2004	DBLP DOI BibTeX RDF
19	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Vijaykrishnan Narayanan	A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.	FPT	2004	DBLP DOI BibTeX RDF
19	Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.	IOLTS	2004	DBLP DOI BibTeX RDF
19	Andrea S. Brogna, Franco Bigongiari, Fabrizio Bertuccelli, Walter Errico, Simone Giovannetti, Egidio Pescari, Roberto Saletti	SEU Protected CPU for Slow Control on Space Vehicles.	DELTA	2004	DBLP DOI BibTeX RDF
19	Angelica Carvalho Di Maio	Geotecnologias digitais no ensino médio: avaliação prática de seu potencial.		2004	RDF
19	Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali	Fault injection into SRAM-based FPGAs for the analysis of SEU effects.	FPT	2003	DBLP DOI BibTeX RDF
19	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi	A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs.	DFT	2003	DBLP DOI BibTeX RDF
19	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
19	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Analysis of SEU Effects in a Pipelined Processor.	IOLTW	2002	DBLP DOI BibTeX RDF
19	Fernanda Lima 0001, Luigi Carro, Raul Velazco, Ricardo Reis 0001	Injecting Multiple Upsets in a SEU tolerant 8051 Micro-controller.	LATW	2002	DBLP BibTeX RDF
19	Ivan de Paúl, Miquel Roca 0001, Oscar Calvo, Raul Velazco	SEU fault injection in simulation environments: example of VHDL configuration on FPGA device.	LATW	2002	DBLP BibTeX RDF
19	Pablo A. Ferreyra, Carlos A. Marqués, Javier P. Gaspar, Raul Velazco, Ricardo T. Ferreyra	SEU-Induced-Fault Detection-Efficiency of a Watch Dog Circuit for a Micro-Satellite on Board Digital Signal Processor System.	LATW	2002	DBLP BibTeX RDF
19	Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	Static Analysis of SEU Effects on Software Applications.	ITC	2002	DBLP DOI BibTeX RDF
19	José A. Soto Mejía	Uma abordagem unificada para modelar processos de Workflow e seu software de suporte.		2002	RDF
19	Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	SEU effect analysis in an open-source router via a distributed fault injection environment.	DATE	2001	DBLP DOI BibTeX RDF
19	Fabian Vargas 0001, Alexandre M. Amory	Circuit Modeling and Fault Injection Approach to Predict SEU Rate and MTTF in Complex Circuits.	LATW	2001	DBLP BibTeX RDF
19	Vincent Pouget, Pascal Fouillat, Dean Lewis, Hervé Lapuyade, L. Sarger, F. M. Roche, S. Duzellier, R. Ecoffet	An Overview of the Applications of a Pulsed Laser System for SEU Testing.	IOLTW	2000	DBLP DOI BibTeX RDF
19	F. L. Vargas, Michael Nicolaidis	SEU-Tolerant SRAM Design Based on Current Monitoring.	FTCS	1994	DBLP DOI BibTeX RDF
19	Luís João de Sousa Cardoso	A União Internacional de Telecomunicações e o Seu Papel na Normalização no Sector das Telecomunicações.	QUATIC	1994	DBLP BibTeX RDF
13	Xin He, Afshin Abdollahi	Cost aware fault tolerant logic synthesis in presence of soft errors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	soft error rate, reliability, linear programming
13	Kuen-Long Leu, Chin-Long Wey, Jwu-E Chen, Yung-Yuan Chen	Robustness investigation of the FlexRay system.	SIES	2009	DBLP DOI BibTeX RDF
13	Chong Zhao, Yi Zhao, Sujit Dey	Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
13	Rajesh Garg, Peng Li 0001, Sunil P. Khatri	Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs).	ISCAS	2008	DBLP DOI BibTeX RDF
13	Mahdi Fazeli, Seyed Ghassem Miremadi	A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET.	DFT	2008	DBLP DOI BibTeX RDF
13	Rui Gong, Kui Dai, Zhiying Wang 0003	Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
13	Juan Antonio Maestro, Pedro Reviriego	Study of the effects of MBUs on the reliability of a 150 nm SRAM device.	DAC	2008	DBLP DOI BibTeX RDF	multiple bit upsets (MBUs), reliability, memory, radiation
13	Han Liang, Piyush Mishra, Kaijie Wu 0001	Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy
13	Sajid Baloch, Tughrul Arslan, Adrian Stoica	Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications.	IPDPS	2007	DBLP DOI BibTeX RDF
13	Yannick Monnet, Marc Renaudin, Régis Leveugle	Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs.	IOLTS	2007	DBLP DOI BibTeX RDF
13	X. Cano, Sebastià A. Bota, Ricardo Graciani Diaz, David Gascon, A. Herms, Albert Comerma, Jaume Segura 0001, Lluís Garrido	Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment.	IOLTS	2007	DBLP DOI BibTeX RDF
13	Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren	Quantitative Analysis of In-Field Defects in Image Sensor Arrays.	DFT	2007	DBLP DOI BibTeX RDF
13	Jorge Luis Lagos-Benites, Davide Appello, Paolo Bernardi, Michelangelo Grosso, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda	An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.	DFT	2007	DBLP DOI BibTeX RDF
13	Avijit Dutta, Nur A. Touba	Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code.	VTS	2007	DBLP DOI BibTeX RDF
13	Luca Sterpone, Massimo Violante	A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	transient fault injection, FPGA, reliability, place and route
13	Luiz Eduardo Cunha Leite, Guido Lemos de Souza Filho, Silvio Romero de Lemos Meira, Patrick Carlos T. de Arújo, Jefferson Ferreira de A. Lima, Sindolfo Miranda Filho	A component model proposal for embedded systems and its use to add reconfiguration capabilities to the FlexTV middleware.	WebMedia	2006	DBLP DOI BibTeX RDF	middleware, component based development, digital television, context representation
13	Alan Silva, Rômulo Silva de Oliveira, Ig Ibert Bittencourt	An environment for supporting automated electronic negotiations using ontologies and production rules.	WebMedia	2006	DBLP DOI BibTeX RDF
13	Américo Talarico Neto, Júnia Coutinho Anacleto Silva, Vânia Paula de Almeida Néris, Muriel de Souza Godoi, Aparecido Fabiano Pinatti de Carvalho	A framework to support the design of learning objects based on the Cog-Learn Pattern Language.	WebMedia	2006	DBLP DOI BibTeX RDF	EAD, cog-learn, cognitor, educação à distância, interação humano-computador, linguagem de padrões, projeto web, SCORM
13	Pavel Kubalík, Radek Dobias, Hana Kubátová	Dependable Design for FPGA Based on Duplex System and Reconfiguration.	DSD	2006	DBLP DOI BibTeX RDF
13	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto	Single-Event Upset Analysis and Protection in High Speed Circuits.	ETS	2006	DBLP DOI BibTeX RDF
13	Sajid Baloch, Tughrul Arslan, Adrian Stoica	An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures.	FPL	2006	DBLP DOI BibTeX RDF
13	Bernhard Fechner	Analysis of checksum-based execution schemes for pipelined processors.	IPDPS	2006	DBLP DOI BibTeX RDF
13	Mihir R. Choudhury, Quming Zhou, Kartik Mohanram	Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques.	ICCAD	2006	DBLP DOI BibTeX RDF
13	Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena	Emulation-based Fault Injection in Circuits with Embedded Memories.	IOLTS	2006	DBLP DOI BibTeX RDF
13	Sajid Baloch, Tughrul Arslan, Adrian Stoica	An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures.	AHS	2006	DBLP DOI BibTeX RDF
13	Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto	Combined software and hardware techniques for the design of reliable IP processors.	DFT	2006	DBLP DOI BibTeX RDF