Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Karine Castellani-Coulié, Jean-Michel Portal, Gilles Micolau, Hassen Aziza |
Analysis of SEU parameters for the study of SRAM cells reliability under radiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 12th Latin American Test Workshop, LATW 2011, Beach of Porto de Galinhas, Brazil, March 27-30, 2011, pp. 1-5, 2011, IEEE, 978-1-4577-1488-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Gilles Micolau, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal |
Impact of SEU configurations on a SRAM cell response at circuit level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 12th Latin American Test Workshop, LATW 2011, Beach of Porto de Galinhas, Brazil, March 27-30, 2011, pp. 1-5, 2011, IEEE, 978-1-4577-1488-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Xinrui Zhang, Liguang Chen, Liyun Wang, Jian Wang 0036, Jinmei Lai |
The design and verification of SEU-hardened configurable DFF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 937-940, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Riadul Islam, Seyed Ebrahim Esmaeili, Thouhidul Islam |
A high performance clock precharge SEU hardened flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 574-577, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita |
SEU tolerant SRAM cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011, pp. 597-602, 2011, IEEE, 978-1-61284-914-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Flávia Goulart Mota Garcia Rosa |
A disseminação da produção científica da Universidade Federal da Bahia através da implantação do seu repositório institucional: uma política de acesso aberto. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2011 |
RDF |
|
19 | Kazuteru Namba, Takashi Ikeda, Hideo Ito |
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(9), pp. 1265-1276, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera |
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 93-C(3), pp. 340-346, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Uros Legat, Anton Biasizzo, Franc Novak |
Automated SEU fault emulation using partial FPGA reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, pp. 24-27, 2010, IEEE Computer Society, 978-1-4244-6612-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita |
SEU tolerant SRAM for FPGA applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China, pp. 491-494, 2010, IEEE, 978-1-4244-8981-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Sohan Purohit, David Harrington, Martin Margala |
An area efficient design methodology for SEU tolerant digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 981-984, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Sebastià A. Bota, Gabriel Torrens, Bartomeu Alorda, Jaume Verd, Jaume Segura 0001 |
Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 5-7 July, 2010, Corfu, Greece, pp. 141-146, 2010, IEEE Computer Society, 978-1-4244-7724-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato |
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings, pp. 248-253, 2010, IEEE, 978-1-4244-6682-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Vladimir Trujillo-Olaya, John M. Espinosa-Duran, Jaime Velasco-Medina, Raoul Velazco |
Dependability validation of a cryptoprocessor to SEU effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 11th Latin American Test Workshop, LATW 2010, Punta del Este, Uruguay, March 28-30, 2010, pp. 1-6, 2010, IEEE, 978-1-4244-7786-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Srikanth V. Devarapalli, Payman Zarkesh-Ha, Steven C. Suddarth |
SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 167-171, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Jong Kiun Kiet, Tan Jun Pin, Ang Boon Jin |
A fast CRAM SEU error detection scheme for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 995-998, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Luiz Carlos Pinto da Costa Júnior |
Ações coletivas com mídias livres: uma interpretação gramsciana de seu programa político. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2010 |
RDF |
|
19 | Shahin Golshan, Eli Bozorgzadeh |
SEU-aware resource binding for modular redundancy based designs on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 1124-1129, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Alireza Rohani, Hamid R. Zarandi |
A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 83-88, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Dependability, FPGA-Test |
19 | Xabier Iturbe, Mikel Azkarate-askasua, Imanol Martinez, Jon Pérez 0001, Armando Astarloa |
A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic, pp. 569-573, 2009, IEEE, 978-1-4244-3892-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Niccolò Battezzati, Filomena Decuzzi, Massimo Violante, Michel Briet |
Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, pp. 89-94, 2009, IEEE Computer Society, 978-1-4244-4596-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Guillaume Hubert, Raoul Velazco, Paul Peronnard |
A generic platform for remote accelerated tests and high altitude SEU experiments on advanced ICs: Correlation with MUSCA SEP3 calculations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, pp. 180, 2009, IEEE Computer Society, 978-1-4244-4596-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou |
SRAM cell design using tri-state devices for SEU protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, pp. 114-119, 2009, IEEE Computer Society, 978-1-4244-4596-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | |
Selective Triple Modular Redundancy for Single Event Upset (SEU) Mitigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009, San Francisco, California, USA, July 29 - August 1, 2009, pp. 344-350, 2009, IEEE Computer Society, 978-0-7695-3714-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena, B. Lestriez, Luis Berrojo |
Study of SEU effects in a Turbo Decoder Bit Error Rate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 10th Latin American Test Workshop, LATW 2009, Rio de Janeiro, Brazil, March 2-5, 2009, pp. 1-5, 2009, IEEE, 978-1-4244-4206-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano |
Error Correction Codes for SEU and SEFI Tolerant Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 425-430, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Bradley F. Dutton, Mustafa Ali, Charles E. Stroud, John Sunwoo |
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2009 International Conference on Embedded Systems & Applications, ESA 2009, July 13-16, 2009, Las Vegas Nevada, USA, pp. 183-189, 2009, CSREA Press, 1-60132-102-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
19 | Bradley F. Dutton, Charles E. Stroud |
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2009 International Conference on Embedded Systems & Applications, ESA 2009, July 13-16, 2009, Las Vegas Nevada, USA, pp. 149-155, 2009, CSREA Press, 1-60132-102-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
19 | Eliane Elias Ferreira dos Santos |
Estrutura Cognitiva para Tecnologias Educacionais Construtivistas ECoTEC e seu Instrumento de Otimização Web-ECoTEC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2009 |
RDF |
|
19 | Alireza Ejlali, Seyed Ghassem Miremadi |
Error propagation analysis using FPGA-based SEU-fault injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 48(2), pp. 319-328, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Toshimasa Funaki, Toshinori Sato |
Formulating MITF for a Multicore Processor with SEU Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 234-241, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Jirí Kvasnicka, Pavel Kubalík, Hana Kubátová |
Experimental SEU Impact on Digital Design Implemented in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 100-103, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Costas Argyrides, Fabian Vargas 0001, Marlon Moraes, Dhiraj K. Pradhan |
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece, pp. 155-160, 2008, IEEE Computer Society, 978-0-7695-3264-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Shi-Jie Wen, Dan Alexandrescu, Renaud Perez |
A Systematical Method of Quantifying SEU FIT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece, pp. 109-114, 2008, IEEE Computer Society, 978-0-7695-3264-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou |
SRAM Cell Design Protected from SEU Upsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece, pp. 169-170, 2008, IEEE Computer Society, 978-0-7695-3264-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Hamid R. Zarandi, Seyed Ghassem Miremadi |
A SEU-protected cache memory-based on variable associativity of sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Reliab. Eng. Syst. Saf. ![In: Reliab. Eng. Syst. Saf. 92(11), pp. 1584-1596, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego |
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007, pp. 261-266, 2007, IEEE Computer Society, 1-4244-1161-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Cristiana Bolchini, Fabio Salice, Marco D. Santambrogio |
Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ERSA ![In: Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2007, Las Vegas, Nevada, USA, June 25-28, 2007, pp. 199-202, 2007, CSREA Press, 1-60132-026-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
19 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan |
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-6, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Drew C. Ness, Christian J. Hescott, David J. Lilja |
Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2007, San Jose, CA, USA, October 21-22, 2007, pp. 46-53, 2007, IEEE Computer Society, 978-1-4244-1790-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube |
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 50-58, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio |
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 87-95, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota |
Evaluation of SEU and crosstalk effects in network-on-chip switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 202-207, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
network-on-chip, crosstalk, single-event upset |
19 | T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani |
SEU Mitigation Techniques for Microprocessor Control Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Sixth European Dependable Computing Conference, EDCC 2006, Coimbra, Portugal, 18-20 October 2006, pp. 77-86, 2006, IEEE Computer Society, 0-7695-2648-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Maico Cassel, Fernanda Lima Kastensmidt |
Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 139-144, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis |
A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 235-241, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Arthur Pereira Frantz, Fernanda Lima Kastensmidt |
SEU Effects Evaluation on a NoC Router Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 7th Latin American Test Workshop, LATW 2006, Buenos Aires, Argentina, March 26-29, 2006., pp. 117-122, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
19 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan |
Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 265, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Michel Pignol |
How to Cope with SEU/SET at System Level?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 315-318, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Matteo Sonza Reorda, Luca Sterpone, Massimo Violante |
Efficient Estimation of SEU Effects in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 54-59, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert |
Evaluation of SET and SEU Effects at Multiple Abstraction Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 309-312, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan |
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 736-741, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Complex Logic Blocks, Routing Errors, Vertex Coloring problem, Fault Tolerance, Field Programmable Gate Arrays, Graph Theory, Single Event Upset |
19 | William Heidergott |
SEU tolerant device, circuit and processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 5-10, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
error detection and correction coding, radiation effects, soft error rate, fault tolerant systems, single event upset, fault masking, temporal redundancy, modular redundancy, fault avoidance |
19 | Marcelo Magalhães Foohs |
Representação gráfica do tempo: efeito de gráficos na compreensão e retenção dos significados do Present Perfect e do seu contraste com o Simple Past. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2005 |
RDF |
|
19 | Romain Desplats, S. Petit, Sana Rezgui, Carl Carmichael, Pascal Fouillat, Dean Lewis |
Investigation of SEU sensitivity of Xilinx Virtex II FPGA by pulsed laser fault injections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 44(9-11), pp. 1709-1714, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Régis Leveugle, Abdelaziz Ammari |
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 590-595, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Vijaykrishnan Narayanan |
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004, pp. 121-128, 2004, IEEE. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante |
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 115-120, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Andrea S. Brogna, Franco Bigongiari, Fabrizio Bertuccelli, Walter Errico, Simone Giovannetti, Egidio Pescari, Roberto Saletti |
SEU Protected CPU for Slow Control on Space Vehicles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 422-424, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Angelica Carvalho Di Maio |
Geotecnologias digitais no ensino médio: avaliação prática de seu potencial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2004 |
RDF |
|
19 | Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali |
Fault injection into SRAM-based FPGAs for the analysis of SEU effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, FPT 2003, December 15-17, 2003, pp. 428-430, 2003, IEEE. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi |
A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 71-78, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante |
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 607-615, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante |
Analysis of SEU Effects in a Pipelined Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 112-116, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Fernanda Lima 0001, Luigi Carro, Raul Velazco, Ricardo Reis 0001 |
Injecting Multiple Upsets in a SEU tolerant 8051 Micro-controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 3rd Latin American Test Workshop, LATW 2002, Montevideo, Uruguay, February 10-13, 2002., pp. 120-125, 2002, IEEE. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
19 | Ivan de Paúl, Miquel Roca 0001, Oscar Calvo, Raul Velazco |
SEU fault injection in simulation environments: example of VHDL configuration on FPGA device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 3rd Latin American Test Workshop, LATW 2002, Montevideo, Uruguay, February 10-13, 2002., pp. 114-119, 2002, IEEE. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
19 | Pablo A. Ferreyra, Carlos A. Marqués, Javier P. Gaspar, Raul Velazco, Ricardo T. Ferreyra |
SEU-Induced-Fault Detection-Efficiency of a Watch Dog Circuit for a Micro-Satellite on Board Digital Signal Processor System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 3rd Latin American Test Workshop, LATW 2002, Montevideo, Uruguay, February 10-13, 2002., pp. 106-108, 2002, IEEE. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
19 | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto |
Static Analysis of SEU Effects on Software Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 500-508, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | José A. Soto Mejía |
Uma abordagem unificada para modelar processos de Workflow e seu software de suporte. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2002 |
RDF |
|
19 | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto |
SEU effect analysis in an open-source router via a distributed fault injection environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 219-225, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Fabian Vargas 0001, Alexandre M. Amory |
Circuit Modeling and Fault Injection Approach to Predict SEU Rate and MTTF in Complex Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 2nd Latin American Test Workshop, LATW 2001, Cancun, Mexico, February 11-14, 2001., pp. 6-12, 2001, IEEE. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
19 | Vincent Pouget, Pascal Fouillat, Dean Lewis, Hervé Lapuyade, L. Sarger, F. M. Roche, S. Duzellier, R. Ecoffet |
An Overview of the Applications of a Pulsed Laser System for SEU Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 52-, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | F. L. Vargas, Michael Nicolaidis |
SEU-Tolerant SRAM Design Based on Current Monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS/24, The Twenty-Fourth Annual International Symposium on Fault-Tolerant Computing, Austin, Texas, USA, June 15-17, 1994, pp. 106-115, 1994, IEEE Computer Society, 0-8186-5520-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Luís João de Sousa Cardoso |
A União Internacional de Telecomunicações e o Seu Papel na Normalização no Sector das Telecomunicações. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QUATIC ![In: Proceedings of the 1st International Conference on the Quality of Information and Communications Technology, QUATIC 1994, Lisboa, Portugal, May 27, 1994., pp. 89-101, 1994, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
13 | Xin He, Afshin Abdollahi |
Cost aware fault tolerant logic synthesis in presence of soft errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 151-154, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
soft error rate, reliability, linear programming |
13 | Kuen-Long Leu, Chin-Long Wey, Jwu-E Chen, Yung-Yuan Chen |
Robustness investigation of the FlexRay system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Fourth International Symposium on Industrial Embedded Systems, SIES 2009, Ecole Polytechnique Federale de Lausanne, Switzerland, July 8-10, 2009, pp. 148-151, 2009, IEEE, 978-1-4244-4110-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Chong Zhao, Yi Zhao, Sujit Dey |
Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(6), pp. 714-724, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Rajesh Garg, Peng Li 0001, Sunil P. Khatri |
Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1788-1791, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Mahdi Fazeli, Seyed Ghassem Miremadi |
A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 193-201, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Rui Gong, Kui Dai, Zhiying Wang 0003 |
Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan, pp. 273-280, 2008, IEEE Computer Society, 978-0-7695-3448-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Juan Antonio Maestro, Pedro Reviriego |
Study of the effects of MBUs on the reliability of a 150 nm SRAM device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 930-935, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multiple bit upsets (MBUs), reliability, memory, radiation |
13 | Han Liang, Piyush Mishra, Kaijie Wu 0001 |
Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 243-252, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy |
13 | Sajid Baloch, Tughrul Arslan, Adrian Stoica |
Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-8, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 113-120, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | X. Cano, Sebastià A. Bota, Ricardo Graciani Diaz, David Gascon, A. Herms, Albert Comerma, Jaume Segura 0001, Lluís Garrido |
Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 183-184, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren |
Quantitative Analysis of In-Field Defects in Image Sensor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 526-534, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Jorge Luis Lagos-Benites, Davide Appello, Paolo Bernardi, Michelangelo Grosso, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda |
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 291-300, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Avijit Dutta, Nur A. Touba |
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 349-354, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Luca Sterpone, Massimo Violante |
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(6), pp. 732-744, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
transient fault injection, FPGA, reliability, place and route |
13 | Luiz Eduardo Cunha Leite, Guido Lemos de Souza Filho, Silvio Romero de Lemos Meira, Patrick Carlos T. de Arújo, Jefferson Ferreira de A. Lima, Sindolfo Miranda Filho |
A component model proposal for embedded systems and its use to add reconfiguration capabilities to the FlexTV middleware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WebMedia ![In: Proceedings of the 12th Brazilian Symposium on Multimedia and the Web, WebMedia 2006, Natal, Rio Grande do Norte, Brazil, November 19-22, 2006, pp. 203-212, 2006, ACM, 85-7669-100-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
middleware, component based development, digital television, context representation |
13 | Alan Silva, Rômulo Silva de Oliveira, Ig Ibert Bittencourt |
An environment for supporting automated electronic negotiations using ontologies and production rules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WebMedia ![In: Proceedings of the 12th Brazilian Symposium on Multimedia and the Web, WebMedia 2006, Natal, Rio Grande do Norte, Brazil, November 19-22, 2006, pp. 303-312, 2006, ACM, 85-7669-100-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Américo Talarico Neto, Júnia Coutinho Anacleto Silva, Vânia Paula de Almeida Néris, Muriel de Souza Godoi, Aparecido Fabiano Pinatti de Carvalho |
A framework to support the design of learning objects based on the Cog-Learn Pattern Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WebMedia ![In: Proceedings of the 12th Brazilian Symposium on Multimedia and the Web, WebMedia 2006, Natal, Rio Grande do Norte, Brazil, November 19-22, 2006, pp. 128-137, 2006, ACM, 85-7669-100-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
EAD, cog-learn, cognitor, educação à distância, interação humano-computador, linguagem de padrões, projeto web, SCORM |
13 | Pavel Kubalík, Radek Dobias, Hana Kubátová |
Dependable Design for FPGA Based on Duplex System and Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 139-145, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto |
Single-Event Upset Analysis and Protection in High Speed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 29-34, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Sajid Baloch, Tughrul Arslan, Adrian Stoica |
An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Bernhard Fechner |
Analysis of checksum-based execution schemes for pipelined processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Mihir R. Choudhury, Quming Zhou, Kartik Mohanram |
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 204-209, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena |
Emulation-based Fault Injection in Circuits with Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 183-184, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Sajid Baloch, Tughrul Arslan, Adrian Stoica |
An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 292-295, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto |
Combined software and hardware techniques for the design of reliable IP processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 265-273, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|