Search results for "SystemC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Imed Moussa, Thierry Grellier, Giang Nguyen	Exploring SW Performance Using SoC Transaction-Level Modeling.	DATE	2003	DBLP DOI BibTeX RDF
19	Robert Siegmund, Dietmar Müller 0001	Efficient modeling and synthesis of on-chip communication protocols for network-on-chip design.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
19	Giovanni Agosta, Francesco Bruschi, Donatella Sciuto	Static analysis of transaction-level models.	DAC	2003	DBLP DOI BibTeX RDF	communication implementation, static analysis, transaction level modelling
19	Maurizio Martignano, Nicola Drago, Franco Fummi, Stefano Martini	A combined approach to validate the design of embedded network devices.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
19	Patrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya	Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures.	ASP-DAC	2001	DBLP DOI BibTeX RDF
19	Stan Y. Liao	Towards a new standard for system-level design.	CODES	2000	DBLP DOI BibTeX RDF
16	Nicolas Ventroux, Alexandre Guerre, Tanguy Sassolas, L. Moutaoukil, Guillaume Blanc, Charly Bechara, Raphaël David	SESAM: An MPSoC Simulation Environment for Dynamic Application Processing.	CIT	2010	DBLP DOI BibTeX RDF	SESAM, simulation, modeling, multiprocessor, dynamic, exploration, SystemC, MPSoC
16	Dogan Fennibay, Arda Yurdakul, Alper Sen 0001	Introducing Hardware-in-Loop Concept to the Hardware/Software Co-design of Real-time Embedded Systems.	CIT	2010	DBLP DOI BibTeX RDF	hil, industrial communication, bacnet, real-time, embedded, linux, systemc, codesign, co-design, hardware/software co-design, hardware-in-the-loop
16	Ke Yu, Neil C. Audsley	Combining Behavioural Real-time Software Modelling with the OSCI TLM-2.0 Communication Standard.	CIT	2010	DBLP DOI BibTeX RDF	Simulation, Software, SystemC, TLM
16	Juan Fernando Eusse Giraldo, Michael Hübner 0001, Ricardo Pezzuol Jacobi	BRICK: a multi-context expression grained reconfigurable architecture.	SBCCI	2009	DBLP DOI BibTeX RDF	validation, reconfigurable computing, MIMO, SystemC, co-simulation, coarse grain
16	Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose	FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.	FCCM	2009	DBLP DOI BibTeX RDF	photodynamic therapy, PDT, Stratix, DE3, FPGA, applications, pipeline, Power, Monte Carlo, SystemC, acceleration, cancer
16	Tom Borgstrom, Eshel Haritan, Ron Wilson, David Abada, Andrew Dauman, Ramesh Chandra, Olivier Mielo, Chuck Cruse, Achim Nohl	System prototypes: virtual, hardware or hybrid?	DAC	2009	DBLP DOI BibTeX RDF	SystemC TLM, hardware/software co-verification, rapid prototype, embedded software, virtual prototype, virtual platform, system validation, FPGA prototype, system prototype
16	Katalin Popovici, Xavier Guerin, Frédéric Rousseau 0001, Pier Stanislao Paolucci, Ahmed Amine Jerraya	Platform-based software design flow for heterogeneous MPSoC.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	multimedia, programming environment, software design, SystemC, Simulink, transaction level modeling, Multiprocessor system-on chip
16	Ankush Varma, Eric Debes, Igor Kozintsev, Paul Klein, Bruce L. Jacob	Accurate and fast system-level power modeling: An XScale-based case study.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	embedded systems, SystemC, Power modeling
16	Ankush Varma, Bruce L. Jacob, Eric Debes, Igor Kozintsev, Paul Klein	Accurate and fast system-level power modeling: An XScale-based case study.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	embedded systems, SystemC, Power modeling
16	Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch	EWD: A metamodeling driven customizable multi-MoC system modeling framework.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	ForSyDe, MoC, heterogeneous system design, interoperable modeling language, Metamodeling, metamodel, SystemC, functional language, denotational semantics, Ptolemy II
16	George Sobral Silveira, Karina R. G. da Silva, Elmar U. K. Melcher	Functional verification of an MPEG-4 decoder design using a random constrained movie generator.	SBCCI	2007	DBLP DOI BibTeX RDF	VeriSC, randmovie, stimuli, verification, SystemC, movie, functional coverage
16	Wolfgang Klingauf, Robert Günzel, Christian Schröder	Embedded software development on top of transaction-level models.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	hardware-software communication, middleware, SoC, embedded software, SystemC, HPC, TLM
16	Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos	A multi-model power estimation engine for accuracy optimization.	ISLPED	2007	DBLP DOI BibTeX RDF	power macromodeling, powerSC, low power design, systemC, power estimation
16	James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu	A new efficient EDA tool design methodology.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Net Framework, C?, ESys.Net, attribute programming, embedded systems, SoC, VHDL, SystemC, modeling and simulation, CoDesign
16	Wolfgang Mueller, Yves Vanderperren	UML and model-driven development for SoC design.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	simulation, UML, SoC, tools, SystemC, UML profiles, ESL design
16	Daniel Große, Ulrich Kühne, Rolf Drechsler	HW/SW co-verification of embedded systems using bounded model checking.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	hardware/software co-verification, embedded systems, formal verification, SystemC, bounded model checking, PSL
16	Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino	ISS-centric modular HW/SW co-simulation.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	systemc, co-simulation, instruction set simulator
16	Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch	Building a standard ESL design and verification methodology: is it just a dream?	DAC	2006	DBLP DOI BibTeX RDF	modeling rapid hardware prototyping, design, verification, methodology, systemC, RTL, ESL, C/C++, systemVerilog
16	Wolfgang Klingauf, Robert Günzel, Oliver Bringmann 0001, Pavel Parfuntseu, Mark Burton	GreenBus: a generic interconnect fabric for transaction level modelling.	DAC	2006	DBLP DOI BibTeX RDF	SoC, SystemC, TLM, on-chip communication
16	Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung	Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	SoC, systemc, transaction-level modeling, TLM, simulation acceleration
16	Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel	Retargetable generation of TLM bus interfaces for MP-SoC platforms.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	simulation, SystemC, architecture exploration, TLM, retargetability, MP-SoC
16	Annette Bunker, Ganesh Gopalakrishnan, Sally A. McKee	Formal hardware specification languages for protocol compliance verification.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Heterogeneous Hardware Logic, Hierarchical Annotated Action Diagrams, Lava, Objective VHDL, OpenVera, SpecC, Specification and Description Language, The Unified Modeling Language, Java, Statecharts, SystemC, Message Sequence Charts, Esterel, Live Sequence Charts, timing diagrams, hardware monitors, SystemVerilog, e, Property Specification Language
16	James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois	ESys.Net: a new solution for embedded systems modeling and simulation.	LCTES	2004	DBLP DOI BibTeX RDF	CIL, ESys.Net, attribute programming, component-based programming, simulation, Java, modeling, embedded systems, C++, framework, system on chip, VHDL, SystemC, hardware/software codesign, C#, Net, Verilog, HDLs, SystemVerilog
16	Rajesh K. Gupta 0001, Sandeep K. Shukla, Nick Savoiu	Efficient Simulation of Synthesis-Oriented System Level Designs.	ISSS	2002	DBLP DOI BibTeX RDF	simulation, SystemC, system-level design
16	Oliver Schliebusch, Andreas Hoffmann 0002, Achim Nohl, Gunnar Braun, Heinrich Meyr	Architecture Implementation Using the Machine Description Language LISA.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Design, Implementation, Synthesis, VHDL, Exploration, SystemC, ASIP, Verilog, LISA
15	Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari	Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices.	CoRR	2024	DBLP DOI BibTeX RDF
15	Fabian Schätzle, Carlos Falquez, Stefan Heinen, Nam Ho, Antoni Portero, Estela Suarez, Johannes Van Den Boom, Stefan van Waasen	Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation.	RAPIDO@HiPEAC	2024	DBLP DOI BibTeX RDF
15	Philip Tasche, Raúl E. Monti, Stefanie Eva Drerup, Pauline Blohm, Paula Herber, Marieke Huisman	Deductive Verification of Parameterized Embedded Systems Modeled in SystemC.	VMCAI (2)	2024	DBLP DOI BibTeX RDF
15	Enrico Fraccaroli, Sara Vinco	Modeling Cyber-Physical Production Systems With SystemC-AMS.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
15	Vittoriano Muttillo, Luigi Pomante, Marco Santic, Giacomo Valente	SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design.	Comput. Electr. Eng.	2023	DBLP DOI BibTeX RDF
15	Andrija Neskovic, Saleh Mulhem, Alexander Treff, Rainer Buchty, Thomas Eisenbarth 0001, Mladen Berekovic	SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?	CoRR	2023	DBLP DOI BibTeX RDF
15	Pauline Blohm, Julius Adelt, Paula Herber	Safe Integration of Learning in SystemC using Timed Contracts and Model Checking.	MEMOCODE	2023	DBLP BibTeX RDF
15	Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Lukas Jünger 0001, Jan Henrik Weinstock, Rainer Leupers	Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TlM-2.0-Based Virtual Platforms.	CODES+ISSS	2023	DBLP BibTeX RDF
15	Ebrahim Nouri, Nooshin Nosrati, Hanieh Totonchi Asl, Mozhgan Rezaie Manavand, Zainalabedin Navabi	Multi-Level Fault Injection Methodology Using UVM-SystemC.	EWDTS	2023	DBLP DOI BibTeX RDF
15	Alexandra Küster, Rainer Dorsch, Christian Haubelt	Structural Generation of Virtual Prototypes for Smart Sensor Development in SystemC-AMS from Simulink Models.	DATE	2023	DBLP DOI BibTeX RDF
15	Rahul Bhadani, Gabor Karsai, Hao Tu, Srdjan M. Lukic	Modeling and Real-Time Simulation of Microgrid Components Using Systemc-Ams.	WSC	2023	DBLP DOI BibTeX RDF
15	Hanwen Gong, Hu He 0001, Bin Gao 0006, Jianshi Tang, Qingtian Zhang, He Qian, Huaqiang Wu	ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing.	ICTA	2023	DBLP DOI BibTeX RDF
15	Zhuanhao Wu, Maya B. Gokhale, Scott Lloyd, Hiren D. Patel	SCCL: An open-source SystemC to RTL translator.	FCCM	2023	DBLP DOI BibTeX RDF
15	Andrija Neskovic, Saleh Mulhem, Alexander Treff, Rainer Buchty, Thomas Eisenbarth 0001, Mladen Berekovic	SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?	ICCAD	2023	DBLP DOI BibTeX RDF
15	Mehran Goli, Rolf Drechsler	Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
15	Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay	Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution.	CoRR	2022	DBLP DOI BibTeX RDF
15	Mehran Goli, Rolf Drechsler	Simulation-based Verification of SystemC-based VPs at the ESL.	CoRR	2022	DBLP BibTeX RDF
15	Nils Bosbach, Lukas Jünger 0001, Jan Moritz Joseph, Rainer Leupers	NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool.	CoRR	2022	DBLP DOI BibTeX RDF
15	Denis Uecker, Matthias Jung 0001	Split'n'Cover: ISO 26262 Hardware Safety Analysis with SystemC.	SAMOS	2022	DBLP DOI BibTeX RDF
15	Essraa Massoud, Mohamed Abdelsalam, Mona Safar, M. Watheq El-Kharashi	A Reusable UVM-SystemC Verification Environment for Simulation, Hardware Emulation, and FPGA Prototyping: Case Studies.	ICM	2022	DBLP DOI BibTeX RDF
15	Nils Bosbach, Jan Moritz Joseph, Rainer Leupers, Lukas Jünger 0001	NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
15	Seyed Hossein Hashemi Shadmehri, Ali BanaGozar, Mehdi Kamal, Sander Stuijk, Ali Afzali-Kusha, Massoud Pedram, Henk Corporaal	SySCIM: SystemC-AMS Simulation of Memristive Computation In-Memory.	DATE	2022	DBLP DOI BibTeX RDF
15	Mehran Goli, Rolf Drechsler	Simulation-based Verification of SystemC-based VPs at the ESL.	MBMV	2022	DBLP BibTeX RDF
15	Yutong Wang, Arya Daroui, Rainer Dömer	Demonstrating Scalability of the Checkerboard GPC with SystemC TLM-2.0.	IESS	2022	DBLP DOI BibTeX RDF
15	Alexandra Küster, Rainer Dorsch, Christian Haubelt, Karsten Einwich	Virtual Prototyping in SystemC AMS for Validation of Tight Sensor/Firmware Interaction in Smart Sensors.	FDL	2022	DBLP DOI BibTeX RDF
15	Chenyu Huang, Huaien Gao, Yongfeng Zhong, Shuting Cai	A High-Performance Bidirectional Compiler for conversion between SystemC and Verilog.	HP3C	2022	DBLP DOI BibTeX RDF
15	Melvin Galicia, Farhad Merchant, Rainer Leupers	A Parallel SystemC Virtual Platform for Neuromorphic Architectures.	ISQED	2022	DBLP DOI BibTeX RDF
15	Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler	Verifying SystemC TLM peripherals using modern C++ symbolic execution tools.	DAC	2022	DBLP DOI BibTeX RDF
15	Gabriel Busnot, Tanguy Sassolas, Nicolas Ventroux, Matthieu Moy	Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support.	Integr.	2021	DBLP DOI BibTeX RDF
15	Khaled Allem, El-Bay Bourennane, Youcef Khelfaoui	A Service-Oriented Component-Based Framework for Dynamic Reconfiguration Modeling Targeting SystemC/TLM.	Int. J. Reconfigurable Comput.	2021	DBLP DOI BibTeX RDF
15	Zhongqi Cheng, Tim Schmidt, Rainer Dömer	Scaled Static Analysis and IP Reuse for Out-of-Order Parallel SystemC Simulation.	Int. J. Parallel Program.	2021	DBLP DOI BibTeX RDF
15	Breytner Fernández-Mesa, Liliana Andrade, Frédéric Pétrot	Synchronization of Continuous Time and Discrete Events Simulation in SystemC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Silvia Scaffeo, Antonio Mastrandrea, Simone Caligola, Tommaso Carlucci, Franco Fummi, Carlo Laudanna, Gabriela Constantin, Rosalba Giugno	SystemC Implementation of Stochastic Petri Nets for Simulation and Parameterization of Biological Networks.	ACM Trans. Embed. Comput. Syst.	2021	DBLP DOI BibTeX RDF
15	Melvin Galicia, Farhad Merchant, Rainer Leupers	A Parallel SystemC Virtual Platform for Neuromorphic Architectures.	CoRR	2021	DBLP BibTeX RDF
15	Sören Tempel, Vladimir Herdt, Rolf Drechsler	An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes.	DATE	2021	DBLP DOI BibTeX RDF
15	Mehran Goli, Alireza Mahzoon, Rolf Drechsler	Automated Debugging-Aware Visualization Technique for SystemC HLS Designs.	DSD	2021	DBLP DOI BibTeX RDF
15	Mehran Goli, Rolf Drechsler	ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs.	ASP-DAC	2021	DBLP DOI BibTeX RDF
15	Breytner Joseph Fernández-Mesa, Liliana Andrade, Frédéric Pétrot	Simulation of Ideally Switched Circuits in SystemC.	ASP-DAC	2021	DBLP DOI BibTeX RDF
15	Rainer Dömer, Zhongqi Cheng, Daniel Mendoza, Emad Malekzadeh Arasteh	Pushing the Limits of Parallel Discrete Event Simulation for SystemC.	A Journey of Embedded and Cyber-Physical Systems	2021	DBLP DOI BibTeX RDF
15	Antonio Genov, François Verdier, Loic Leconte	Expand Reuse Strategy to ESL Power Modeling in SystemC/TLM.	ICECS	2021	DBLP DOI BibTeX RDF
15	Mehran Goli, Rolf Drechsler	Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs.	ICCAD	2021	DBLP DOI BibTeX RDF
15	Nathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany	IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs.	ICCAD	2021	DBLP DOI BibTeX RDF
15	Mehran Goli, Rolf Drechsler	VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes.	FDL	2021	DBLP DOI BibTeX RDF
15	Tommaso Rizzi, Emilio Pérez-Bosch Quesada, Christian Wenger, Cristian Zambelli, Davide Bertozzi	Comparative Analysis and Optimization of the SystemC-AMS Analog Simulation Efficiency of Resistive Crossbar Arrays.	DCIS	2021	DBLP DOI BibTeX RDF
15	Benjamin Beichler, Michael Rethfeldt, Hannes Raddatz, Lukas Steffen, Dirk Timmermann, Christian Haubelt	A SystemC Model of the IEEE 802.11 EDCA Protocol for Virtual Prototyping.	ISNCC	2021	DBLP DOI BibTeX RDF
15	Luigi Pomante, Vittoriano Muttillo, Marco Santic, Paolo Serri	SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
15	Bin Lin, Fei Xie	A Systematic Investigation of State-of-the-Art SystemC Verification.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
15	Mehran Goli, Rolf Drechsler	PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques.	ACM Trans. Design Autom. Electr. Syst.	2020	DBLP DOI BibTeX RDF
15	Marius Monton	A RISC-V SystemC-TLM simulator.	CoRR	2020	DBLP BibTeX RDF
15	Gaogao Yan, Li Jiao, Shuling Wang, Lingtai Wang, Naijun Zhan	Automatically Generating SystemC Code from HCSP Formal Models.	ACM Trans. Softw. Eng. Methodol.	2020	DBLP DOI BibTeX RDF
15	Yukai Chen, Sara Vinco, Daniele Jahier Pagliari, Paolo Montuschi, Enrico Macii, Massimo Poncino	Modeling and Simulation of Cyber-Physical Electrical Energy Systems With SystemC-AMS.	IEEE Trans. Sustain. Comput.	2020	DBLP DOI BibTeX RDF
15	Tun Li, Jun Ye, Qingping Tan	Towards functional verifying a family of systemC TLMs.	Frontiers Comput. Sci.	2020	DBLP DOI BibTeX RDF
15	Lukas Steiner, Matthias Jung 0001, Felipe S. Prado, Kirill Bykov, Norbert Wehn	DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator.	SAMOS	2020	DBLP DOI BibTeX RDF
15	Paula Herber, Timm Liebrenz	Dependence Analysis and Automated Partitioning for Scalable Formal Analysis of SystemC Designs.	MEMOCODE	2020	DBLP DOI BibTeX RDF
15	Mehran Goli, Rolf Drechsler	Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization.	ISVLSI	2020	DBLP DOI BibTeX RDF
15	Josef Treus, Paula Herber	Early Analysis of Security Threats by Modeling and Simulating Power Attacks in SystemC.	VTC Spring	2020	DBLP DOI BibTeX RDF
15	Bin Lin, Jinchao Chen, Fei Xie	Selective Concolic Testing for Hardware Trojan Detection in Behavioral SystemC Designs.	DATE	2020	DBLP DOI BibTeX RDF
15	Breytner Fernández-Mesa, Liliana Andrade, Frédéric Pétrot	Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemC.	DATE	2020	DBLP DOI BibTeX RDF
15	Gabriel Busnot, Tanguy Sassolas, Nicolas Ventroux, Matthieu Moy	Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models.	ASP-DAC	2020	DBLP DOI BibTeX RDF
15	Zhongqi Cheng, Emad Malekzadeh Arasteh, Rainer Dömer	Event Delivery using Prediction for Faster Parallel SystemC Simulation.	ASP-DAC	2020	DBLP DOI BibTeX RDF
15	Jakob Heller, Christoph Niemann 0002, Franz Plocksties, Christian Haubelt, Dirk Timmermann	Towards Virtual Prototyping of Electrically Active Implants Using SystemC-AMS.	MBMV	2020	DBLP BibTeX RDF
15	Alisson Linhares, Henrique Rusa, Daniel Formiga, Rodolfo Azevedo	A SystemC profiling framework to improve fixed-point hardware utilization.	SBCCI	2020	DBLP DOI BibTeX RDF
15	Éder F. Zulian, Germain Haugou, Christian Weis, Matthias Jung 0001, Norbert Wehn	System simulation with PULP virtual platform and SystemC.	RAPIDO	2020	DBLP DOI BibTeX RDF
15	François Pêcheux, Liliana Andrade, Marie-Minerve Louërat, Ilias Bournias, Roselyne Chotin, Daniela Genius	Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions.	FDL	2020	DBLP DOI BibTeX RDF
15	Carna Zivkovic, Christoph Grimm 0001, Johannes Kölsch, D. Short, M. Ferstl, Dirk Denger, D. Krems, A. Barisic	Bringing Uncertainties into System Simulation: A SystemC AMS Case Study.	FDL	2020	DBLP DOI BibTeX RDF
15	Mehran Goli, Alireza Mahzoon, Rolf Drechsler	ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique.	ICCD	2020	DBLP DOI BibTeX RDF
15	Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler	Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
15	Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler	Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes.	DAC	2020	DBLP DOI BibTeX RDF
15	Yukai Chen, Donkyu Baek, Jaemin Kim, Santa Di Cataldo, Naehyuck Chang, Enrico Macii, Sara Vinco, Massimo Poncino	A SystemC-AMS Framework for the Design and Simulation of Energy Management in Electric Vehicles.	IEEE Access	2019	DBLP DOI BibTeX RDF