Search results for "VHDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	Xinli Gu, Krzysztof Kuchcinski, Zebo Peng	Testability analysis and improvement from VHDL behavioral specifications.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Norbert Wehn, Jörg Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, Steffen Rumler	Scheduling of behavioral VHDL by retiming techniques.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Arlet Ottens, Henk Corporaal, Wilco Van Hoogstraeten	A new flexible VHDL simulator.	EURO-DAC	1994	DBLP DOI BibTeX RDF	C++, VHDL
28	Donatella Sciuto, Stefano Antoniazzi, Alessandro Balboni, William Fornaciari	The role of VHDL within the TOSCA hardware/software codesign framework.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Oz Levia, Serge Maginot, Jacques Rouillard	Lessons in Language Design: Cost/Benefit analysis of VHDL Features.	DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Yuri Tatarnikov	The State of VHDL in Russia.	DAC	1993	DBLP DOI BibTeX RDF	VHDL
22	Aubin Lecointre, Daniela Dragomirescu, Robert Plana	System Architecture Modeling of an UWB Receiver for Wireless Sensor Network.	SAMOS	2007	DBLP DOI BibTeX RDF
22	Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee	SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
22	Alex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis 0001, Sergio Bampi	Design of Very Deep Pipelined Multipliers for FPGAs.	DATE	2004	DBLP DOI BibTeX RDF
22	Fabrizio Ferrandi, Franco Fummi, Graziano Pravadelli, Donatella Sciuto	Identification of design errors through functional testing.	IEEE Trans. Reliab.	2003	DBLP DOI BibTeX RDF
22	Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali	Fast Prototyping with Co-operation of Simulation and Emulation.	FPL	2002	DBLP DOI BibTeX RDF
22	Guido Arnout	C for System Level Design.	DATE	1999	DBLP DOI BibTeX RDF
22	Tsai Chi Huang, Sudhakar Yalamanchili, Roy W. Melton, Philip R. Bingham, Cecil O. Alford	Teaching Pipelining and Concurrency using Hardware Description Languages.	MSE	1999	DBLP DOI BibTeX RDF
22	Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum	Program Slicing of Hardware Description Languages.	CHARME	1999	DBLP DOI BibTeX RDF
22	Harry Hsieh, Felice Balarin	Synchronous equivalence for embedded systems: a tool for design exploration.	ICCAD	1999	DBLP DOI BibTeX RDF
22	Dragos Lungeanu, C.-J. Richard Shi	Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization.	ICCAD	1999	DBLP DOI BibTeX RDF
22	Josef Fleischmann, Rolf Schlagenhaft, Martin Peller, Norbert Fröhlich	OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
22	Ghassan Al Hayek, Chantal Robach	On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hardware test data, behavioral fault modeling, gate-level strategies, high-level fault detection, gate-level fault detection, design automation tools, generated test set, gate-level fault coverage, hardware description languages, hardware description languages, behavioral specification
22	Shuo Shi, Hongli Tian, Yandong Zhai	Design of Intelligent Traffic Light Controller Based on VHDL.	WKDD	2009	DBLP DOI BibTeX RDF
22	Juan Carlos Baraza, Joaquin Gracia, Sara Blanc, Daniel Gil, Pedro J. Gil	Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
22	Ismael Millán, Oscar Montiel, Roberto Sepúlveda, Oscar Castillo 0001	Design and Implementation of a Hybrid Fuzzy Controller Using VHDL.	Soft Computing for Hybrid Intelligent Systems	2008	DBLP DOI BibTeX RDF
22	José A. Olivas, Roberto Sepúlveda, Oscar Montiel, Oscar Castillo 0001	Methodology to Test and Validate a VHDL Inference Engine through the Xilinx System Generator.	Soft Computing for Hybrid Intelligent Systems	2008	DBLP DOI BibTeX RDF
22	Weiguang Sheng, Liyi Xiao, Zhigang Mao	An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.	DELTA	2008	DBLP DOI BibTeX RDF	simulated fault injection, reliability, VLSI, soft error, stratified sampling
22	Stephen Wood, David H. Akehurst, W. Gareth J. Howells, Klaus D. McDonald-Maier	Array OL Descriptions of Repetitive Structures in VHDL.	ECMDA-FA	2008	DBLP DOI BibTeX RDF
22	César A. M. Marcon, Sergio Johann Filho, Fabiano Hessel	A VHDL based approach for fast and accurate energy consumption estimations.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
22	Yana Yankova, Koen Bertels, Georgi Kuzmanov, Georgi Gaydadjiev, Yi Lu 0004, Stamatis Vassiliadis	DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator.	FPL	2007	DBLP DOI BibTeX RDF
22	Maciej Brzozowski, Vyacheslav N. Yarmolik	Obfuscation as Intellectual Rights Protection in VHDL Language.	CISIM	2007	DBLP DOI BibTeX RDF
22	Gildas Genest, Richard Chamberlain, Robin J. Bruce	Programming an FPGA-based Super Computer Using a C-to-VHDL Compiler: DIME-C.	AHS	2007	DBLP DOI BibTeX RDF
22	Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber	A Mixed Language Fault Simulation of VHDL and SystemC.	DSD	2006	DBLP DOI BibTeX RDF
22	Johan Iskandar, John D. Zakis	VHDL Implementation of Neurone Networks Using a Simplified Action Potential Waveform.	CIMCA/IAWTIC	2006	DBLP DOI BibTeX RDF
22	Oliver Pell, Wayne Luk	Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information.	FPL	2006	DBLP DOI BibTeX RDF
22	Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker 0001, Reiner W. Hartenstein	From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.	FPL	2006	DBLP DOI BibTeX RDF
22	Marcelino Minero-Muñoz, Vicente Alarcón Aquino	A Hierarchical Approach for Modelling an MPLS Network Using VHDL.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
22	Fabrizio Ferrandi, Giovanna Ferrara, Roberto Palazzo, Vincenzo Rana, Marco D. Santambrogio	VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow.	IPDPS	2006	DBLP DOI BibTeX RDF
22	Betul Buyukkurt, Zhi Guo, Walid A. Najjar	Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
22	Kaiping Zeng, Sorin A. Huss	Architecture refinements by code refactoring of behavioral VHDL-AMS models.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Joël Chavas, Demian Battaglia, Andres Cicuttin, Riccardo Zecchina	Construction and VHDL Implementation of a Fully Local Network with Good Reconstruction Properties of the Inputs.	IWINAC (2)	2005	DBLP DOI BibTeX RDF
22	Kaiping Zeng, Sorin A. Huss	RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis.	ISVLSI	2005	DBLP DOI BibTeX RDF
22	Hamid Reza Ghasemi, Zainalabedin Navabi	An Effective VHDL-AMS Simulation Algorithm with Event Partitioning.	VLSI Design	2005	DBLP DOI BibTeX RDF
22	B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot	VHDL-AMS Library Development for Pacemaker Applications.	DATE	2004	DBLP DOI BibTeX RDF
22	Andrea Del Re, Alberto Nannarelli, Marco Re	A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters.	DATE	2004	DBLP DOI BibTeX RDF
22	Jan Borgosz, Boguslaw Cyganek	Proposal of the Programming Rules for VHDL Designs.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
22	Chandramouli Gopalakrishnan, Srinivas Katkoori	An Architectural Leakage Power Simulator for VHDL Structural Datapaths.	ISVLSI	2003	DBLP DOI BibTeX RDF
22	Rami Ahola, Daniel Wallner, Marius Sida	Bluetooth Transceiver Design with VHDL-AMS.	DATE	2003	DBLP DOI BibTeX RDF
22	Pilar Martínez Ortigosa, O. López, R. Estrada, Inmaculada García, Ester M. Garzón	A VHDL Library to Analyse Fault Tolerant Techniques.	FPL	2003	DBLP DOI BibTeX RDF
22	Volnei A. Pedroni	Teaching Design-Oriented VHDL.	MSE	2003	DBLP DOI BibTeX RDF
22	Angel Barriga, Santiago Sánchez-Solano, Piedad Brox Jiménez, Alejandro Cabrera, Iluminada Baturone	VHDL High Level Modelling and Implementation of Fuzzy Systems.	WILF	2003	DBLP DOI BibTeX RDF
22	Chia-Yu Yao, Chin-Chih Yeh, Tsuan-Fan Lin, Hsin-Horng Chen, Chiang-Ju Chien	A design flow for linear-phase fixed-point FIR filters: from the NPRM specifications to a VHDL code.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
22	Régis Leveugle	Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance.	DATE	2002	DBLP DOI BibTeX RDF
22	Jian-Yi Wu, Steven B. Bibyk	Robust design with virtual tests of mixed-signal circuits in VHDL-AMS.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
22	Irfan Darmawan, W. T. Hartono, Eril Mozef, Sarwono Sutikno, Kuspriyanto	VHDL design and simulation of MAM memory for LAPCAM parallel architecture for image processing.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
22	Reinaldo A. C. Bianchi, Anna Helena Reali Costa	Implementing Computer Vision Algorithms in Hardware: An FPGA/VHDL-Based Vision System for a Mobile Robot.	RoboCup	2001	DBLP DOI BibTeX RDF
22	Oleg Maslennikov	Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units.	PPAM	2001	DBLP DOI BibTeX RDF
22	Kah-Howe Tan, Wen Fung-Leong, Sameer Kadam, Michael A. Soderstrand, Louis G. Johnson	Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
22	Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon	Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
22	Daniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil	A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System.	IOLTW	2000	DBLP DOI BibTeX RDF
22	Fabian Vargas 0001, Alexandre M. Amory, Raoul Velazco	Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL.	IOLTW	2000	DBLP DOI BibTeX RDF
22	Juan Carlos Baraza, Joaquin Gracia, Daniel Gil, Pedro J. Gil	A Prototype of a VHDL-Based Fault Injection Tool.	DFT	2000	DBLP DOI BibTeX RDF
22	Régis Leveugle	Fault Injection in VHDL Descriptions and Emulation.	DFT	2000	DBLP DOI BibTeX RDF
22	Françoise Martinolle, Charles Dawson 0002, Debra Corlette, Mike Floyd	Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI.	DATE	1999	DBLP DOI BibTeX RDF
22	Alex Doboli, Ranga Vemuri	A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems.	DATE	1999	DBLP DOI BibTeX RDF
22	François Pêcheux, Yannick Hervé	DIPS for MIPS: An Instrumented VHDL/Corba Kernel for Distributed Learning in EECS.	MSE	1999	DBLP DOI BibTeX RDF
22	Daniel Gil, R. Martínez, J. V. Busquets, Juan Carlos Baraza, Pedro J. Gil	Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System.	EDCC	1999	DBLP DOI BibTeX RDF
22	Md. Altaf-Ul-Amin, Zahari Mohamed Darus	VHDL Design of a Test Processor Based on Mixed-Mode Test Generation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
22	Shugang Wei, Kensuke Shimizu	Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
22	Ronald J. Hayne, Barry W. Johnson	Behavioral Fault Modeling in a VHDL Synthesis Environment.	VTS	1999	DBLP DOI BibTeX RDF
22	Adrian López, Maite Veiga, Eugenio Villar	Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL.	Ada-Europe	1999	DBLP DOI BibTeX RDF
22	Peter J. Ashenden, Philip A. Wilsey	Extensions to VHDL for Abstraction of Concurrency and Communication.	MASCOTS	1998	DBLP DOI BibTeX RDF
22	Michael G. Wahl, Holger Völkel	A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor.	DATE	1998	DBLP DOI BibTeX RDF
22	J. Scott Calhoun, Vijay K. Madisetti, Robert B. Reese, Thomas Egolf	Developing and Distributing Component-Level VHDL Models.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
22	Todd A. DeLong, Barry W. Johnson, Joseph A. Profeta III	A Fault Injection Technique for VHDL Behavioral-Level Models.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
22	Sandi Habinc, Peter Sinander	Using VHDL for Board Level Simulation.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
22	Joel F. Hurford, Thomas C. Hartrum	Improving Conservative VHDL Simulation Performance by Reduction of Feedback.	Workshop on Parallel and Distributed Simulation	1996	DBLP DOI BibTeX RDF	parallel simulation, circuit simulation, conservative simulation
22	Ralf Reetz	Deep Embedding VHDL.	TPHOLs	1995	DBLP DOI BibTeX RDF
22	Maximo H. Salinas, Barry W. Johnson, James H. Aylor	Implementation-Independent Model of an Instruction Set Architecture in VHDL.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
22	Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem	Formal Verification of VHDL Descriptions in the Prevail Environment.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
22	Bruno Poterie	Storage mechanism for VHDL intermediate form.	EURO-DAC	1990	DBLP DOI BibTeX RDF
22	Tuomo Tikkanen, Timo Lappänen, Jorma Kivelä	Structured analysis and VHDL in embedded ASIC design and verification.	EURO-DAC	1990	DBLP DOI BibTeX RDF
22	Heh-Tyan Liaw, K.-T. Tran, Chen-Shang Lin	VVDS: A Verification/Diagnosis System for VHDL.	DAC	1989	DBLP DOI BibTeX RDF
22	Steven S. Leung	Behavioral Modeling of Transmission Gates in VHDL.	DAC	1989	DBLP DOI BibTeX RDF
22	Robert K. Chun, Keh-Jeng Chang, Lawrence P. McNamee	VISION: VHDL Induced Schematic Imaging on Net-Lists.	DAC	1987	DBLP DOI BibTeX RDF
21	Jian-Long Kuo	Intelligent Decoupled SAC-SVD Method in Color Space Transformation of Computer Vision.	IEA/AIE	2009	DBLP DOI BibTeX RDF	reconfigurable computing system (RCS), single assignment C (SAC), chromaticity coordinate, parallel computing, singular value decomposition (SVD), VHDL, data flow graph (DFG), color space, Decoupled
21	Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar	A Compiler Intermediate Representation for Reconfigurable Fabrics.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	FPGA, VHDL, Configurable computing, Intermediate representation
21	Angel Barriga, Nashaat M. Hussein	A Fuzzy Thresholding Circuit for Image Segmentation.	KES (1)	2008	DBLP DOI BibTeX RDF	Fuzzy Logic application, VHDL fuzzy system description, Image segmentation, image thresholding
21	In-Kwon Park, Jung-Hyun Kim 0006, Kwang-Seok Hong	An implementation of an FPGA-based embedded gesture recognizer using a data glove.	ICUIMC	2008	DBLP DOI BibTeX RDF	FPGA, VHDL, gesture recognition
21	Juan Pablo Martinez Brito, Sergio Bampi	Design of a digital FM demodulator based on a 2nddegree order all-digital phase-locked loop.	SBCCI	2007	DBLP DOI BibTeX RDF	all-digital phase-locked loop (ADPLL), digital FM demodulator, frequency modulation (FM), FPGA, VHDL, software-defined radio (SDR), reconfigurable logic
21	Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray 0002	Hardware-based text-to-braille translator.	ASSETS	2006	DBLP DOI BibTeX RDF	braille translation, FPGAs, VHDL
21	Tadayoshi Horita, Takurou Murata, Itsuo Takanami	A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network.	DFT	2006	DBLP DOI BibTeX RDF	weight fault, neuron fault, fault tolerance, FPGA, VHDL, multilayer neural network
21	Ching-Chang Wong, Yu-Han Lin, Shin-An Lee, Cheng-Hsing Tsai	GA-based Fuzzy System Design in FPGA for an Omni-directional Mobile Robot.	J. Intell. Robotic Syst.	2005	DBLP DOI BibTeX RDF	omni-directional mobile robot, genetic algorithms, FPGA, VHDL, fuzzy control
21	Abdelaziz Ammari, K. Hadjiat, Régis Leveugle	Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	RT-level VHDL, 8051, fault injection, VLSI design, dependability analysis, digital circuits
21	Ali Y. Duale, M. Ümit Uyar	A Method Enabling Feasible Conformance Test Sequence Generation for EFSM Models.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	test generation, VHDL, Conformance testing, FSM, Estelle, EFSM
21	Zhenxing Zhang, Jicheng Hu	FPGA Implementation of 4 Samples DWT Based on the Model of Pyramidal Structural Data Coding.	CIT	2004	DBLP DOI BibTeX RDF	bit-moving, VHDL simulation, filter, DWT, pyramid
21	M. Diaby, Matthieu Tuna, Jean Lou Desbarbieux, Franck Wajsbürt	High Level Synthesis Methodology from C to FPGA Used for a Network Protocol Communication.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF	KPN, FPGA, High Level Synthesis, Code Generator, VHDL, Hardware/Software codesign
21	Sung-Hsien Sun, Shie-Jue Lee	A JPEG Chip for Image Compression and Decompression.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	image compression/decompression, standard cell design, FPGA, VHDL, CAD tools, VLSI chip
21	Cheng-Yu Pai, Asim J. Al-Khalili, William E. Lynch	Low-Power Constant-Coefficient Multiplier Generator.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	constant multipliers, low power, VHDL, DSP, design automation, integer multiplication
21	Octavian Cret, Kalman Pusztai, Cristian Vancea, Balint Szente	CREC: A Novel Reconfigurable Computing Design Methodology.	IPDPS	2003	DBLP DOI BibTeX RDF	general-purpose reconfigurable systems, Hardware / Software CoDesign, multiple execution units, FPGA, VHDL, RISC, Instruction Level Parallelism (ILP)
21	Tao Lin, Zhou Zhengou	The Implementation of 100MHz Data Acquisition Based on FPGA.	IWSOC	2003	DBLP DOI BibTeX RDF	Compression Sampling, flag, field programmable gate array (FPGA), memory, VHDL, Top-Down
21	Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee	PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations.	CASES	2002	DBLP DOI BibTeX RDF	FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization
21	Amjad Hajjar, Tom Chen 0001	An Accurate Coverage Forecasting Model for Behavioral Model Verification.	DELTA	2002	DBLP DOI BibTeX RDF	Behavioral model verification, Statistical stopping rules, VHDL
21	Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	VLSI Architecture for a Flexible Motion Estimation with Parameters.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Motion estimation, VHDL, Block matching