Search results for "bit-serial"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Wentai Liu, Su-Shing Chen, Ralph K. Cavin III	A bit-serial VLSI architecture for generating moments in real-time.	IEEE Trans. Syst. Man Cybern.	1993	DBLP DOI BibTeX RDF
17	M. G. Parker, Mohammed Benaissa	Bit-serial, VLSI architecture for the implementation of maximum-length number-theoretic transforms using mixed basis representation.	ICASSP (1)	1993	DBLP DOI BibTeX RDF
17	Paolo Ienne, Marc A. Viredaz	GENES IV: A bit-serial processing element for a built-model neural-network accelerator.	ASAP	1993	DBLP DOI BibTeX RDF
17	M. Anwarul Hasan, Vijay K. Bhargava	Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2^m).	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF
17	Hiroshi Katayama, Youji Kanie, Keiji Taniguchi, Hiroji Kinoshita	Bit-serial, high-speed image processing system.	Syst. Comput. Jpn.	1992	DBLP DOI BibTeX RDF
17	Gary Dudley, Matt Nieman, Steve Vernick	A programmable processor for bit-serial protocols.	ICASSP	1992	DBLP DOI BibTeX RDF
17	David Smitley, Ken Iobst	Bit-Serial SIMD on the CM-2 and the Cray-2.	J. Parallel Distributed Comput.	1991	DBLP DOI BibTeX RDF
17	William Aiello, Frank Thomson Leighton, Bruce M. Maggs, Mark Newman	Fast Algorithms for Bit-Serial Routing on a Hypercube.	Math. Syst. Theory	1991	DBLP DOI BibTeX RDF
17	Douglas R. Stinson	On bit-serial multiplication and dual bases in GF(2m).	IEEE Trans. Inf. Theory	1991	DBLP DOI BibTeX RDF
17	Vincenzo Di Lecce, Eugenio Di Sciascio	Evaluation of a bit-serial ASIC chip for SAR processing.	Microprocess. Microprogramming	1991	DBLP DOI BibTeX RDF
17	R. Nagalla, Laurence E. Turner	Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms.	VLSI	1991	DBLP BibTeX RDF
17	Geraint Jones, Mary Sheeran	Deriving Bit-Serial Circuits in Ruby.	VLSI	1991	DBLP BibTeX RDF
17	Steven C. Bass, G. M. Butler, R. L. Williams, F. Barlos, D. R. Miller	A bit-serial, floating point CORDIC processor in VLSI.	ICASSP	1991	DBLP DOI BibTeX RDF
17	Muzhong Wang, Ian F. Blake	Bit Serial Multiplication in Finite Fields.	SIAM J. Discret. Math.	1990	DBLP DOI BibTeX RDF
17	Thomas H. Cormen, Charles E. Leiserson	A Hyperconcentrator Swith for Routing Bit-Serial Messages.	J. Parallel Distributed Comput.	1990	DBLP DOI BibTeX RDF
17	Bertil Svensson, Tomas Nordström	Execution of neural network algorithms on an array of bit-serial processors.	ICPR (2)	1990	DBLP DOI BibTeX RDF
17	S. P. Johansen	A universal online bit-serial cell for parallel expression evaluation.	SPDP	1990	DBLP DOI BibTeX RDF
17	Richard H. Bayford	The bit-serial systolic back-projection engine (BSSBPE).	ASAP	1990	DBLP DOI BibTeX RDF
17	William Aiello, Frank Thomson Leighton, Bruce M. Maggs, Mark Newman	Fast Algorithms for Bit-Serial Routing on a Hypercube.	SPAA	1990	DBLP DOI BibTeX RDF
17	Masakatu Morii, Masao Kasahara, Douglas L. Whiting	Efficient bit-serial multiplication and the discrete-time Wiener-Hopf equation over finite fields.	IEEE Trans. Inf. Theory	1989	DBLP DOI BibTeX RDF
17	F. Balestro, Gilles Privat, M. S. Tawfik	A bit-serial approach to VLSI implementation of digital LDI ladder filters.	ICASSP	1989	DBLP DOI BibTeX RDF
17	David Smitley, Ken Iobst	Bit-Serial SIMD on the CM-2 and the Cray 2.	PPSC	1989	DBLP BibTeX RDF
17	Thomas J. Brosnan, Noel R. Strader II	Modular Error Detection for Bit-Serial Multiplication.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF
17	Henk Meijer, Selim G. Akl	Bit serial addition trees and their applications.	Computing	1988	DBLP DOI BibTeX RDF
17	Ronald G. Harber, Xiaobo Sharon Hu, J. Li, Steven C. Bass	The application of bit-serial CORDIC computational units to the design of inverse kinematics processors.	ICRA	1988	DBLP DOI BibTeX RDF
17	Rajat Roy, Magdy A. Bayoumi	A fault-tolerant bit-serial array structure for digital filters.	ICASSP	1988	DBLP DOI BibTeX RDF
17	P. A. Ramamoorthy, Brahmaji Potu	Bit serial systolic chip set for real-time image coding.	ICASSP	1987	DBLP DOI BibTeX RDF
17	Paul M. Chau, Kay-Cheung Chew, Walter H. Ku	A bit-serial floating-point complex multiplier-accumulator for fault-tolerant digital signal processing arrays.	ICASSP	1987	DBLP DOI BibTeX RDF
17	Y. S. Cheung, S. C. Leung	A second generation Silicon compiler for bit-serial signal processing architecture.	ICASSP	1987	DBLP DOI BibTeX RDF
17	Steven G. Smith, M. S. McGregor, Peter B. Denyer	Techniques to increase the computational throughput of bit-serial architectures.	ICASSP	1987	DBLP DOI BibTeX RDF
17	Peter Kornerup, David W. Matula	A bit-serial arithmetic unit for rational arithmetic.	IEEE Symposium on Computer Arithmetic	1987	DBLP DOI BibTeX RDF
17	Alan F. Murray, Anthony V. W. Smith, Zoe F. Butler	Bit-Serial Neural Networks.	NIPS	1987	DBLP BibTeX RDF
17	P. L. Shaffer	Implementation of a parallel extended Kalman filter using a bit-serial silicon compiler.	FJCC	1987	DBLP BibTeX RDF
17	Dik Lun Lee	A Word-Parallel, Bit-Serial Signature Processor for Superimposed Coding.	ICDE	1986	DBLP DOI BibTeX RDF
17	Brent E. Nelson, Christopher J. Read	A bit-serial VLSI vector quantizer.	ICASSP	1986	DBLP DOI BibTeX RDF
17	Steven G. Smith, Peter B. Denyer	Efficient bit-serial complex multiplication and sum-of-products computation using distributed arithmetic.	ICASSP	1986	DBLP DOI BibTeX RDF
17	Thomas H. Cormen, Charles E. Leiserson	A Hyperconcentrator Switch for Routing Bit-Serial Messages.	ICPP	1986	DBLP BibTeX RDF
17	Nikos Kanopoulos, G. Thomas Mitchell	Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors.	IEEE Des. Test	1984	DBLP DOI BibTeX RDF
17	Gregory H. Allen, Peter B. Denyer, David S. Renshaw	A bit serial linear array DFT.	ICASSP	1984	DBLP DOI BibTeX RDF
17	Richard W. Linderman, Peter P. Reusens, Paul M. Chau, Walter H. Ku	Digital signal processing capabilities of CUSP, a high performance bit-serial VLSI processor.	ICASSP	1984	DBLP DOI BibTeX RDF
17	Laurence E. Turner, Peter B. Denyer, David S. Renshaw	A bit serial LDI recursive digital filter.	ICASSP	1984	DBLP DOI BibTeX RDF
17	Nick Kanopoulos, G. Thomas Mitchell	Testing of Bit-Serial Signal Processors.	ITC	1983	DBLP BibTeX RDF
17	Alan F. Murray, Peter B. Denyer, David S. Renshaw	Self-Testing in Bit Serial VLSI Parts: High Coverage at Low Cost.	ITC	1983	DBLP BibTeX RDF
17	Elwyn R. Berlekamp	Bit-serial Reed - Solomon encoders.	IEEE Trans. Inf. Theory	1982	DBLP DOI BibTeX RDF
17	Dennis Mancl	Programming Languages for Bit-Serial Array Machines		1981	RDF
17	Anthony P. Reeves, John D. Bruner	Efficient Function Implementation for Bit-Serial Parallel.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF
15	Xin Cai, Martin A. Brooke	A compact CPU architecture for sensor signal processing.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung	Customizable elliptic curve cryptosystems.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
15	Robert Siegmund, Dietmar Müller 0001	Automatic Synthesis of Communication Controller Hardware from Protocol Specifications.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
15	Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor	A FPGA-based Library for On-Line Signal Processing.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	FFT, DSP, DCT, configurable computing, on-line arithmetic
15	Wen-Yu Tseng, Chin-Chou Chen, David S. L. Wei, Sy-Yen Kuo	Design and Implementation of a High Speed Parallel Architecture for ATM UNI.	ISPAN	1996	DBLP DOI BibTeX RDF	UNI, VLSI, Parallel architecture, ATM
14	Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito	Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Arash Reyhani-Masoleh, M. Anwar Hasan	Fault Detection Architectures for Field Multiplication Using Polynomial Bases.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	polynomial basis multiplier, Finite fields, error detection
14	Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici	Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
14	Roman Genov, Gert Cauwenberghs	Kerneltron: Support Vector 'Machine' in Silicon.	SVM	2002	DBLP DOI BibTeX RDF
14	Khaled Benkrid, Danny Crookes, Abdsamad Benkrid	Design and implementation of a novel algorithm for general purpose median filtering on FPGAs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
12	Zbigniew Kokosinski, Bartlomiej Malus	FPGA Implementations of a Parallel Associative Processor with Multi-Comparand Multi-Search Operations.	ISPDC	2008	DBLP DOI BibTeX RDF
12	Ashkan Olyaei, Roman Genov	Algorithmic Delta-Sigma-modulated FIR filter.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Chang Hoon Kim, Chun Pyo Hong, Soonhak Kwon	A Novel Arithmetic Unit over GF(2m) for Low Cost Cryptographic Applications.	HPCC	2005	DBLP DOI BibTeX RDF	VLSI, Cryptography, Finite Field, Multiplication, Division
12	Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama	Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic.	ISMVL	2005	DBLP DOI BibTeX RDF
12	Alireza Hodjat, David Hwang 0001, Ingrid Verbauwhede	A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks.	ITCC (1)	2005	DBLP DOI BibTeX RDF	security, Elliptic Curve Cryptography, side-channel attacks, Galois fields, hardware architecture
12	Arash Reyhani-Masoleh, M. Anwar Hasan	Towards fault-tolerant cryptographic computations over finite fields.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	polynomial basis multiplier, security, fault-tolerant computing, finite fields, Error correction
12	A. S. Nepomniaschaya, Zbigniew Kokosinski	Associative Graph Processor and Its Properties.	PARELEC	2004	DBLP DOI BibTeX RDF	associative parallel processor, bit-parallel processing, associative graph processing, multiple-search
12	Zbigniew Kokosinski, Wojciech Sikora	An FPGA Implementation of a Multi-comparand Multi-search Associative Processor.	FPL	2002	DBLP DOI BibTeX RDF
12	Arash Reyhani-Masoleh, M. Anwarul Hasan	Error Detection in Polynomial Basis Multipliers over Binary Extension Fields.	CHES	2002	DBLP DOI BibTeX RDF	polynomial basis multiplier, fault tolerant computing, Finite fields, error detection
12	Bernard Girau	Digital Hardware Implementation of 2D Compatible Neural Networks.	IJCNN (3)	2000	DBLP DOI BibTeX RDF
12	Bernard Girau	Building a 2D-Compatible Multilayer Neural Network.	IJCNN (2)	2000	DBLP DOI BibTeX RDF
12	Jyh-Huei Guo, Chin-Liang Wang, Hung-Chih Hu	Design and implementation of an RSA public-key cryptosystem.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
12	Tamás Szabó, Béla Fehér, Gábor Horváth 0001	Neural network implementation using distributed arithmetic.	KES (3)	1998	DBLP DOI BibTeX RDF
12	Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor	Finite field inversion over the dual basis.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
12	Luigi Dadda, Vincenzo Piuri, Renato Stefanelli	Multi-parallel convolvers.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
12	James D. Feldman, Louis C. Fulmer	RADCAP: an operational parallel processing facility.	AFIPS National Computer Conference	1974	DBLP DOI BibTeX RDF
9	Thomas J. Sullivan, Stephen R. Deiss, Tzyy-Ping Jung, Gert Cauwenberghs	A brain-machine interface using dry-contact, low-noise EEG sensors.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Turki F. Al-Somani, Alaaeldin Amin	High performance elliptic curve point operations with pipelined GF(2m) field multiplier.	AICCSA	2008	DBLP DOI BibTeX RDF
9	Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi	Comb Architectures for Finite Field Multiplication in F(2^m).	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	FPGA, elliptic curve cryptography, normal basis, redundant representation, Finite field multiplier
9	Giacomo de Meulenaer, François Gosset, Guerric Meurice de Dormale, Jean-Jacques Quisquater	Integer Factorization Based on Elliptic Curve Method: Towards Better Exploitation of Reconfigurable Hardware.	FCCM	2007	DBLP DOI BibTeX RDF
9	Tao Sheng, Mudar Sarem, Jingli Zhou	Memory Efficient and Low Complexity Variable Length Decoding for MPEG-4 Applications.	ICPP Workshops	2007	DBLP DOI BibTeX RDF
9	Arash Hariri, Arash Reyhani-Masoleh	Fault Detection Structures for the Montgomery Multiplication over Binary Extension Fields.	FDTC	2007	DBLP DOI BibTeX RDF
9	Dimitrios Kagaris, P. Karpodinis, Dimitris Nikolos	On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	William N. Chelton, Mohammed Benaissa	Limiting Flexibility in Multiplication over GF(2m): A Design Methodology.	SiPS	2006	DBLP DOI BibTeX RDF
9	Hyun-Sung Kim 0001, Sung-Woon Lee	Low Complexity Systolic Architecture for Modular Multiplication over GF(2m).	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF
9	Daeik D. Kim, Martin A. Brooke	Scalable delta-sigma modulator readout architecture for array-based sensor system.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Steffen Toscher, Thomas Reinemann, Roland Kasper	An Adaptive FPGA-Based Mechatronic Control System Supporting Partial Reconfiguration of Controller Functionalities.	AHS	2006	DBLP DOI BibTeX RDF
9	Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar	BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor.	ASYNC	2005	DBLP DOI BibTeX RDF
9	Steffen Toscher, Roland Kasper, Thomas Reinemann	Dynamic Reconfiguration of Mechatronic Real-Time Systems Based on Configuration State Machines.	IPDPS	2005	DBLP DOI BibTeX RDF
9	Benjamas Tongprasit, Kiyoto Ito, Tadashi Shibata	A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
9	Weisheng Chong, Masanori Hariyama, Michitaka Kameyama	Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.	ISVLSI	2004	DBLP DOI BibTeX RDF
9	Milos Drutarovský, Viktor Fischer	Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector.	FPL	2004	DBLP DOI BibTeX RDF
9	Haque Mohammad Munirul, Michitaka Kameyama	Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
9	Kuen Hung Tsoi, Ka Hei Leung, Philip Heng Wai Leong	Compact FPGA-based True and Pseudo Random Number Generators.	FCCM	2003	DBLP DOI BibTeX RDF
9	Roman Genov, Gert Cauwenberghs	Algorithmic partial analog-to-digital conversion in mixed-signal array processors.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
9	Naofumi Homma, Takafumi Aoki, Makoto Motegi, Tatsuo Higuchi 0001	A framework of evolutionary graph generation system and its application to circuit synthesis.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
9	Huapeng Wu, M. Anwarul Hasan, Ian F. Blake, Shuhong Gao	Finite Field Multiplier Using Redundant Representation.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	cyclotomic ring, redundant set, multiplier, Finite field arithmetic, normal basis, squaring
9	Ryan N. Schneider, Laurence E. Turner, Michal M. Okoniewski	Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method.	FPGA	2002	DBLP DOI BibTeX RDF
9	Viktor Fischer, Milos Drutarovský, Rastislav Lukac	Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware.	FPL	2002	DBLP DOI BibTeX RDF
9	Kibum Suh, Seongmo Park, Seongmin Kim, Bontae Koo, Igkyun Kim, Kyungsoo Kim, Hanjin Cho	An efficient architecture of DCTQ module in MPEG-4 video codec.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
9	Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen	A new group distributed arithmetic design for the one dimensional discrete Fourier transform.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
9	V. Boonsobhak, Apisak Worapishet	A pixel-level ADC with improved performance trade-off for high-speed CMOS imagers.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
9	Jie Chen 0002, K. J. Ray Liu	Efficient architecture and design of an embedded video coding engine.	IEEE Trans. Multim.	2001	DBLP DOI BibTeX RDF
9	Johnny Holmberg, Lennart Harnefors, Krister Landernäs, Svante Signell	Computational properties of LDI/LDD lattice filters.	ISCAS (2)	2001	DBLP DOI BibTeX RDF