Search results for "clocking"

Hits ?▲	Authors	Title	Venue	Year	Link
18	Sergio Ríos Aguilar	Intelligent Position Aware Mobile Services for Seamless and Non-Intrusive Clocking-in.	Int. J. Interact. Multim. Artif. Intell.	2014	DBLP DOI BibTeX RDF
18	Xuan Zhang 0001, Tao Tong, David M. Brooks, Gu-Yeon Wei	Evaluating Adaptive Clocking for Supply-Noise Resilience in Battery-Powered Aerial Microrobotic System-on-Chip.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
18	Raj K. Jana, Gregory L. Snider, Debdeep Jena	Energy-Efficient Clocking Based on Resonant Switching for Low-Power Computation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
18	Douglas Tougaw	A Clocking Strategy for Scalable and Fault-Tolerant QDCA Signal Distribution in Combinational and Sequential Devices.	Field-Coupled Nanocomputing	2014	DBLP DOI BibTeX RDF
18	Rui Policarpo Duarte, Christos-Savvas Bouganis	Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs.	ReConFig	2014	DBLP DOI BibTeX RDF
18	Rui Policarpo Duarte, Christos-Savvas Bouganis	Over-clocking of Linear Projection Designs through Device Specific Optimisations.	IPDPS Workshops	2014	DBLP DOI BibTeX RDF
18	Davide De Caro, Michele De Martino, Nicola Petra, Antonio G. M. Strollo	Analysis of Spread-Spectrum Clocking Modulations Under Synchronization Timing Constraint.	ApplePies	2014	DBLP DOI BibTeX RDF
18	Rui Policarpo Duarte, Christos-Savvas Bouganis	A Unified Framework for Over-Clocking Linear Projections on FPGAs under PVT Variation.	ARC	2014	DBLP DOI BibTeX RDF
18	Robert A. Groves, Phillip J. Restle, Alan J. Drake, David Shan, Michael G. R. Thomson	Optimization and modeling of resonant clocking inductors for the POWER8TM microprocessor.	CICC	2014	DBLP DOI BibTeX RDF
18	William Walker, Dennis Michael Fischette	Wireline clocking and equalization.	CICC	2014	DBLP DOI BibTeX RDF
18	Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew J. Turnquist, Mikko Kaltiokallio	A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS.	CICC	2014	DBLP DOI BibTeX RDF
18	Carlos Tokunaga, Joseph F. Ryan 0002, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De	5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.	ISSCC	2014	DBLP DOI BibTeX RDF
18	Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger	5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor.	ISSCC	2014	DBLP DOI BibTeX RDF
18	Visvesh S. Sathe 0001	Quasi-resonant clocking: a run-time control approach for true voltage-frequency-scalability.	ISLPED	2014	DBLP DOI BibTeX RDF
18	Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine	Two phase clocking subthreshold adiabatic logic.	ISCAS	2014	DBLP DOI BibTeX RDF
18	Ignatius Bezzam, Shoba Krishnan	A pulsed resonance clocking for energy recovery.	ISCAS	2014	DBLP DOI BibTeX RDF
18	Mike Bichan, Dustin Dunwell, Qiwei Wang, Anthony Chan Carusone	A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC.	ISCAS	2014	DBLP DOI BibTeX RDF
18	Ignatius Bezzam, Shoba Krishnan	Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches.	VLSID	2014	DBLP DOI BibTeX RDF
18	Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine	Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic.	APCCAS	2014	DBLP DOI BibTeX RDF
18	Xin Fan	GALS design methodology based on pausible clocking. (PDF / PS)		2014	RDF
18	Michael Vielhaber 0001	Computation of functions on n bits by asynchronous clocking of cellular automata.	Nat. Comput.	2013	DBLP DOI BibTeX RDF
18	R. R. Manikandan, Bharadwaj Amrutur	Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance.	IEEE Trans. Circuits Syst. II Express Briefs	2013	DBLP DOI BibTeX RDF
18	Ramen Dutta, Eric A. M. Klumperink, Xiang Gao 0002, Zhiyu Ru, Ronan A. R. van der Zee, Bram Nauta	Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic.	IEEE Trans. Circuits Syst. II Express Briefs	2013	DBLP DOI BibTeX RDF
18	Ali Mesgarani, Islam T. Abougindia, Suat U. Ay	A 6-bit 1.5GS/s pipelined binary search ADC with simplified clocking scheme.	MWSCAS	2013	DBLP DOI BibTeX RDF
18	Bernd Deutschmann	Spread spectrum clocking for emission reduction of charge pump applications.	EMC Compo	2013	DBLP DOI BibTeX RDF
18	Xuan Zhang 0001, Tao Tong, David M. Brooks, Gu-Yeon Wei	Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOS.	CICC	2013	DBLP DOI BibTeX RDF
18	Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai	Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits.	ISSCC	2013	DBLP DOI BibTeX RDF
18	Wai Kay Leong, Yin Xu, Ben Leong, Zixiao Wang	Mitigating egregious ACK delays in cellular data networks by eliminating TCP ACK clocking.	ICNP	2013	DBLP DOI BibTeX RDF
18	Anshuman Chandra	Special session 11B: Hot topic on-chip clocking - Industrial trends.	VTS	2013	DBLP DOI BibTeX RDF
18	José Ramón García Oya, Fernando Muñoz 0001, Antonio Torralba 0002, Antonio Jurado, Fernando J. Marquez, Enrique López-Morillo	Data Acquisition System based on Subsampling Using Multiple Clocking Techniques.	IEEE Trans. Instrum. Meas.	2012	DBLP DOI BibTeX RDF
18	Keisuke Inoue, Mineo Kaneko	A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
18	Wuhua Hu, Gaoxi Xiao	Self-clocking principle for congestion control in the Internet.	Autom.	2012	DBLP DOI BibTeX RDF
18	Xiaokuo Yang, Li Cai, Qiang Kang, Xiaohui Zhao	Clocking misalignment tolerance of pipelined magnetic QCA architectures.	Microelectron. J.	2012	DBLP DOI BibTeX RDF
18	Danny Dolev, Matthias Függer, Christoph Lenzen 0001, Markus Posch, Ulrich Schmid 0001, Andreas Steininger	FATAL+: A Self-Stabilizing Byzantine Fault-tolerant Clocking Scheme for SoCs	CoRR	2012	DBLP BibTeX RDF
18		Resonant Clocking Circuits for Reversible Computation	CoRR	2012	DBLP BibTeX RDF
18	Kwanyeob Chae, Saibal Mukhopadhyay	All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
18	Haven Blake Skinner, Xuchu Hu, Matthew R. Guthaus	Harmonic resonant clocking.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
18	Xin Fan 0003, Milos Krstic, Eckhard Grass, Birgit Sanders, Christoph Heer	Exploring pausible clocking based GALS design for 40-nm system integration.	DATE	2012	DBLP DOI BibTeX RDF
18	Manuel J. Barragan Asian, Gildas Léger, José L. Huertas	OBT for settling error test of sampled-data systems using signal-dependent clocking.	ETS	2012	DBLP DOI BibTeX RDF
18	Xin Fan 0003, Milos Krstic, Eckhard Grass	Performance Analysis of GALS Datalink Based on Pausible Clocking.	ASYNC	2012	DBLP DOI BibTeX RDF
18	Rui Policarpo Duarte, Christos-Savvas Bouganis	High-level linear projection circuit design optimization framework for FPGAs under over-clocking.	FPL	2012	DBLP DOI BibTeX RDF
18	Nilanjana Pradhan, Kunal Das, Debashis De	Diverse clocking strategy in MQCA.	RAIT	2012	DBLP DOI BibTeX RDF
18	Matthew R. Guthaus, Baris Taskin	High-Performance, Low-Power Resonant Clocking: Embedded tutorial.	ICCAD	2012	DBLP DOI BibTeX RDF
18	Gerrit den Besten, Shunichi Kaeriyama	High-speed wireline transceivers and clocking.	CICC	2012	DBLP DOI BibTeX RDF
18	Ken Chang, SeongHwan Cho	Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee.	ISSCC	2012	DBLP DOI BibTeX RDF
18	Anthony Hill, Hiroo Hayashi	Session 14 overview: Digital clocking and PLLs: High-performance digital subcommittee.	ISSCC	2012	DBLP DOI BibTeX RDF
18	Nathaniel J. August, Hyung-Jin Lee, Martin Vandepas, Rachael J. Parker	A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
18	Nasirul Chowdhury, Jeff Wight, Christopher Mozak, Nasser A. Kurd	Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
18	Yasuhiro Takahashi, Zhongyu Luo, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama	2PCDAL: Two-phase clocking dual-rail adiabatic logic.	APCCAS	2012	DBLP DOI BibTeX RDF
18	Jared Zerbe, Barry Daly, Lei Luo 0006, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara	A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
18	Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, Zhongfeng Wang	Design of Sequential Elements for Low Power Clocking System.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
18	Swaroop Ghosh, Kaushik Roy 0001	Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
18	Anita Kumari, Sanjukta Bhanja	Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
18	Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki	Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2011	DBLP DOI BibTeX RDF
18	Takumi Okuhira, Tohru Ishihara	Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits.	PATMOS	2011	DBLP DOI BibTeX RDF
18	Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin	Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power.	ICCAD	2011	DBLP DOI BibTeX RDF
18	Ali M. El-Husseini, Matthew Morrise	Clocking design automation in Intel's Core i7 and future designs.	ICCAD	2011	DBLP DOI BibTeX RDF
18	Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada	A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS.	ISSCC	2011	DBLP DOI BibTeX RDF
18	Behzad Mesgarzadeh, Iman Esmaeil Zadeh, Atila Alvandpour	A multi-segment clocking scheme to reduce on-chip EMI.	SoCC	2011	DBLP DOI BibTeX RDF
18	Nikolaos Andrikos	Clocking techniques for the reduction of EMI in digital circuits.		2011	RDF
18	Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001	Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
18	Naofumi Takagi, Masamitsu Tanaka	Comparisons of Synchronous-Clocking SFQ Adders.	IEICE Trans. Electron.	2010	DBLP DOI BibTeX RDF
18	Vinayak Honkote	Design Automation and Analysis of Resonant Rotary Clocking Technology.	ISVLSI	2010	DBLP DOI BibTeX RDF
18	Marco Ottavi, Salvatore Pontarelli, Erik DeBenedictis, Adelio Salsano, Peter M. Kogge, Fabrizio Lombardi	High throughput and low power dissipation in QCA pipelines using Bennett clocking.	NANOARCH	2010	DBLP DOI BibTeX RDF
18	James D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski	POWER7TM local clocking and clocked storage elements.	ISSCC	2010	DBLP DOI BibTeX RDF
18	Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu	Using variable clocking to reduce leakage in synchronous circuits.	ICCD	2010	DBLP DOI BibTeX RDF
18	Rajesh Kannan Megalingam, Shekhil Hassan Thavalengal, Tanmay Muralidhar Rao, Ashwin Mohan, Vivek Periye	Low power analysis of DLX processor datapath using a novel clocking scheme.	ICWET	2010	DBLP DOI BibTeX RDF
18	Vinayak Honkote, Baris Taskin	Skew analysis and bounded skew constraint methodology for rotary clocking technology.	ISQED	2010	DBLP DOI BibTeX RDF
18	Megalingam Rajesh Kannan, M. Arunkumar, V. Arjun Ashok, Krishnan Nived, C. J. Daniel	Power-Efficient Cache Design Using Dual-Edge Clocking Scheme in Sun OpenSPARC T1 and Alpha AXP Processors.	BAIP	2010	DBLP DOI BibTeX RDF
18	Spencer S. Kellis, Nathaniel Gaskin, Bennion Redd, Eric D. Marsman, Richard Brown 0003	Hybrid on-chip clocking for sensor nodes.	SoC	2010	DBLP DOI BibTeX RDF
18	Tamer A. Ali 0001, Dinesh Patil, Frankie Liu, Elad Alon, Jon K. Lexau, Chih-Kong Ken Yang, Ron Ho	Clocking Links in Multi-chip Packages: A Case Study.	Hot Interconnects	2010	DBLP DOI BibTeX RDF
18	Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon	A 10 MS/s 11-bit 0.19 mm2 Algorithmic ADC With Improved Clocking Scheme.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
18	Nasser A. Kurd, Praveen Mosalikanti, Mark Neidengard, Jonathan Douglas, Rajesh Kumar	Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
18	Zhengtao Yu 0002, Xun Liu	Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
18	Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy 0001	Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
18	Ibuki Mori, Yoshihisa Yamada, Santhos A. Wibowo, Masashi Kono, Haruo Kobayashi 0001, Yukihiro Fujimura, Nobukazu Takai, Toshio Sugiyama, Isao Fukai, Norihisa Onishi, Ichiro Takeda, Jun-Ichi Matsuda	EMI Reduction by Spread-Spectrum Clocking in Digitally-Controlled DC-DC Converters.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
18	Bryan Casper, Frank O'Mahony	Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links - A Tutorial.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
18	Paul T. M. van Zeijl, Manel Collados	On the Attenuation of DAC Aliases Through Multiphase Clocking.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
18	Katsuyuki Ikeuchi, Kosuke Sakaida, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya	Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test.	CICC	2009	DBLP DOI BibTeX RDF
18	Xin Fan 0003, Milos Krstic, Eckhard Grass	Analysis and optimization of pausible clocking based GALS design.	ICCD	2009	DBLP DOI BibTeX RDF
18	Xiao Y. Wang, Rajeev K. Dokania, Alyssa B. Apsel	Implementation of a Global Clocking Scheme for ULP Radio Networks.	ISCAS	2009	DBLP DOI BibTeX RDF
18	Takefumi Yoshikawa, Yoshihide Komatsu, Tsuyoshi Ebuchi, Takashi Hirata	Transceiver Macro with Spread-Spectrum Clocking Capability for AC-Coupled Cable Interfaces.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
18	Jihyun Lee, Hyungyu Park, Kyungshik Lim, Kwangil Lee	Cross-layer Design for Fast TCP ACK-Clocking over WiMedia UWB Networks.	IEEE Trans. Consumer Electron.	2008	DBLP DOI BibTeX RDF
18	Swaroop Ghosh, Patrick Ndai, Kaushik Roy 0001	A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking.	DATE	2008	DBLP DOI BibTeX RDF
18	Ting Wu 0003, Xudong Shi 0004, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, T. J. Chin, Jie Shen 0010, Rich Perego, Ken Chang	Clocking circuits for a 16Gb/s memory interface.	CICC	2008	DBLP DOI BibTeX RDF
18	Lin Zhang, Berkehan Ciftcioglu, Hui Wu	Active deskew in injection-locked clocking.	CICC	2008	DBLP DOI BibTeX RDF
18	Dennis Michael Fischette, Kimo Tam	Session 17 - Clocking circuits.	CICC	2008	DBLP DOI BibTeX RDF
18	Seung-Jun Bae, Young-Soo Sohn, Kwang-Il Park, Kyoung-Ho Kim, Dae-Hyun Chung, Jingook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim 0003, Hye-Ran Kim, Yong-Jae Shin, Cheol-Goo Park, Gil-Shin Moon, Ki-Woong Yeom, Kang-Young Kim, Jae-Young Lee, Hyang-Ja Yang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim	A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.	ISSCC	2008	DBLP DOI BibTeX RDF
18	Selçuk Köse, Emre Salman, Zeljko Ignjatovic, Eby G. Friedman	Pseudo-random clocking to enhance signal integrity.	SoCC	2008	DBLP DOI BibTeX RDF
18	Hanni Bagnordi, Mabo Ito	Performance evaluation of a FFT using adpative clocking.	SoCC	2008	DBLP DOI BibTeX RDF
18	Aihan Yin, Peizhou Zhang	Research and Simulation Analysis of Improved Dual-clocking Algorithm in EPON.	ISCSCT (2)	2008	DBLP DOI BibTeX RDF
18	José C. García 0001, Juan A. Montiel-Nelson, Saeid Nooshabadi	Low energy CMOS true single phase power supply clocking adiabatic differential cascode voltage switch logic circuit.	APCCAS	2008	DBLP DOI BibTeX RDF
18	Shih-Hsu Huang, Chia-Ming Chang 0002, Yow-Tyng Nieh	A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains.	J. Inf. Sci. Eng.	2007	DBLP BibTeX RDF
18	Allen B. Downey	TCP self-clocking and bandwidth sharing.	Comput. Networks	2007	DBLP DOI BibTeX RDF
18	Sohini Dasgupta, Alex Yakovle	Comparative analysis of GALS clocking schemes.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
18	Robert D. Mullins, Simon W. Moore	Demystifying Data-Driven and Pausible Clocking Schemes.	ASYNC	2007	DBLP DOI BibTeX RDF
18	Ruxandra-Liana Costea, Corneliu A. Marinov	Clocking and WTA design of a continuous time Hopfield net with parasitic capacitances.	ECCTD	2007	DBLP DOI BibTeX RDF
18	Moonsoo Kang, Jeonghoon Mo	Packet Transmission Order Based TCP Loss Recovery Algorithm: Extending Self Clocking Property to Resolve ACK Starvation.	WOWMOM	2007	DBLP DOI BibTeX RDF
18	Paul Madeira, Marc-Andre LaCroix, John Hogeboom	A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology.	ESSCIRC	2007	DBLP DOI BibTeX RDF
18	Shamik Das, Matthew F. Bauwens	Clocking nanocircuits for nanocomputers and other nanoelectronic systems.	NANOARCH	2007	DBLP DOI BibTeX RDF