Search results for "emulation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Ilya Ganusov, Martin Burtscher	Efficient emulation of hardware prefetchers via event-driven helper threading.	PACT	2006	DBLP DOI BibTeX RDF	prefetching, multi-core architectures, helper threading
19	Pablo García Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli	A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
19	In-Yeup Kong, Won-Joo Hwang	Design and Emulation of Integration Framework for Heterogeneous Wireless PAN Networks.	UCS	2006	DBLP DOI BibTeX RDF	Heterogeneous WPAN, Integration, Framework, Convergence
19	David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil	Fast Emulation of Permanent Faults in VLSI Systems.	FPL	2006	DBLP DOI BibTeX RDF
19	Lucas Nussbaum, Olivier Richard	Lightweight emulation to study peer-to-peer systems.	IPDPS	2006	DBLP DOI BibTeX RDF
19	P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis	A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
19	Huizhou Zhao, Wei Yan 0007, Tong Zhao 0001, Xiaoming Li 0001	Wireless Multi-hop Network Scenario Emulation with MinMax Error.	LCN	2006	DBLP DOI BibTeX RDF
19	Elena Gabriela Barrantes, David H. Ackley, Stephanie Forrest, Darko Stefanovic	Randomized instruction set emulation.	ACM Trans. Inf. Syst. Secur.	2005	DBLP DOI BibTeX RDF	Automated diversity, randomized instruction sets, software diversity
19	Albrecht Mayer, Harry Siebert, Klaus D. McDonald-Maier	Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs.	DATE	2005	DBLP DOI BibTeX RDF
19	Michael Matthes 0001, Holger Biehl, Michael Lauer, Oswald Drobnik	MASSIVE: An Emulation Environment for Mobile Ad-Hoc Networks.	WONS	2005	DBLP DOI BibTeX RDF
19	Il-Gu Lee, Seungbeom Lee, Sin-Chong Park	Effective Co-Verification of IEEE 802.11a MAC/PHY Combining Emulation and Simulation Technology.	Annual Simulation Symposium	2005	DBLP DOI BibTeX RDF
19	Oumer M. Teyeb, Malek Boussif, Troels B. Sørensen, Jeroen Wigard, Preben E. Mogensen	Emulation Based Performance Investigation of FTP File Downloads over UMTS Dedicated Channels.	ICN (1)	2005	DBLP DOI BibTeX RDF
19	Cheng-Hong Yang 0001, Li-Yeh Chuang, Shyang-Lung Lin, Chi-Min Wang	A Wireless Emulation Management System for Learning Mandarin Phonetic and Chanjei Morse Code.	ICALT	2005	DBLP DOI BibTeX RDF
19	Paul R. Schumacher, Marco Mattavelli, Adrian Chirila-Rus, Robert D. Turney	A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs.	ICME	2005	DBLP DOI BibTeX RDF
19	Qingyan Liu, Chika O. Nwankpa	Applications of operational transconductance amplifier in power system analog emulation.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
19	Yue Li 0019, Depei Qian, Chunxiao Xing, Ying He 0002	The PARNEM: Using Network Emulation to Predict the Correctness and Performance of Applications.	GCC	2005	DBLP DOI BibTeX RDF
19	Fatih Kocan, Mehmet Hadi Gunes	Acyclic circuit partitioning for path delay fault emulation.	AICCSA	2005	DBLP DOI BibTeX RDF
19	James Aweya, Michel Ouellette, Delfin Y. Montuno, Jeganathan Markandu, Karin Sundstrom, Kent Felske	Circuit emulation services over ethernet-part 2: prototype and experimental results.	Int. J. Netw. Manag.	2004	DBLP DOI BibTeX RDF
19	Glenn Judd, Peter Steenkiste	Repeatable and realistic wireless experimentation through physical emulation.	Comput. Commun. Rev.	2004	DBLP DOI BibTeX RDF
19	Roland Wischnewski, Eckhard Freund	COSIMIR© Transport: Modeling, Simulation and Emulation of Modular Carrier based Transport Systems.	ICRA	2004	DBLP DOI BibTeX RDF
19	Lewis Girod, Thanos Stathopoulos, Nithya Ramanathan, Jeremy Elson, Deborah Estrin, Eric Osterweil, Tom Schoellhammer	A system for simulation, emulation, and deployment of heterogeneous sensor networks.	SenSys	2004	DBLP DOI BibTeX RDF	EmStar, real code simulation, sensor networks, TinyOS
19	Swapan Bhattacharyya, Joydeep Bhattacharyya, Adrish Ray Chaudhuri	ASET: A Formal Model for System Emulation and Verification.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
19	Angelos Bilas, Courtney R. Gibson, Reza Azimi, Rosalia Christodoulopoulou, Peter Jamieson	Using System Emulation to Model Next-Generation Shared Virtual Memory Clusters.	Clust. Comput.	2003	DBLP DOI BibTeX RDF	high-bandwidth interconnects, distributed shared memory, parallel systems, clusters of workstations, low-latency
19	Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi	A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation.	DSN	2003	DBLP DOI BibTeX RDF
19	Colin J. Fidge	Verifying Emulation of Legacy Mission Computer Systems.	FME	2003	DBLP DOI BibTeX RDF
19	Seyed Ghassem Miremadi, Ali Reza Ejlali	Switch Level Fault Emulation.	FPL	2003	DBLP DOI BibTeX RDF
19	Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Allen Chen, Nathan Chan, Robert W. Brodersen, Borivoje Nikolic	Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
19	Aidan J. Delaney, Thomas J. Naughton	Emulation of an unconventional model of computation in Java.	PPPJ/IRE	2002	DBLP BibTeX RDF
19	Csaba Attila Boer, Alexander Verbraeck, Hans P. M. Veeke	Real-time control: the possible role of a backbone architecture in real-time control and emulation.	WSC	2002	DBLP DOI BibTeX RDF
19	Dawid Kurzyniec, Vaidy S. Sunderam, Mauro Migliardi	PVM Emulation in the Harness Metacomputing Framework - Design and Performance Evaluation.	CCGRID	2002	DBLP DOI BibTeX RDF
19	Michael Greenwald	Two-handed emulation: how to build non-blocking implementation of complex data-structures using DCAS.	PODC	2002	DBLP DOI BibTeX RDF
19	Jorge Muruzábal	On the Emulation of Kohonen's Self-Organization via Single-Map Metropolis-Hastings Algorithms.	International Conference on Computational Science (2)	2001	DBLP DOI BibTeX RDF
19	Oliver Bringmann 0001, Wolfgang Rosenstiel, Carsten Menn	Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation.	DATE	2000	DBLP DOI BibTeX RDF
19	Thierry Lafage, André Seznec	Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note).	Euro-Par	2000	DBLP DOI BibTeX RDF
19	Mauro Migliardi, Vaidy S. Sunderam	PVM Emulation in the Harness Metacomputing System: A Plug-in Based Approach.	PVM/MPI	1999	DBLP DOI BibTeX RDF
19	Adger E. Harvin III, José G. Delgado-Frias	A Dictionary Machine Emulation on a VLSI Computing Tree System.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	tree architectures, VLSI, data structure, pipeline computing, bit-serial, Dictionary machines
19	Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang	Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
19	Martin C. Herbordt, Owais Kidwai, Charles C. Weems	Preprototyping SIMD Coprocessors Using Virtual Machine Emulation and Trace Compilation.	SIGMETRICS	1997	DBLP DOI BibTeX RDF
19	Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel	Co-Emulation and Debugging of HW/SW-Systems.	ISSS	1997	DBLP DOI BibTeX RDF
19	Chunghee Kim, Hyunchul Shin	A performance-driven logic emulation system: FPGA network design and performance-driven partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
19	Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel	Breakpoints and Breakpoint Detection in Source Level Emulation.	ISSS	1996	DBLP DOI BibTeX RDF
19	Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof	Local ratio cut and set covering partitioning for huge logic emulation systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
19	Francisco Castillo, Jose A. García 0003, Juan Manuel Moreno, Joan Cabestany	A Coprocessor Card for Fast Neural Network Emulation.	IWANN	1995	DBLP DOI BibTeX RDF
19	Alf-Christian Achilles	Optimal Emulation of Meshes on Meshes of Trees.	Euro-Par	1995	DBLP DOI BibTeX RDF
19	Joseph Varghese, Michael Butts, Jon Batcheller	An efficient logic emulation system.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
19	Lester F. Ludwig, Dennis F. Dunn	Laboratory for emulation and study of integrated and coordinated media communication.	Comput. Commun. Rev.	1987	DBLP DOI BibTeX RDF
19	Liba Svobodova, Roy Mattson	The role of emulation in performance measurement and evaluation.	SIGMETRICS	1976	DBLP DOI BibTeX RDF
19	Michael J. Flynn, Charles Neuhauser, Robert M. McClure	EMMY: an emulation system for user microprogramming.	AFIPS National Computer Conference	1975	DBLP DOI BibTeX RDF
16	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
16	Azalia Mirhoseini, Yousra Alkabani, Farinaz Koushanfar	Real time emulations: foundation and applications.	DAC	2010	DBLP DOI BibTeX RDF	real-time emultion, thermal modeling
16	Haris E. Psillakis	Sampled-Data Adaptive NN Tracking Control ofUncertainNonlinear Systems.	IEEE Trans. Neural Networks	2009	DBLP DOI BibTeX RDF
16	Paul Johnson, Ehsan Nourbakhsh, T. Ryan Burchfield, Jeff Dix, Ravi Prakash 0001, Subbarayan Venkatesan, Neeraj Mittal	ASSERT: Advanced wireleSS Environment Research Testbed.	SenSys	2009	DBLP DOI BibTeX RDF	wireless, sensor, testbeds, ASSERT
16	Brendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire	A Hardware Accelerated Simulation Environment for Spiking Neural Networks.	ARC	2009	DBLP DOI BibTeX RDF	FPGAs, reconfiguration, spiking neural networks, online training
16	Changbin Liu, Ricardo Correa, Xiaozhou Li, Prithwish Basu, Boon Thau Loo, Yun Mao	Declarative Policy-based Adaptive MANET Routing.	ICNP	2009	DBLP DOI BibTeX RDF
16	Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu	Active Cache Emulator.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Timothée Maret, Raphaël Kummer, Peter G. Kropf, Jean-Frédéric Wagen	Freemote Emulator: A Lightweight and Visual Java Emulator for WSN.	WWIC	2008	DBLP DOI BibTeX RDF	Lightweight Emulator, Java Based Motes, Freemote, Wireless Sensor Networks
16	Huiming Wang, Xingang Shi, Zhiliang Wang, Xia Yin, Jianping Wu	Performance testing of Mobile IPv6 protocol.	ISCC	2008	DBLP DOI BibTeX RDF
16	Roman Chertov, Sonia Fahmy, Ness B. Shroff	A Device-Independent Router Model.	INFOCOM	2008	DBLP DOI BibTeX RDF
16	Andrea Pellegrini, Kypros Constantinides, Dan Zhang 0004, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin	CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework.	ICCD	2008	DBLP DOI BibTeX RDF
16	Vladimir M. Krasnopolsky, Michael S. Fox-Rabinovitz, Alexei A. Belochitski	Using neural network emulations of model physics in numerical model ensembles.	IJCNN	2008	DBLP DOI BibTeX RDF
16	Alaa Seddik-Ghaleb, Yacine Ghamri-Doudane, Sidi-Mohammed Senouci	TCP computational energy cost within wireless Mobile Ad Hoc Network.	LCN	2008	DBLP DOI BibTeX RDF
16	Laszlo Kis, Gergely Regula, Béla Lantos	Design and hardware-in-the-loop test of the embedded control system of an indoor quadrotor helicopter.	WISES	2008	DBLP DOI BibTeX RDF
16	Jae-Wan Jang, Jin-Soo Kim 0001	Design issues and performance comparisons in supporting the sockets interface over user-level communication architecture.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	Sockets interface, cLAN, Interconnection network, VIA, User-level communication
16	Andy J. Wellings, Alan Burns 0001, Osmar Marchi dos Santos, Benjamin M. Brosgol	Integrating Priority Inheritance Algorithms in the Real-Time Specification for Java.	ISORC	2007	DBLP DOI BibTeX RDF
16	Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh	An FPGA-based Pentium in a complete desktop system.	FPGA	2007	DBLP DOI BibTeX RDF	pentium®, FPGA, emulator, accelerator, processor
16	John Wawrzynek	Adventures with a Reconfigurable Research Platform.	FPL	2007	DBLP DOI BibTeX RDF
16	Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz	RAMP Blue: A Message-Passing Manycore System in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
16	Seongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer 0001, Li Zhao 0002, W. Cohen	Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance.	ISPASS	2007	DBLP DOI BibTeX RDF	memory hierarchy model, full-system simulation acceleration, operating system performance characterization, operating system performance prediction, computer hardware complexity, cycle-accurate processor system simulation overheads, system libraries, OS service performance behavior, processor hierarchy model, Linux, software complexity
16	Shih-Hsiang Lo, Jiun-Hung Ding, Sheng-Je Hung, Jin-Wei Tang, Wei-Lun Tsai, Yeh-Ching Chung	SEMU: A Framework of Simulation Environment for Wireless Sensor Networks with Co-simulation Model.	GPC	2007	DBLP DOI BibTeX RDF	hardware and software co-simulation, Simulator, wireless sensor networks, dynamic binary translation
16	Francisco Bernardo, Nemanja Vucevic, Lukasz Budzisz, Anna Umbert	A beyond 3G real-time testbed for an All-IP heterogeneous network.	MOBIWAC	2007	DBLP DOI BibTeX RDF	real-time, testbed, heterogeneous networks, end-to-end QoS, beyond 3G
16	Kaori Maeda, Masahide Ishino, Eitaro Kohno, Takashi Kishida	A Userland Network Emulator with Packet Capture and Replay.	SAINT	2007	DBLP DOI BibTeX RDF
16	David Castells-Rufas, Jordi Carrabina	Jumble: A Hardware-in-the-Loop Simulation System for JHDL.	FCCM	2007	DBLP DOI BibTeX RDF
16	Gábor Németh, Peter Tarján, Gergely Biczók, Ferenc Kubinszky, Andras Veres	Measuring high-speed TCP performance during mobile handovers.	LCN	2007	DBLP DOI BibTeX RDF
16	Roman Obermaisser	Reuse of CAN-Based Legacy Applications in Time-Triggered Architectures.	IEEE Trans. Ind. Informatics	2006	DBLP DOI BibTeX RDF
16	Michele C. Weigle, Prashanth Adurthi, Félix Hernández-Campos, Kevin Jeffay, F. Donelson Smith	Tmix: a tool for generating realistic TCP application workloads in ns-2.	Comput. Commun. Rev.	2006	DBLP DOI BibTeX RDF	source-level modeling, synthetic traffic generation, ns
16	Pierre Vanhauwaert, Régis Leveugle, Philippe Roche	Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
16	Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia	Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
16	Otgonchimeg Buyanjargal, Jin Tae Kim, Seung Yong Lee, Youngmi Kwon	Performance Improvement of Grid Web Services based on Multi Homing Transport Layer.	CIT	2006	DBLP DOI BibTeX RDF
16	Weirong Jiang, Chao Zhang	A portable real-time emulator for testing multi-radio MANETs.	IPDPS	2006	DBLP DOI BibTeX RDF
16	Shiliang Hu, James E. Smith 0001	Reducing Startup Time in Co-Designed Virtual Machines.	ISCA	2006	DBLP DOI BibTeX RDF
16	Young-Su Kwon, C.-M. Kyung	ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
16	Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh K. Gupta 0001	Dynamic phase analysis for cycle-close trace generation.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	SimPoint, simulation, tracing, phase
16	Jae-Wan Jang, Jin-Soo Kim 0001	Supporting the Sockets Interface over User-Level Communication Architecture: Design Issues and Performance Comparisons.	ICPP	2005	DBLP DOI BibTeX RDF
16	Giuliano Antoniol, Yann-Gaël Guéhéneuc	Feature Identification: A Novel Approach and a Case Study.	ICSM	2005	DBLP DOI BibTeX RDF	dynamic and static analyses, Program understanding, meta-modelling, feature analysis
16	Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park	Instruction Based Testbench Architecture, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
16	Praveen Ikkurthy, John Shahbazian, Miguel A. Labrador, Kenneth J. Christensen	Testing Large Scale Streaming Internet Applications over Wireless LANs.	HASE	2004	DBLP DOI BibTeX RDF
16	Anne Bigot, Fabrice Charpentier, Helena Krupnova, Isabelle Sans	Deploying Hardware Platforms for SoC Validation: An Industrial Case Study.	FPL	2004	DBLP DOI BibTeX RDF
16	Jonathan Noel Tombs, Miguel Angel Aguirre Echánove, Fernando Muñoz 0001, Vicente Baena Lecuyer, Antonio Jesús Torralba Silgado, A. Fernandez-León, Francisco Tortosa	The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead.	FPL	2004	DBLP DOI BibTeX RDF
16	Maneesh Varshney, Rajive L. Bagrodia	Detailed models for sensor network simulations and their impact on network performance.	MSWiM	2004	DBLP DOI BibTeX RDF	simulation, sensor network
16	Robert Ricci, Chris Alfeld, Jay Lepreau	A solver for the network testbed mapping problem.	Comput. Commun. Rev.	2003	DBLP DOI BibTeX RDF
16	Trong-Yen Lee, Pao-Ann Hsiung, I-Mu Wu, Feng-Shi Su	RESS: Real-Time Embedded Software Synthesis and Prototyping Methodology.	RTCSA	2003	DBLP DOI BibTeX RDF
16	Hongyuan Shi, Harish Sethu	Greedy Fair Queueing: A Goal-Oriented Strategy for Fair Real-Time Packet Scheduling.	RTSS	2003	DBLP DOI BibTeX RDF
16	Giuseppe Desoli, Nikolay Mateev, Evelyn Duesterwald, Paolo Faraboschi, Josh Fisher	A New Facility for Dynamic Control of Program Execution: DELI.	EMSOFT	2002	DBLP DOI BibTeX RDF
16	Francesco Gregoretti, Roberto Passerone, Leonardo Maria Reyneri, Claudio Sansoè	A High Speed VLSI Architecture for Handwriting Recognition.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	image processing, parallel architectures, artificial neural networks, handwriting recognition, VLSI implementations
16	Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel	Power estimation approach for SRAM-based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
16	John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak	Efficient error detection, localization, and correction for FPGA-based debugging.	DAC	2000	DBLP DOI BibTeX RDF
16	Michael S. Boykin, Taieb Znati	Design and Analysis of a Quantum-based QoS-Aware Fair Share Server for Integrated Services Networks.	Annual Simulation Symposium	1999	DBLP DOI BibTeX RDF	service quantum, scheduling, Fair Queuing
16	Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar	A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.	VLSI Design	1999	DBLP DOI BibTeX RDF
16	Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang	An Asynchronous 2-D Discrete Cosine Transform Chip.	ASYNC	1998	DBLP DOI BibTeX RDF	DCT, asynchronous, threshold logic, bit-serial
16	Richard W. Wieler, Zaifu Zhang, Robert D. McLeod	Emulating static faults using a Xilinx based emulator.	FCCM	1995	DBLP DOI BibTeX RDF