Search results for "gate-level"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Gregor Leander, Thorben Moos, Amir Moradi 0001, Shahram Rasoolzadeh	The SPEEDY Family of Block Ciphers - Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
13	Yuan Yao, Tuna B. Tufan, Tarun Kathuria, Baris Ege, Ulkuhan Guler 0001, Patrick Schaumont	Pre-silicon Architecture Correlation Analysis (PACA): Identifying and Mitigating the Source of Side-channel Leakage at Gate-level.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
13	Konstantinos G. Liakos, Georgios K. Georgakilas, Fotis C. Plessas	Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning Analysis.	ISVLSI	2021	DBLP DOI BibTeX RDF
13	Tong Lu, Fang Zhou 0001, Ning Wu, Fen Ge, Benjun Zhang	Hardware Trojan Detection Method for Gate-Level Netlists Based on the Idea of Few-Shot Learning.	ICCT	2021	DBLP DOI BibTeX RDF
13	Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa	Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists.	IOLTS	2021	DBLP DOI BibTeX RDF
13	Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker	Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models.	DFT	2021	DBLP DOI BibTeX RDF
13	Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin, Thomas Lange, Maximilien Glorieux	Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis.	ISQED	2021	DBLP DOI BibTeX RDF
13	Motoki Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, Masahiro Iida, Hiroaki Yasuda, Hiroto Ito	R-GCN Based Function Inference for Gate-level Netlist.	IPSJ Trans. Syst. LSI Des. Methodol.	2020	DBLP DOI BibTeX RDF
13	Mohammad Taherifard, Mahdi Fazeli, Ahmad Patooghy	Scan-based attack tolerance with minimum testability loss: a gate-level approach.	IET Inf. Secur.	2020	DBLP DOI BibTeX RDF
13	Negin Zaraee, Boyou Zhou, Kyle Vigil, Mohammad M. Shahjamali, Ajay Joshi, M. Selim Ünlü	Gate-Level Validation of Integrated Circuits With Structured-Illumination Read-Out of Embedded Optical Signatures.	IEEE Access	2020	DBLP DOI BibTeX RDF
13	Shilpa Pendyala, Sheikh Ariful Islam, Srinivas Katkoori	Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling.	IEEE Trans. Emerg. Top. Comput.	2020	DBLP DOI BibTeX RDF
13	Guilherme Paim, Leandro Mateus Giacomini Rocha, Hussam Amrouch, Eduardo Antônio César da Costa, Sergio Bampi, Jörg Henkel	A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders.	IEEE Trans. Circuits Syst. Video Technol.	2020	DBLP DOI BibTeX RDF
13	Bon Woong Ku, Kyungwook Chang, Sung Kyu Lim	Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
13	Binod Kumar 0001, Kanad Basu, Masahiro Fujita, Virendra Singh	Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
13	K. Sravani, Rathnamala Rao	Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
13	Arunkumar Vijayan, Mehdi B. Tahoori, Krishnendu Chakrabarty	Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection.	ACM Trans. Design Autom. Electr. Syst.	2020	DBLP DOI BibTeX RDF
13	Jeremy Blackstone, Wei Hu 0008, Alric Althoff, Armaiti Ardeshiricham, Lu Zhang, Ryan Kastner	A Unified Model for Gate Level Propagation Analysis.	CoRR	2020	DBLP BibTeX RDF
13	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures.	IEICE Trans. Inf. Syst.	2020	DBLP DOI BibTeX RDF
13	Nils Albartus, Max Hoffmann 0001, Sebastian Temme, Leonid Azriel, Christof Paar	DANA Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2020	DBLP DOI BibTeX RDF
13	Yuan Yao, Tarun Kathuria, Baris Ege, Patrick Schaumont	Architecture Correlation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level.	IACR Cryptol. ePrint Arch.	2020	DBLP BibTeX RDF
13	Nils Albartus, Max Hoffmann 0001, Sebastian Temme, Leonid Azriel, Christof Paar	DANA - Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering.	IACR Cryptol. ePrint Arch.	2020	DBLP BibTeX RDF
13	Bijan Alizadeh, Yasaman Abadi	Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
13	Stavros Simoglou, Christos P. Sotiriou, Nikolaos Blias	Timing Errors in STA-based Gate-Level Simulation.	ASYNC	2020	DBLP DOI BibTeX RDF
13	Yanqing Zhang 0002, Haoxing Ren, Brucek Khailany	Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk).	ICCAD	2020	DBLP DOI BibTeX RDF
13	Qizhi Zhang, Jiaji He, Yiqiang Zhao, Xiaolong Guo	A Formal Framework for Gate- Level Information Leakage Using Z3.	AsianHOST	2020	DBLP DOI BibTeX RDF
13	Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue	32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
13	Tatsuki Kurihara, Kento Hasegawa, Nozomu Togawa	Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning Methods.	IOLTS	2020	DBLP DOI BibTeX RDF
13	Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer 0001	Representing Gate-Level SET Faults by Multiple SEU Faults at RTL.	IOLTS	2020	DBLP DOI BibTeX RDF
13	Rongliang Fu, Zhimin Zhang 0004, Guang-Ming Tang, Junying Huang, Xiaochun Ye, Dongrui Fan, Ninghui Sun	Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
13	Yuan Yao, Tarun Kathuria, Baris Ege, Patrick Schaumont	Architecture Correlation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level.	HOST	2020	DBLP DOI BibTeX RDF
13	Rachel Selina Rajarathnam, Yibo Lin, Yier Jin, David Z. Pan	ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist.	HOST	2020	DBLP DOI BibTeX RDF
13	Sheng-En David Lin, Dae Hyun Kim 0004	Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs.	IEEE Trans. Emerg. Top. Comput.	2019	DBLP DOI BibTeX RDF
13	Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita	Signal Selection Methods for Debugging Gate-Level Sequential Circuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2019	DBLP DOI BibTeX RDF
13	Burçin Çakir, Sharad Malik	Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit Embeddings.	ACM Trans. Design Autom. Electr. Syst.	2019	DBLP DOI BibTeX RDF
13	Sebastian Wallat, Nils Albartus, Steffen Becker 0003, Max Hoffmann 0001, Maik Ender, Marc Fyrbiak, Adrian Drees, Sebastian Maaßen, Christof Paar	Highway to HAL: Open-Sourcing the First Extendable Gate-Level Netlist Reverse Engineering Framework.	CoRR	2019	DBLP BibTeX RDF
13	Maoyuan Qin, Wei Hu 0008, Xinmu Wang, Dejun Mu, Baolei Mao	Theorem proof based gate level information flow tracking for hardware security verification.	Comput. Secur.	2019	DBLP DOI BibTeX RDF
13	Imran Hafeez Abbassi, Faiq Khalid, Osman Hasan, Awais Mehmood Kamboh	Using gate-level side channel parameters for formally analyzing vulnerabilities in integrated circuits.	Sci. Comput. Program.	2019	DBLP DOI BibTeX RDF
13	Kai Huang 0002, Yun He, Xiaowen Jiang 0001	Holistic hardware Trojan design of trigger and payload at gate level with rare switching signals eliminated.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
13	Tom J. Mannos, Brian Dziki, Moslema Sharif	Fault Testing a Synthesizable Embedded Processor at Gate Level using UltraScale FPGA Emulation.	FPGA	2019	DBLP DOI BibTeX RDF
13	Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka	Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application.	PReMI (2)	2019	DBLP DOI BibTeX RDF
13	Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin	The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications.	NORCAS	2019	DBLP DOI BibTeX RDF
13	Jitka Kocnová, Zdenek Vasícek	Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits.	GECCO (Companion)	2019	DBLP DOI BibTeX RDF
13	Pengyong Zhao, Qiang Liu 0011	Density-based Clustering Method for Hardware Trojan Detection Based on Gate-level Structural Features.	AsianHOST	2019	DBLP DOI BibTeX RDF
13	Ikki Nagaoka, Masamitsu Tanaka, Koji Inoue, Akira Fujimaki	A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic.	ISSCC	2019	DBLP DOI BibTeX RDF
13	Sebastian Wallat, Nils Albartus, Steffen Becker 0003, Max Hoffmann 0001, Maik Ender, Marc Fyrbiak, Adrian Drees, Sebastian Maaßen, Christof Paar	Highway to HAL: open-sourcing the first extendable gate-level netlist reverse engineering framework.	CF	2019	DBLP DOI BibTeX RDF
13	Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin	Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors.	AHS	2019	DBLP DOI BibTeX RDF
13	Xu Liu, Alessandro Bernardini, Ulf Schlichtmann, Xing Zhou	A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation.	ISQED	2019	DBLP DOI BibTeX RDF
13	Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa	Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists.	CyberICPS/SECPRE/SPOSE/ADIoT@ESORICS	2019	DBLP DOI BibTeX RDF
13	Swatilekha Majumdar	A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology.	VDAT	2019	DBLP DOI BibTeX RDF
13	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
13	Seyed Mohammad Sebt, Ahmad Patooghy, Hakem Beitollahi, Michel A. Kinsy	Circuit enclaves susceptible to hardware Trojans insertion at gate-level designs.	IET Comput. Digit. Tech.	2018	DBLP DOI BibTeX RDF
13	Inki Hong, Dae Hyun Kim 0004	Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
13	Jaya Dofe, Qiaoyan Yu	Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
13	Sheng-En David Lin, Dae Hyun Kim 0004	Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
13	Ryan LaRose	Overview and Comparison of Gate Level Quantum Software Platforms.	CoRR	2018	DBLP BibTeX RDF
13	Shahrzad Keshavarz, Falk Schellenberg, Bastian Richter 0001, Christof Paar, Daniel E. Holcomb	SAT-based Reverse Engineering of Gate-Level Schematics using Fault Injection and Probing.	CoRR	2018	DBLP BibTeX RDF
13	Yu-Yun Dai, Robert K. Brayton	Identifying Transparent Logic in Gate-Level Circuits.	Advanced Logic Synthesis	2018	DBLP DOI BibTeX RDF
13	Daniela Ritirc, Armin Biere, Manuel Kauers	Improving and extending the algebraic approach for verifying gate-level multipliers.	DATE	2018	DBLP DOI BibTeX RDF
13	Henry G. Dietz	A Gate-Level Approach To Compiling For Quantum Computers.	IGSC	2018	DBLP DOI BibTeX RDF
13	Shahrzad Keshavarz, Falk Schellenberg, Bastian Richter 0001, Christof Paar, Daniel E. Holcomb	SAT-based reverse engineering of gate-level schematics using fault injection and probing.	HOST	2018	DBLP DOI BibTeX RDF
13	Ankit Jindal, Binod Kumar 0001, Kanad Basu, Masahiro Fujita	ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis.	VLSID	2018	DBLP DOI BibTeX RDF
13	Travis Meade, Shaojie Zhang, Yier Jin	IP protection through gate-level netlist security enhancement.	Integr.	2017	DBLP DOI BibTeX RDF
13	Jeremy Schlachter, Vincent Camus, Krishna V. Palem, Christian C. Enz	Design and Applications of Approximate Circuits by Gate-Level Pruning.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
13	Siyuan Xu, Benjamin Carrión Schäfer	Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
13	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
13	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
13	Sandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du 0001, Sung Kyu Lim	Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
13	Elsa Gonsiorowski, Justin M. LaPre, Christopher D. Carothers	Automatic Model Generation for Gate-Level Circuit PDES with Reverse Computation.	ACM Trans. Model. Comput. Simul.	2017	DBLP DOI BibTeX RDF
13	Hassan Salmani	COTD: Reference-Free Hardware Trojan Detection and Recovery Based on Controllability and Observability in Gate-Level Netlist.	IEEE Trans. Inf. Forensics Secur.	2017	DBLP DOI BibTeX RDF
13	Xin Xie, Yangyang Sun, Hongda Chen 0004, Yong Ding 0003	Hardware Trojans classification based on controllability and observability in gate-level netlist.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
13	Thao Le 0001, Jia Di	Golden reference matching for gate-level netlist functionality identification.	MWSCAS	2017	DBLP DOI BibTeX RDF
13	Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar 0002, John Sartori	Software-based gate-level information flow security for IoT systems.	MICRO	2017	DBLP DOI BibTeX RDF
13	Abdul Rafay Khatri, Ali Hayek, Josef Börcsök	Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs.	ARC	2017	DBLP DOI BibTeX RDF
13	Yu Tai, Wei Hu 0008, Dejun Mu, Baolei Mao, Lantian Guo, Maoyuan Qin	A Simplifying Logic Approach for Gate Level Information Flow Tracking.	ChinaCom (2)	2017	DBLP DOI BibTeX RDF
13	Fuqiang Chen, Qiang Liu	Single-triggered hardware Trojan identification based on gate-level circuit structural characteristics.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier.	ISCAS	2017	DBLP DOI BibTeX RDF
13	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	Hardware Trojans classification for gate-level netlists using multi-layer neural networks.	IOLTS	2017	DBLP DOI BibTeX RDF
13	Yiting Chen, Dae Hyun Kim 0004	A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits.	ISQED	2017	DBLP DOI BibTeX RDF
13	Arkadiusz W. Luczyk	A method to manage unknown values generation and propagation during gate level simulations of multi-clock digital circuits.	MIXDES	2017	DBLP DOI BibTeX RDF
13	Andrew Becker, Wei Hu 0008, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne	Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking.	DAC	2017	DBLP DOI BibTeX RDF
13	Masaru Oya, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Masao Yanagisawa, Nozomu Togawa	Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2016	DBLP DOI BibTeX RDF
13	Wei Hu 0008, Baolei Mao, Jason Oberg, Ryan Kastner	Detecting Hardware Trojans with Gate-Level Information-Flow Tracking.	Computer	2016	DBLP DOI BibTeX RDF
13	Yu Tai, Wei Hu 0008, Huixiang Zhang, Dejun Mu, Xing-Li Huang	Generating optimized gate level information flow tracking logic for enforcing multilevel security.	Autom. Control. Comput. Sci.	2016	DBLP DOI BibTeX RDF
13	Jaya Dofe, Yuejun Zhang, Qiaoyan Yu	DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation.	ISVLSI	2016	DBLP DOI BibTeX RDF
13	A. V. Lapin, D. A. Bulakh, A. V. Korshunov, G. G. Kazennov	The use of Petri nets as the basis of algorithm for gate level digital circuits simulation.	EWDTS	2016	DBLP DOI BibTeX RDF
13	Anton Karputkin, Jaan Raik	A synthesis-agnostic behavioral fault model for high gate-level fault coverage.	DATE	2016	DBLP BibTeX RDF
13	Ghaith Tarawneh, Andrey Mokhov, Alex Yakovlev	Formal verification of clock domain crossing using gate-level models of metastable flip-flops.	DATE	2016	DBLP BibTeX RDF
13	Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello	Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed.	SAFECOMP Workshops	2016	DBLP DOI BibTeX RDF
13	Imran Hafeez Abbasi, Faiq Khalid Lodhi, Awais Mehmood Kamboh, Osman Hasan	Formal Verification of Gate-Level Multiple Side Channel Parameters to Detect Hardware Trojans.	FTSCS	2016	DBLP DOI BibTeX RDF
13	Parameswaran Ramanathan, Kewal K. Saluja	Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations.	ATS	2016	DBLP DOI BibTeX RDF
13	Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Diederik Verkest, Aaron Thean, Sung Kyu Lim	Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.	ISLPED	2016	DBLP DOI BibTeX RDF
13	Travis Meade, Yier Jin, Mark M. Tehranipoor, Shaojie Zhang	Gate-level netlist reverse engineering for hardware security: Control logic register identification.	ISCAS	2016	DBLP DOI BibTeX RDF
13	Kyle Juretus, Ioannis Savidis	Reducing logic encryption overhead through gate level key insertion.	ISCAS	2016	DBLP DOI BibTeX RDF
13	Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa	Hardware Trojans classification for gate-level netlists based on machine learning.	IOLTS	2016	DBLP DOI BibTeX RDF
13	Masaru Oya, Masao Yanagisawa, Nozomu Togawa	Redesign for untrusted gate-level netlists.	IOLTS	2016	DBLP DOI BibTeX RDF
13	Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas 0001, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar	Gate-level modelling of NBTI-induced delays under process variations.	LATS	2016	DBLP DOI BibTeX RDF
13	Kyle Juretus, Ioannis Savidis	Reduced Overhead Gate Level Logic Encryption.	ACM Great Lakes Symposium on VLSI	2016	DBLP DOI BibTeX RDF
13	Thao Le 0001, Jia Di, Mark M. Tehranipoor, Domenic Forte, Lei Wang 0003	Tracking Data Flow at Gate-Level through Structural Checking.	ACM Great Lakes Symposium on VLSI	2016	DBLP DOI BibTeX RDF
13	Sheng-En David Lin, Partha Pratim Pande, Dae Hyun Kim 0004	Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs.	ISQED	2016	DBLP DOI BibTeX RDF
13	MohammadSadegh Sadri, Andrea Bartolini, Luca Benini	Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level.	Integr.	2015	DBLP DOI BibTeX RDF