Search results for "reconfigurability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Wentai Liu, Thomas H. Hildebrandt, Ralph K. Cavin III	Hamiltonian Cycles in the Shuffle-Exchange Network.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	optimal embedding, shuffle permutation, exact equation, shuffle-exchange connected array, spare processors, fault-tolerance, parallel processing, fault tolerant computing, reconfigurability, redundancy, multiprocessor interconnection networks, directed graphs, Hamiltonian cycles, shuffle-exchange network
19	Peter J. Varman, I. V. Ramakrishnan	Optimal Matrix Multiplication on Fault-Tolerant VLSI Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	optimal matrix multiplication, fault-tolerant VLSI arrays, optimal-time algorithm, 2-D systolic algorithm, simulation, VLSI, fault tolerant computing, reconfigurability, testability, clock cycle
19	Sun-Yuan Kung, Shiann-Ning Jean, Chih-Wei Jim Chang	Fault-Tolerant Array Processors Using Single-Track Switches.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fabrication time processing, fault tolerant array processors, single-track switches, array grid model, reconfigurability theorem, run-time processing, propagation time, parallel processing, graph theory, graph theory, fault tolerant computing, yield enhancement
19	Woei Lin, Chuan-lin Wu	A Distributed Resource Management Mechanism for a Partitionable Multiprocessor System.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	homogeneous processing element pool, distributed resource management mechanism, partitionable multiprocessor system, physically independent subsystems, performance evaluation, parallel processing, parallel computations, parallel architectures, distributed processing, reconfigurability, multistage interconnection networks, operating systems (computers), performance simulation
19	Peter J. Varman, I. V. Ramakrishnan, Donald S. Fussell	A Robust Matrix-Multiplication Array.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	VLSI, robust, reconfigurability, matrix multiplication, Array processor, wafer-scale integration
10	Carlo Bertolli, Daniele Buono, Gabriele Mencagli, Massimo Torquati, Marco Vanneschi, Matteo Mordacchini, Franco Maria Nardini	Resource discovery support for time-critical adaptive applications.	IWCMC	2010	DBLP DOI BibTeX RDF	pervasive grid, high-performance computing, autonomic computing, resource discovery
10	Yibo Chen, Jishen Zhao, Yuan Xie 0001	3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory.	ISLPED	2010	DBLP DOI BibTeX RDF	non-volatile FPGA, phase-change memory, 3D IC
10	Brahim Hamid, Fatma Krichen	Model-based engineering for dynamic reconfiguration in DRTES.	ECSA Companion Volume	2010	DBLP DOI BibTeX RDF	model driven engineering, dynamic reconfiguration, meta-model, UML profiles, component-based architecture, distributed real time embedded systems
10	Ganesh Venkatesh, Jack Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steven Swanson, Michael Bedford Taylor	Conservation cores: reducing the energy of mature computations.	ASPLOS	2010	DBLP DOI BibTeX RDF	conservation core, heterogeneous many-core, utilization wall, patching
10	José A. Ceroni	Economic Rationalization of Automation Projects.	Handbook of Automation	2009	DBLP DOI BibTeX RDF
10	Gérard Morel, Jean-François Pétin, Timothy L. Johnson	Reliability, Maintainability, and Safety.	Handbook of Automation	2009	DBLP DOI BibTeX RDF
10	Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung	Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	2D filter design, FPGA, Singular Value Decomposition, reconfigurable logic
10	Paulo Leitão	Holonic Rationale and Bio-inspiration on Design of Complex Emergent and Evolvable Systems.	Trans. Large Scale Data Knowl. Centered Syst.	2009	DBLP DOI BibTeX RDF	Self-organization, Emergent Behavior, Bio-inspiration, Holonic Manufacturing Systems
10	Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha	A hybrid nano-CMOS architecture for defect and fault tolerance.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	nanotechnology, Defect tolerance, nanowires
10	Shuo Wang, Jianwei Dai, El-Sayed A. M. Hasaneen, Lei Wang 0003, Faquir C. Jain	Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	threshold voltage and quantum dot transistor, Low power
10	Bert Geelen, Vissarion Ferentinos, Francky Catthoor, Spyridon Toulatos, Gauthier Lafruit, Thanos Stouraitis, Rudy Lauwereins, Diederik Verkest	Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Wavelets, Dynamism, Loop transformations, Memory optimization
10	Laurent Gatet, Hélène Tap-Béteille, Francis Bony	Comparison Between Analog and Digital Neural Network Implementations for Range-Finding Applications.	IEEE Trans. Neural Networks	2009	DBLP DOI BibTeX RDF
10	Vipin Balachandran, Deepak P 0001, Deepak Khemani	Interpretable and reconfigurable clustering of document datasets by deriving word-based rules.	CIKM	2009	DBLP DOI BibTeX RDF	interpretable clustering
10	Douglas Brooks, Ayanna M. Howard	Mobility reconfiguration for terrain exploration using passive perception.	ICRA	2009	DBLP DOI BibTeX RDF
10	Paulo Leitão	Holonic Rationale and Self-organization on Design of Complex Evolvable Systems.	HoloMAS	2009	DBLP DOI BibTeX RDF	Biological-inspired Theories, Self-organization, Emergent behavior, Holonic Manufacturing Systems
10	Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	ZerehCache: armoring cache architectures in high defect density technologies.	MICRO	2009	DBLP DOI BibTeX RDF	fault-tolerant cache, process variation, manufacturing yield
10	Fabio Cancare, Marco D. Santambrogio, Donatella Sciuto	An application-centered design flow for self reconfigurable systems implementation.	ASP-DAC	2009	DBLP DOI BibTeX RDF
10	Jochen Strunk, Toni Volkmer, Klaus Stephan, Wolfgang Rehm, Heiko Schick	Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA.	IPDPS	2009	DBLP DOI BibTeX RDF
10	Rainer Buchty, David Kramer, Fabian Nowak, Wolfgang Karl	A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems.	ARC	2009	DBLP DOI BibTeX RDF
10	Ali Ahmadinia, Tughrul Arslan, Hernando Fernandez-Canque	Optimization of Reconfigurable Multi-core SOCs for Multi-standard Applications.	KES (2)	2009	DBLP DOI BibTeX RDF
10	M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli	Complete nanowire crossbar framework optimized for the multi-spacer patterning technique.	CASES	2009	DBLP DOI BibTeX RDF	MSPT, spacer technique, decoder, emerging technologies, gray code, crossbars, nanowires
10	N. Pete Sedcole, Peter Y. K. Cheung	Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modeling, FPGA, Delay, reconfiguration, process variation, yield
10	Philip Y. Paik, Vamsee K. Pamula, Krishnendu Chakrabarty	Adaptive Cooling of Integrated Circuits Using Digital Microfluidics.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Jie Tao 0001, Marcel Kunze, Fabian Nowak, Rainer Buchty, Wolfgang Karl	Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Simulation, Reconfigurable architecture, Multicore processor, Cache performance
10	Anne-Lise Gehin, Marcel Staroswiecki	Reconfiguration Analysis Using Generic Component Models.	IEEE Trans. Syst. Man Cybern. Part A	2008	DBLP DOI BibTeX RDF
10	Paulo Leitão, Francisco J. Restivo	Implementation of a Holonic Control System in a Flexible Manufacturing System.	IEEE Trans. Syst. Man Cybern. Part C	2008	DBLP DOI BibTeX RDF
10	Ozgur Sinanoglu	Scan Architecture With Align-Encode.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
10	Emre Yetginer, Ezhan Karasan	Dynamic Wavelength Allocation in IP/WDM Metro Access Networks.	IEEE J. Sel. Areas Commun.	2008	DBLP DOI BibTeX RDF
10	Luis Miguel Contreras-Medina, René de Jesús Romero-Troncoso, Jose de Jesus Rangel-Magdaleno, Jesus Roberto Millan-Almaraz	FPGA based multiple-channel vibration analyzer for industrial applications with reconfigurable post-processing capabilities for automatic failure detection on machinery.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, embedded systems, vibration analysis
10	Narges Bani Asadi, Teresa H. Meng, Wing Hung Wong	Reconfigurable computing for learning Bayesian networks.	FPGA	2008	DBLP DOI BibTeX RDF	Bayesian networks, reconfigurable computing, Markov chain Monte Carlo
10	Harald Heinecke, Werner Damm, Bernhard Josko, Alexander Metzner, Hermann Kopetz, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale	Software Components for Reliable Automotive Systems.	DATE	2008	DBLP DOI BibTeX RDF
10	Wenjing Rao, Alex Orailoglu	Towards fault tolerant parallel prefix adders in nanoelectronic systems.	DATE	2008	DBLP DOI BibTeX RDF
10	Laurent Alaus, Dominique Noguet, Jacques Palicot	A Reconfigurable LFSR for Tri-standard SDR Transceiver, Architecture and Complexity Analysis.	DSD	2008	DBLP DOI BibTeX RDF
10	Gwo Giun Lee, He-Yuan Lin, Ming-Jiun Wang, Bo-Han Chen, Yuan-Long Cheng	On the verification of multi-standard SoC'S for reconfigurable video coding based on algorithm/architecture co-exploration.	SiPS	2008	DBLP DOI BibTeX RDF
10	Bert Geelen, Aris Ferentinos, Francky Catthoor, Gauthier Lafruit, Diederik Verkest	Spatial locality trade-offs of wavelet-based applications in dynamic execution environments.	ICASSP	2008	DBLP DOI BibTeX RDF
10	Stefania Gnesi	Software Engineering: Ugo Montanari's Main Contributions and Introduction to the Section.	Concurrency, Graphs and Models	2008	DBLP DOI BibTeX RDF
10	Young-Su Kwon, Bontae Koo, Nak-Woong Eum	Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor.	FPL	2008	DBLP DOI BibTeX RDF
10	Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dudek, Thomas Dowrick, Liam McDaid	Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks.	FPL	2008	DBLP DOI BibTeX RDF
10	Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard	Reconfigurable hardware: The holy grail of matching performance with programming productivity.	FPL	2008	DBLP DOI BibTeX RDF
10	Karel Bruneel, Dirk Stroobandt	Automatic generation of run-time parameterizable configurations.	FPL	2008	DBLP DOI BibTeX RDF
10	Florian Dittmann 0001, Stefan Frank, Simon Oberthür	Algorithmic skeletons for the design of partially reconfigurable systems.	IPDPS	2008	DBLP DOI BibTeX RDF
10	Thomas Jacob Koickal, Luiz Carlos Gouveia, Alister Hamilton	Bio-inspired Event Coded Configurable Analog Circuit Block.	ICES	2008	DBLP DOI BibTeX RDF
10	Andres Upegui, Andrés Pérez-Uribe, Yann Thoma, Eduardo Sanchez	Neural Development on the Ubichip by Means of Dynamic Routing Mechanisms.	ICES	2008	DBLP DOI BibTeX RDF	ontogenetic circuits, synaptogenetic circuits, dynamic topology, neural plasticity, reconfigurable circuit, dynamic routing
10	Emilio Castillo, César Pedraza, Javier Castillo, Cristobal Camarero, José Luis Bosque, Rafael Menéndez de Llano, José Ignacio Martínez	SMILE: Scientific Parallel Multiprocessing based on Low-Cost Reconfigurable Hardware.	FCCM	2008	DBLP DOI BibTeX RDF
10	Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides	Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA.	ARC	2008	DBLP DOI BibTeX RDF	FPGA, Resource Constraint, Random Numbers, Multivariate Gaussian Distribution
10	Aveek Dutta, Jeff Fifield, Graham Schelle, Dirk Grunwald, Douglas C. Sicker	An intelligent physical layer for cognitive radio networks.	WICON	2008	DBLP DOI BibTeX RDF
10	Francesco Bruschi, Vincenzo Rana, Donatella Sciuto	An architecture for dynamically reconfigurable real time audio processing systems.	ESTIMedia	2008	DBLP DOI BibTeX RDF
10	Gerald L. Fudge, Mark A. Chivers, Sujit Ravindran, Ross E. Bland, Phillip E. Pace	A reconfigurable direct RF receiver architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Mark Hammerquist, Roman L. Lysecky	Design space exploration for application specific FPGAS in system-on-a-chip designs.	SoCC	2008	DBLP DOI BibTeX RDF
10	Chenggong Lv, Jun Wang 0059, Lu Liu, Weijia You	The Separation of Duty with Privilege Calculus.	RSKT	2008	DBLP DOI BibTeX RDF
10	Mohammad Hosseinabady, José L. Núñez-Yáñez	Fault-tolerant dynamically reconfigurable NoC-based SoC.	ASAP	2008	DBLP DOI BibTeX RDF
10	Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy 0001, Ranjani Narayan	Synthesis of application accelerators on Runtime Reconfigurable Hardware.	ASAP	2008	DBLP DOI BibTeX RDF
10	Mahdi Niamanesh, Rasool Jalili	A Formalism for Recongurability Analysis in Distributed Non-Blocking Components.	ICDCS Workshops	2008	DBLP DOI BibTeX RDF
10	Paul Grace, Gordon S. Blair, Carlos A. Flores-Cortés, Nelly Bencomo	Engineering complex adaptations in highly heterogeneous distributed systems.	Autonomics	2008	DBLP DOI BibTeX RDF	adaptation, middleware, reflection, heterogeneity
10	Ivanka Terzic, Munir Merdan, Alois Zoitl, Ingo Hegny	Modular assembly machine - ontology based concept.	ETFA	2008	DBLP DOI BibTeX RDF
10	Paul Grace, Danny Hughes 0001, Barry Porter, Gordon S. Blair, Geoff Coulson, François Taïani	Experiences with open overlays: a middleware approach to network heterogeneity.	EuroSys	2008	DBLP DOI BibTeX RDF	WSN, middleware, framework, overlay network
10	Nele Mentens, Benedikt Gierlichs, Ingrid Verbauwhede	Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration.	CHES	2008	DBLP DOI BibTeX RDF
10	Fariaz Karim	A peer-to-peer approach to providing QoS monitoring for web service activities.	Middleware (Companion)	2008	DBLP DOI BibTeX RDF	QoS, web service, middleware, P2P
10	Yang Cao, Hoda A. ElMaraghy, Ahmed Azab	Reconfigurable Control Structure for Robots in Assembly.	J. Intell. Robotic Syst.	2007	DBLP DOI BibTeX RDF	Reconfigurable control, Supervisory Control Switching System, Robotic system
10	Ali Ahmadinia	Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	free-space manager, routing-conscious placement, line-sweep technique, optimal runtime, field-programmable gate array (FPGA), lower bounds, Reconfigurable hardware, geometric optimization, module placement
10	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-Dependent Delay Testing of FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
10	Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere	Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
10	Angela L. Chiu, Gagan L. Choudhury, Robert D. Doverspike, Guangzhi Li	Restoration Design in IP over Reconfigurable All-Optical Networks.	NPC	2007	DBLP DOI BibTeX RDF	IP-over-Optical, ULH, ROADM, reconfigurable all-optical network, wavelength service, shared mesh restoration, restoration overbuild, traffic engineering, fast reroute, IP service
10	Proshanta Saha, Tarek A. El-Ghazawi	A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems.	MEMOCODE	2007	DBLP DOI BibTeX RDF
10	Farhad Aghili, Kourosh Parsa	Configuration Control and Recalibration of a New Reconfigurable Robot.	ICRA	2007	DBLP DOI BibTeX RDF
10	Jürgen Becker 0001, Adam Donlin, Michael Hübner 0001	New tool support and architectures in adaptive reconfigurable computing.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
10	Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi	Computing and design for software and silicon manufacturing.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
10	Santiago Rodriguez-Parera, André Bourdoux, François Horlin, Jordi Carrabina, Liesbet Van der Perre	Front-End ADC Requirements for Uniform Bandpass Sampling in SDR.	VTC Spring	2007	DBLP DOI BibTeX RDF
10	Jie Tao 0001, Kim D. Hoàng, Wolfgang Karl	CMP Cache Architecture and the OpenMP Performance.	IWOMP	2007	DBLP DOI BibTeX RDF
10	Grégory Gailliard, Eric Nicollet, Michel Sarlotte, François Verdier	Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM.	DATE	2007	DBLP DOI BibTeX RDF
10	Zhuan Ye, John Grosspietsch, Gokhan Memik	Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio.	DATE	2007	DBLP DOI BibTeX RDF
10	Tiong Aik Koh, Boon Chong Ng, Yong Liang Guan 0001, Tiffany Jing Li	Reconfigurable FPGA Implementation of Product Accumulate Codes.	SiPS	2007	DBLP DOI BibTeX RDF
10	Thomas Schmid 0002, Oussama Sekkat, Mani B. Srivastava	An experimental study of network performance impact of increased latency in software defined radios.	WINTECH	2007	DBLP DOI BibTeX RDF	GNU radio, IEEE 802.15.4, software defined radio
10	Gareth W. Morris, Matthew Aubury	Design Space Exploration of the European Option Benchmark Using HyperStreams.	FPL	2007	DBLP DOI BibTeX RDF
10	Xinming Duan, Yulu Yang, Mei Yang, Lei Li, Yingtao Jiang	Topology and Binary Routing Schemes of A PRDT-Based NoC.	ITNG	2007	DBLP DOI BibTeX RDF
10	Ashok Kumar Tummala, Parimal Patel	Distributed IDS using Reconfigurable Hardware.	IPDPS	2007	DBLP DOI BibTeX RDF
10	Giovanni Bartolomeo, Stefano Salsano, Nicola Blefari-Melazzi	Reconfigurable Systems with a User-Centric Focus.	SAINT Workshops	2007	DBLP DOI BibTeX RDF
10	Nahar Sultana, Ki-Moon Choi, Eui-nam Huh	Application Driven Cluster Based Group Key Management with Identifier in Mobile Wireless Sensor Network.	FGCN (1)	2007	DBLP DOI BibTeX RDF
10	Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung	Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
10	Proshanta Saha, Tarek A. El-Ghazawi	Software/Hardware Co-Scheduling for Reconfigurable Computing Systems.	FCCM	2007	DBLP DOI BibTeX RDF
10	Arne Hamann, Razvan Racu, Rolf Ernst	Methods for multi-dimensional robustness optimization in complex embedded systems.	EMSOFT	2007	DBLP DOI BibTeX RDF
10	Soheil Saifipoor, Behrouz Tork Ladani, Naser Nematbakhsh	A Dynamic Reconfigurable Web Service Composition Framework Using Reo Coordination Language.	ECOWS	2007	DBLP DOI BibTeX RDF
10	Marco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto	A novel SoC design methodology combining adaptive software and reconfigurable hardware.	ICCAD	2007	DBLP DOI BibTeX RDF
10	Onur Turkcu, Suresh Subramaniam 0001	Blocking Analysis of Limited-Reconfigurable Optical Networks.	ICCCN	2007	DBLP DOI BibTeX RDF
10	Ashwin Sampath, Hui Dai, Haitao Zheng 0001, Ben Y. Zhao	Multi-channel Jamming Attacks using Cognitive Radios.	ICCCN	2007	DBLP DOI BibTeX RDF
10	R. Mahesh 0001, A. Prasad Vinod 0001	Frequency Response Masking based Reconfigurable Channel Filters for Software Radio Receivers.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Christian Wicpalek, Thomas Mayer 0003, Linus Maurer, U. Vollenbruch, Tindaro Pittorino, Andreas Springer	Analysis of Spurious Emission and In-Band Phase Noise of an All Digital Phase Locked Loop for RF Synthesis using a Frequency Discriminator.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Vincent Brost, Fan Yang 0019, Michel Paindavoine	A modular VLIW Processor.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Gianmarco Girau, Andrea Tomatis, Fabio Dovis, Paolo Mulassano	Efficient Software Defined Radio Implementations of GNSS Receivers.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia	Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.	IOLTS	2007	DBLP DOI BibTeX RDF
10	Ould-cheikh Mourad, Si-Mohamed Lotfy, Noureddine Mehallegue, Ahmed Bouridane, Camel Tanougast	AES Embedded Hardware Implementation.	AHS	2007	DBLP DOI BibTeX RDF
10	Yong-Kyu Jung	Fault-recovery Non-FPGA-based Adaptable Computing System Design.	AHS	2007	DBLP DOI BibTeX RDF
10	Ahmed O. El-Rayis, Tughrul Arslan, Ahmet T. Erdogan	High Performance Embedded Reconfigurable Concatenated Convolution- Puncturing Fabric for 802.16.	AHS	2007	DBLP DOI BibTeX RDF
10	Björn Osterloh, Harald Michalik, Björn Fiethe, Frank Bubenhagen	Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application.	AHS	2007	DBLP DOI BibTeX RDF
10	Hsiao-Lan Wei, Eric T. G. Wang	Creating Strategic Value from Supply Chain Visibility- the Dynamic Capabilities View.	HICSS	2007	DBLP DOI BibTeX RDF