Search results for "silicon"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Viktor Schlosser	Imaging the transmission of light through a crystalline silicon wafer with a silicon detector array.	IECON	2013	DBLP DOI BibTeX RDF
18	Xin Li 0001, Fa Wang, Shupeng Sun, Chenjie Gu	Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits.	ICCAD	2013	DBLP DOI BibTeX RDF
18	Bahram Jalali, Nick K. Hon, Kevin K. Tsia	Periodically poled silicon (PePSi) for efficient and electronically-tuned nonlinear optics in silicon.	OFC/NFOEC	2013	DBLP BibTeX RDF
18	Michael L. Davenport, Jared F. Bauters, Molly Piels, Martijn J. R. Heck, Arnold Chen, Alexander W. Fang, John E. Bowers 0001	A 400 Gb/s WDM receiver using a low loss silicon nitride AWG integrated with hybrid silicon photodetectors.	OFC/NFOEC	2013	DBLP BibTeX RDF
18	Prasanjeet Das, Sandeep K. Gupta 0001	Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning.	VTS	2013	DBLP DOI BibTeX RDF
18	Mehdi Dehbashi	Debug automation from pre-silicon to post-silicon.		2013	RDF
18	Benjamin Backes, Colin McDonough, Larry Smith 0004, Wei Wang 0003, Robert E. Geer	Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits.	J. Electron. Test.	2012	DBLP DOI BibTeX RDF
18	Mehdi Dehbashi, Görschwin Fey	Automated debugging from pre-silicon to post-silicon.	DDECS	2012	DBLP DOI BibTeX RDF
18	Mile Ivanda, Maja Balarin, Ozren Gamulin, Vedran Derek, Davor Ristic, Svetozar Music, Mira Ristic, Kresimir Furic, Zorica Crnjak Orel	Porous silicon prepared by electrochemical etching of silicon eptaxial layer.	MIPRO	2012	DBLP BibTeX RDF
18	Bahareh Yaghootkar, Mahmoud Amouzgar, Mojtaba Kahrizi	Fabrication of silicon micro-rod array with controlled density and size distribution using porous silicon.	IECON	2012	DBLP DOI BibTeX RDF
18	Michael B. Taylor	Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse.	DAC	2012	DBLP DOI BibTeX RDF
18	Yuriy Vashpanov, Jae-Il Jung, Kae-Dal Kwack	Photo-EMF Sensitivity of Porous Silicon Thin Layer-Crystalline Silicon Heterojunction to Ammonia Adsorption.	Sensors	2011	DBLP DOI BibTeX RDF
18	Allon Adir, Shady Copty, Shimon Landa, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann	A unified methodology for pre-silicon verification and post-silicon validation.	DATE	2011	DBLP DOI BibTeX RDF
18	Wei Zhou, Max Guest, Darcy Hart	System level evaluation of Silicon imager based see-through Silicon application.	3DIC	2011	DBLP DOI BibTeX RDF
18	Liang Gu, W. Liu, S. L. Lei, S. B. Wang, Y. Y. Deng	Discharge light and carbonization distribution characteristics at XLPE-silicon rubber interface with silicon-grease in tracking failure test.	ICDIP	2011	DBLP DOI BibTeX RDF
18	Pei Ling Li, Chie Gau, Bau Tong Dai, Chien-Wei Liu	Study of silicon nitride film embedded with silicon quantum dots.	NEMS	2011	DBLP DOI BibTeX RDF
18	Ai Rong Chen, Peng Liu, Shou Zhong Wang	Silicon Content and Isothermal Quenching Process' Influence on High Silicon Cast Steel Organization and Performance.	ICDMA	2011	DBLP DOI BibTeX RDF
18	Allon Adir, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann	Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor.	DAC	2011	DBLP DOI BibTeX RDF
18	Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen 0024, George Bakewell	A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation.	DAC	2011	DBLP DOI BibTeX RDF
18	Andrew Alduino	Demonstration of a high speed 4-channel integrated silicon photonics WDM link with hybrid silicon lasers.	Hot Chips Symposium	2010	DBLP DOI BibTeX RDF
18	Yasuhiro Matsumoto, Mauricio Ortega-López, Frank Wünsch	HW-CVD deposited microcrystalline-silicon on crystalline-silicon solar cell with inverted heterojunction structure.	CCE	2010	DBLP DOI BibTeX RDF
18	Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita	Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging.	ICCD	2010	DBLP DOI BibTeX RDF
18	Luís da Silva Zambom, Ronaldo Domingues Mansano, Ana Paula Mousinho	Low-temperature deposition of silicon oxide and silicon nitride by reactive magnetron sputtering.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
18	Monem Krichen, Abdelaziz Zouari, Adel Ben Arab	A simple analytical model of thin films crystalline silicon solar cell with quasi-monocrystalline porous silicon at the backside.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
18	Zhizhong Yuan, Aleksei Anopchenko, Nicola Daldosso, Romain Guider, Daniel Navarro-Urrios, Alessandro Pitanti, Rita Spano, Lorenzo Pavesi	Silicon Nanocrystals as an Enabling Material for Silicon Photonics.	Proc. IEEE	2009	DBLP DOI BibTeX RDF
18	Ke Tao, Dexian Zhang, Yun Sun, Linshen Wang, Jingfang Zhao, Ying Xue, Yuanjian Jiang, Hongkun Cai, Yanping Sui, Jin Wang	Boron doped hydrogenated nanocrystalline silicon thin films prepared by layer-by-layer technique and its application in n-i-p flexible amorphous silicon thin film solar cells.	NEMS	2009	DBLP DOI BibTeX RDF
18	Paul S. Andry, Cornelia K. Tsang, Bucknell C. Webb, Edmund J. Sprogis, Steven L. Wright, Bing Dang, Dennis G. Manzer	Fabrication and characterization of robust through-silicon vias for silicon-carrier applications.	IBM J. Res. Dev.	2008	DBLP DOI BibTeX RDF
18	Godofredo García Salgado, R. Hernández, Javier Martínez, Tomás Díaz, Héctor Juárez, Enrique Rosendo, Reina Galeazzi, A. García, G. Juárez	Fabrication, characterization, and analysis of photodetectors metal-porous silicon with different geometry and thickness of the porous silicon layer.	Microelectron. J.	2008	DBLP DOI BibTeX RDF
18	Atsushi Waseda, Kenichi Fujii	Density Evaluation of Silicon Thermal-Oxide Layers on Silicon Crystals by the Pressure-of-Flotation Method.	IEEE Trans. Instrum. Meas.	2007	DBLP DOI BibTeX RDF
18	R. Rao, J. E. Bradby, S. Ruffell, J. S. Williams	Nanoindentation-induced phase transformation in crystalline silicon and relaxed amorphous silicon.	Microelectron. J.	2007	DBLP DOI BibTeX RDF
18	Raphael Tsu, D. Quinlan, K. Daneshvar	Silicon-O-M-O-silicon superlattice.	Microelectron. J.	2006	DBLP DOI BibTeX RDF
18	Liguo Chen, Tao Chen 0010, Lining Sun	The bond Strength Measurement of silicon-silicon bonding wafers Based on Crack Opening Method.	Int. J. Inf. Acquis.	2006	DBLP DOI BibTeX RDF
18	Gen-Wen Hsieh, Ching-Hsiang Tsai, Wei-Chih Lin	Anodic bonding of glass and silicon wafers with an intermediate silicon nitride film and its application to batch fabrication of SPM tip arrays.	Microelectron. J.	2005	DBLP DOI BibTeX RDF
18	Frédéric Marty, Lionel Rousseau, Bassam Saadany, B. Mercier, Olivier Français, Y. Mita, Tarik Bourouina	Advanced etching of silicon based on deep reactive ion etching for silicon high aspect ratio microstructures and three-dimensional micro- and nanostructures.	Microelectron. J.	2005	DBLP DOI BibTeX RDF
18	Brian Taba, Kwabena Boahen 0001	Silicon growth cones map silicon retina.	NIPS	2005	DBLP BibTeX RDF
18	B. Díaz, José A. Rodríguez 0004, Montse Riera, Andreu Llobera, Carlos Domínguez, Joaquín Tutor-Sánchez	Optical properties of silicon rich silicon oxides obtained by PECVD.	Microelectron. J.	2004	DBLP DOI BibTeX RDF
18	Matteo Cocuzza	Development of silicon and silicon carbide-based micro-electromechanical systems.		2004	RDF
18	Summer F. C. Tseng, Wei-Ting Kary Chien, Bing-Chu Cai	Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
18	Jackie Chan, Hei Wong, M. C. Poon, Chi-Wah Kok	Oxynitride gate dielectric prepared by thermal oxidation of low-pressure chemical vapor deposition silicon-rich silicon nitride.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
18	Tom Conlon, Mary Simpson	Silicon Valley versus Silicon Glen: the impact of computers upon teaching and learning: a comparative study.	Br. J. Educ. Technol.	2003	DBLP DOI BibTeX RDF
18	Jed Kolko	Silicon mountains, silicon molehills: geographic concentration and convergence of internet industries in the US.	Inf. Econ. Policy	2002	DBLP DOI BibTeX RDF
18	J. Barton, G. McCarthy, R. Doyle, K. Delaney, Enric Cabruja, Manuel Lozano 0003, Ana Collado, Joaquín Santander	Reliability evaluation of a silicon-on-silicon MCM-D package.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
18	Laurent Jalabert, Pierre Temple-Boyer, Gérard Sarrabayrouse, F. Cristiano, B. Colombeau, F. Voillot, C. Armand	Reduction of boron penetration through thin silicon oxide with a nitrogen doped silicon layer.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
18	Jan Sevenhans	Silicon radio integration: architectures and technology: from cartesian zero IF receive & transmit to polar zero I and Q, from silicon bipolar to bulk and SOI CMOS.	CICC	2000	DBLP DOI BibTeX RDF
18	Ferdinando Taddei	The Rotational Barriers of Groups Containing Silicon in Substituted Benzenes. A Theoretical Approach to the Silicon Substituent Effect.	J. Chem. Inf. Comput. Sci.	1998	DBLP DOI BibTeX RDF
18	Gordon E. Moore	The role of Fairchild in silicon technology in the early days of "Silicon Valley".	Proc. IEEE	1998	DBLP DOI BibTeX RDF
18	Jan Sevenhans, Bart Verstraeten, Graham Fletcher, Harry Dietrich, Winfried Rabe, Jean Luc Bacq, J. Varin, J. Dulongpont	Silicon germanium and silicon bipolar RF circuits for 2.7 V single chip radio transceiver integration.	CICC	1998	DBLP DOI BibTeX RDF
18	Andrew M. Odlyzko	Silicon Dreams and Silicon Bricks: The Continuing Evolution of Libraries.	Libr. Trends	1997	DBLP BibTeX RDF
18	Maria Grazia Albanesi	An example of integrated circuit design based on silicon compilation: the SCPC1 (Silicon Compiler Pyramidal Chip).	Recent Issues in Pattern Analysis and Recognition	1989	DBLP DOI BibTeX RDF
18	Ahmed Amine Jerraya	Contribution à la compilation de silicium et au compilateur SYCO. (Silicon compilation and the syco silicon compiler).		1989	RDF
18	Donald P. Seraphim, Andrew E. Brennemann, Francois Max d'Heurle, Harold L. Friedman	Electrochemical Phenomena in Thin Films of Silicon Dioxide on Silicon.	IBM J. Res. Dev.	1964	DBLP DOI BibTeX RDF
18	Atanu Chattopadhyay, Zeljko Zilic	Serial reconfigurable mismatch-tolerant clock distribution.	DAC	2009	DBLP DOI BibTeX RDF	process variation, clock skew, clock networks
18	Nicholas Callegari, Li-C. Wang, Pouria Bastani	Speedpath analysis based on hypothesis pruning and ranking.	DAC	2009	DBLP DOI BibTeX RDF	speedpath, data mining, timing analysis
18	Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao	Spare-cell-aware multilevel analytical placement.	DAC	2009	DBLP DOI BibTeX RDF	spare cells, placement, physical design
18	Rob Aitken, Erik Jan Marinissen	Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
18	Bart Vermeulen	Functional Debug Techniques for Embedded Systems.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
18	Pouria Bastani, Li-C. Wang, Magdy S. Abadir	Linking Statistical Learning to Diagnosis.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
18	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	Material Fatigue and Reliability of MEMS Accelerometers.	DFT	2008	DBLP DOI BibTeX RDF
18	Walid Ibrahim	A Novel EDA Tool for VLSI Test Vectors Management.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Test vectors selection, Genetic algorithms, Verification, VLSI, EDA tools
18	Kazuhiro Shimonomura, Takayuki Kushima, Tetsuya Yagi	Neuromorphic binocular vision system for real-time disparity estimation.	ICRA	2007	DBLP DOI BibTeX RDF
18	P. Yeung, A. Torres, P. Batra	Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor.	DATE	2007	DBLP DOI BibTeX RDF
18	Giacomo Indiveri, Elisabetta Chicca, Rodney J. Douglas	A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.	IEEE Trans. Neural Networks	2006	DBLP DOI BibTeX RDF
18	Paddy J. French	Integrated Microsystems in Industrial Applications.	SAMOS	2006	DBLP DOI BibTeX RDF	integrated sensors, packaging
18	Noah Bamford, Rekha Bangalore, Eric Chapman, Hector Chavez, Rajeev Dasari, Yinfang Lin, Edgar Jimenez	Challenges in System on Chip Verification.	MTV	2006	DBLP DOI BibTeX RDF
18	Giovanni De Micheli	Nanoelectronics: Challenges and Opportunities.	PATMOS	2006	DBLP DOI BibTeX RDF
18	Jean-Pierre Schoellkopf	ATRS: An Alternative Roadmap for Semiconductors, Technology Evolution and Impacts on System Architecture.	ASYNC	2006	DBLP DOI BibTeX RDF
18	Bhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao	Enabling Quality and Schedule Predictability in SoC Design using HandoffQC.	ISQED	2006	DBLP DOI BibTeX RDF
18	Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham	A Scheme for On-Chip Timing Characterization.	VTS	2006	DBLP DOI BibTeX RDF
18	Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin	Ultra low-cost defect protection for microprocessor pipelines.	ASPLOS	2006	DBLP DOI BibTeX RDF	defect-protection, reliability, pipelines, low-cost
18	K. Uday Bhaskar, M. Prasanth, V. Kamakoti 0001, Kailasnath Maneparambil	A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
18	Gary Smith 0001	A new era for CAD.	ISPD	2005	DBLP DOI BibTeX RDF
18	Udayan Mallik, R. Jacob Vogelstein, Eugenio Culurciello, Gert Cauwenberghs, Ralph Etienne-Cummings	A real-time spike-domain sensory information processing system [image processing applications].	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Kazuhiro Shimonomura, Tetsuya Yagi	A 100×100 pixels orientation-selective multi-chip vision system.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Nobuyuki Nishiguchi	An advance RTL to GDS2 design methodology for 90 nm and below system LSIs to solve timing closure, signal integrity and design for manufacturing.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
18	K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti 0001	A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	Jie Yang 0010, Luigi Capodieci, Dennis Sylvester	Advanced timing analysis based on post-OPC extraction of critical dimensions.	DAC	2005	DBLP DOI BibTeX RDF	process CD, layout, OPC, design flow
18	E. L. Meyer, E. E. van Dyk	Assessing the reliability and degradation of photovoltaic module performance parameters.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
18	Dan Hillman	Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm.	DATE	2004	DBLP DOI BibTeX RDF
18	Didier Keymeulen, Ricardo Salem Zebulum, Adrian Stoica, Vu Duong, Michael I. Ferguson	Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device.	FPL	2004	DBLP DOI BibTeX RDF
18	Kousik Sivakumar, Balaji Panchapakesan	Surface Oriented Self Assembled Growth of Carbon Nanotubes.	ICMENS	2004	DBLP DOI BibTeX RDF
18	Shreekant (Ticky) Thakkar	Battery life challenges on future mobile notebook platforms.	ISLPED	2004	DBLP DOI BibTeX RDF
18	Yukio Okuda	Panel Synopsis - Diagnosis Meets Physical Failure Analysis: How Long Can We Succeed?	ITC	2004	DBLP DOI BibTeX RDF
18	Mark Hopkins	Nomadic platform approach for wireless mobile multimedia.	DAC	2004	DBLP DOI BibTeX RDF
18	Kee-Keun Lee, Jiping He, Amarjit Singh, Bruce C. Kim	Benzocyclobutene (BCB) Based Intracortical Neural Implant.	ICMENS	2003	DBLP DOI BibTeX RDF
18	Ilkka Saastamoinen, M. Alho, Jari Nurmi	Buffer implementation for Proteo network-on-chip.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
18	Patrick Groeneveld	Physical Design Challenges for Billion Transistor Chips.	ICCD	2002	DBLP DOI BibTeX RDF
18	B. Chester Hwang	Trends of Key Advanced Device Technologies.	ARVLSI	1997	DBLP DOI BibTeX RDF	SIA roadmap, Sematech, TFSOI, graded-channel CMOS, complementary IC technology, 0.25 micron, CMOS integrated circuits, CMOS technology, Moore's law, GaAs, Si
18	E. Miranda, Leonardo Maria Reyneri	A CPWM Synapsis for Weighted Radial Basis Functions.	IWANN	1995	DBLP DOI BibTeX RDF
18	Antonio Abramo, Franco Venturi, Enrico Sangiorgi, Jack M. Higman, Bruno Riccò	A numerical method to compute isotropic band models from anisotropic semiconductor band structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
18	Meyer E. Nigri, Philip C. Treleaven	High Level Syntheses of Neural Network Chips.	IWANN	1993	DBLP DOI BibTeX RDF
18	C. Bernard Shung, Rajeev Jain, Ken Rimey, Edward Wang, Mani B. Srivastava, Brian C. Richards, Erik Lettang, Syed Khalid Azim, Lars E. Thon, Paul N. Hilfinger, Jan M. Rabaey, Robert W. Brodersen	An integrated CAD system for algorithm-specific IC design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
18	Johannes M. Mulder, Robert J. Portier, A. Srivastava	A framework for high-speed controller design.	MICRO	1990	DBLP BibTeX RDF
15	Andrew B. Kahng, Vijayalakshmi Srinivasan	Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Big chips, dark silicon, network scalability, thermal design power, large-scale designs, field-programmable gate arrays, hardware accelerators, dynamic voltage and frequency scaling, 3D integration, physical synthesis, clock network synthesis
15	Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu	DfT Architecture for 3D-SICs with Multiple Towers.	ETS	2011	DBLP DOI BibTeX RDF	three-dimensional stacking, 3D-SIC, multi-tower, DfT, wrapper, design-for-test, TSV, through-silicon via
15	David A. Laws	A Company of Legend: The Legacy of Fairchild Semiconductor.	IEEE Ann. Hist. Comput.	2010	DBLP DOI BibTeX RDF	Fairchild, Hoerni, Moore, Noyce, Silicon Valley, integrated circuit, Planar, Microelectronics, Semiconductor
15	Rong-xia Sun, Xiaofeng Chen 0005	The Design of the Laser Simulation Training Device.	WKDD	2010	DBLP DOI BibTeX RDF	semi-conductor laser machine, silicon light battery, ISD1420, soniferous display, SCM
15	N. Khalid, Jugdutt Singh, Hai Phuong Le, Kriyang Shah, John Devlin, Z. Sauli	Very High Q, NEMS Inductor for 12GHz Wireless Sensor Applications.	DELTA	2010	DBLP DOI BibTeX RDF	High Q inductor, Micro/Nano Electro-Mechanical Systems (MEMS/NEMS), Silicon-on-sapphire
15	Subhasish Mitra	Robust System Design.	VLSI Design	2010	DBLP DOI BibTeX RDF	Robust systems, IFRA, BISER, Built-In Soft Error Resilience, Circuit Failure Prediction, On-line Self-Test, Reliability, Validation, aging, soft errors, post-silicon validation
15	Wenchao Li 0001, Alessandro Forin, Sanjit A. Seshia	Scalable specification mining for verification and diagnosis.	DAC	2010	DBLP DOI BibTeX RDF	error localization, verification, formal specification, debugging, diagnosis, assertions, post-silicon validation
15	Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang	An efficient phase detector connection structure for the skew synchronization system.	DAC	2010	DBLP DOI BibTeX RDF	adjustable delay buffer, phase detector, post-silicon tuning