Search results for "superscalar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Joshua Redstone, Susan J. Eggers, Henry M. Levy	An Analysis of Operating System Behavior on a Simultaneous Multithreaded Architecture.	ASPLOS	2000	DBLP DOI BibTeX RDF
17	Ramon Canal, Joan-Manuel Parcerisa, Antonio González 0001	A Cost-Effective Clustered Architecture.	IEEE PACT	1999	DBLP DOI BibTeX RDF	code partitioning, dynamic steering, inter-cluster communication, cluster, microarchitecture, clustered architecture, workload balance
17	Heiko Oehring, Ulrich Sigmund, Theo Ungerer	MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	MPEG-2 video decompression, Simultaneous multithreading, multimedia extension
17	Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata	An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism.	EUROMICRO	1999	DBLP DOI BibTeX RDF
17	Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors.	LCPC	1999	DBLP DOI BibTeX RDF
17	Freddy Gabbay, Avi Mendelson	Using Value Prediction to Increase the Power of Speculative Execution Hardware.	ACM Trans. Comput. Syst.	1998	DBLP DOI BibTeX RDF	stride value prediction, speculative execution, value prediction
17	Matthias Menge	Superskalare Prozessoren.	Inform. Spektrum	1998	DBLP DOI BibTeX RDF	Scoreboarding, Reservierungseinheit, Competion-Unit, Retirement-Unit, History-Buffer, Reorder-Buffer
17	Pedro Marcuello, Antonio González 0001	Data Speculative Multithreaded Architecture.	EUROMICRO	1998	DBLP DOI BibTeX RDF
17	Jack L. Lo, Luiz André Barroso, Susan J. Eggers, Kourosh Gharachorloo, Henry M. Levy, Sujay S. Parekh	An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors.	ISCA	1998	DBLP DOI BibTeX RDF
17	Kimberly Keeton, David A. Patterson 0001, Yong Qiang He, Roger C. Raphael, Walter E. Baker	Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads.	ISCA	1998	DBLP DOI BibTeX RDF
17	Kenneth M. Wilson, Kunle Olukotun	Designing High Bandwidth On-Chip Caches.	ISCA	1997	DBLP DOI BibTeX RDF
17	Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Kenneth G. Wilson, Kunyung Chang	The Case for a Single-Chip Multiprocessor.	ASPLOS	1996	DBLP DOI BibTeX RDF
17	Karel Driesen, Urs Hölzle, Jan Vitek	Message Dispatch on Pipelined Processors.	ECOOP	1995	DBLP DOI BibTeX RDF	message dispatch, performance, implementation, computer architecture
17	Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel	Optimization of Instruction Fetch Mechanisms for High Issue Rates.	ISCA	1995	DBLP DOI BibTeX RDF
17	Zhi-Guo Yu, Xiao-Yu Zhong, Xiao-Jie Ma, Xiaofeng Gu	W-IQ: Wither-logic based issue queue for RISC-V superscalar out-of-order processor.	Integr.	2024	DBLP DOI BibTeX RDF
17	Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi 0001, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai	An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS.	ISCAS	2023	DBLP DOI BibTeX RDF
17	Benjamin Binder 0001, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, Mathieu Jan	Formal modeling and verification for amplification timing anomalies in the superscalar TriCore architecture.	Int. J. Softw. Tools Technol. Transf.	2022	DBLP DOI BibTeX RDF
17	Nicolas Derumigny, Théophile Bastian, Fabian Gruber, Guillaume Iooss, Christophe Guillon, Louis-Noël Pouchet, Fabrice Rastello	PALMED: Throughput Characterization for Superscalar Architectures.	CGO	2022	DBLP DOI BibTeX RDF
17	Bingcai Sui, Caixia Sun, Yongwen Wang, Hui Guo	Design and optimization of Issue queue in Out-of-Order superscalar microprocessor.	CACML	2022	DBLP DOI BibTeX RDF
17	Alexander Antonov	Superscalar Out-of-Order RISC-V ASIP Based on Programmable Hardware Generator with Decoupled Computations and Flow Control.	MECO	2022	DBLP DOI BibTeX RDF
17	Barbara Gigerl, Robert Primas, Stefan Mangard	Secure and Efficient Software Masking on Superscalar Pipelined Processors.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
17	Barbara Gigerl, Robert Primas, Stefan Mangard	Secure and Efficient Software Masking on Superscalar Pipelined Processors.	ASIACRYPT (2)	2021	DBLP DOI BibTeX RDF
17	Rosa M. Badia	Superscalar Programming Models: A Perspective from Barcelona.	HPDC	2021	DBLP DOI BibTeX RDF
17	Timothée Ewart, Francesco Cremonesi, Felix Schürmann, Fabien Delalondre	Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function ex.	ACM Trans. Math. Softw.	2020	DBLP DOI BibTeX RDF
17	Ying Zhang 0040, Krishnendu Chakrabarty, Zebo Peng, Ahmed Rezine, Huawei Li 0001, Petru Eles, Jianhui Jiang	Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
17	T. Gokulan, Akshay Muraleedharan, Kuruvilla Varghese	Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA.	DSD	2020	DBLP DOI BibTeX RDF
17	Dejan Spasov	An Improvement in the Convergence of Superscalar Processors.	MIPRO	2020	DBLP DOI BibTeX RDF
17	Benjamin Binder 0001, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, Mathieu Jan	Scalable Detection of Amplification Timing Anomalies for the Superscalar TriCore Architecture.	FMICS	2020	DBLP DOI BibTeX RDF
17	Kleovoulos Kalaitzidis	Advanced Speculation to Increase the Performance of Superscalar Processors. (Spéculation Avancée pour Augmenter Les Performances des Processeurs Superscalaires).		2020	RDF
17	Bharath Srinivas Prabakaran, Mihika Dave, Florian Kriebel, Semeen Rehman, Muhammad Shafique 0001	Architectural-Space Exploration of Heterogeneous Reliability and Checkpointing Modes for Out-of-Order Superscalar Processors.	IEEE Access	2019	DBLP DOI BibTeX RDF
17	Yumin Hou, Xu Wang, Jiawei Fu, Junping Ma, Hu He 0001, Xu Yang 0003	Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
17	Julien Proy, Karine Heydemann, Fabien Majéric, Albert Cohen 0001, Alexandre Berzati	Studying EM Pulse Effects on Superscalar Microarchitectures at ISA Level.	CoRR	2019	DBLP BibTeX RDF
17	Mutaz A. B. Al-Tarawneh	Analysis of the Factors Influencing Architectural Time-Predictability of Superscalar Processors.	J. Comput. Sci. Eng.	2019	DBLP DOI BibTeX RDF
17	Rafael Billig Tonetto, Douglas Maciel Cardoso, Marcelo Brandalero, Luciano Agostini, Gabriel L. Nazar, José Rodrigo Azambuja, Antonio Carlos Schneider Beck	A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
17	Niranjan Soundararajan, Saurabh Gupta, Ragavendra Natarajan, Jared Stark, Rahul Pal, Franck Sala, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney	Towards the adoption of Local Branch Predictors in Modern Out-of-Order Superscalar Processors.	MICRO	2019	DBLP DOI BibTeX RDF
17	Julien Proy, Karine Heydemann, Alexandre Berzati, Fabien Majéric, Albert Cohen 0001	A First ISA-Level Characterization of EM Pulse Effects on Superscalar Microarchitectures: A Secure Software Perspective.	ARES	2019	DBLP DOI BibTeX RDF
17	Douglas Maciel Cardoso, Rafael Billig Tonetto, Marcelo Brandalero, Luciano Agostini, Gabriel L. Nazar, José Rodrigo Azambuja, Antonio Carlos Schneider Beck	Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors.	ICECS	2019	DBLP DOI BibTeX RDF
17	Sam Van den Steen, Lieven Eeckhout	Modeling Superscalar Processor Memory-Level Parallelism.	IEEE Comput. Archit. Lett.	2018	DBLP DOI BibTeX RDF
17	Henry Wong, Vaughn Betz, Jonathan Rose	High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors.	ACM Trans. Reconfigurable Technol. Syst.	2018	DBLP DOI BibTeX RDF
17	Bharath Srinivas Prabakaran, Mihika Dave, Semeen Rehman, Florian Kriebel, Muhammad Shafique 0001	Heterogeneous Reliability Modes with Efficient State Compression for Out-of-Order Superscalar Processors.	CoRR	2018	DBLP BibTeX RDF
17	Rafael Billig Tonetto, Gabriel L. Nazar, Antonio Carlos Schneider Beck	Precise evaluation of the fault sensitivity of OoO superscalar processors.	DATE	2018	DBLP DOI BibTeX RDF
17	Renuka Patel, Sanjay Kumar	Visualizing effect of dependency in superscalar pipelining.	RAIT	2018	DBLP DOI BibTeX RDF
17	Peter T. Breuer, Jonathan P. Bowen, Esther Palomar, Zhiming Liu 0001	Superscalar Encrypted RISC: The Measure of a Secret Computer.	TrustCom/BigDataSE	2018	DBLP DOI BibTeX RDF
17	Miroslav N. Velev	Survey of Techniques for Efficient Solving of Boolean Formulas from Formal Verification of Pipelined, Superscalar, and VLIW Microprocessors at a High Level of Abstraction.	ISAIM	2018	DBLP BibTeX RDF
17	Alessandro Barenghi, Gerardo Pelosi	Side-channel security of superscalar CPUs: evaluating the impact of micro-architectural features.	DAC	2018	DBLP DOI BibTeX RDF
17	Yang Zhang, Zhi Qi, Xiaoxi Wu, Wenjie Fu	A novel evaluation method for superscalar out-of-order ARM microprocessors targeting android applications.	PACRIM	2017	DBLP DOI BibTeX RDF
17	Victor Anton, Cristian Ramon-Cortes, Jorge Ejarque, Rosa M. Badia	Transparent Execution of Task-Based Parallel Applications in Docker with COMP Superscalar.	PDP	2017	DBLP DOI BibTeX RDF
17	Sungkwan Ku, Elliott Forbes, Rangeen Basu Roy Chowdhury, Eric Rotenberg	A case for standard-cell based RAMs in highly-ported superscalar processor structures.	ISQED	2017	DBLP DOI BibTeX RDF
17	Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh	On Testing of Superscalar Processors in Functional Mode for Delay Faults.	VLSID	2017	DBLP DOI BibTeX RDF
17	Andrea Mondelli	Revisiting Wide Superscalar Microarchitecture.		2017	RDF
17	Marcelo Brandalero, Antonio Carlos Schneider Beck	Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism.	Des. Autom. Embed. Syst.	2016	DBLP DOI BibTeX RDF
17	Yumin Hou, Hu He 0001, Xu Yang 0003, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu	FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW.	VLSI Design	2016	DBLP DOI BibTeX RDF
17	Peter T. Breuer, Jonathan P. Bowen	Superscalar Encrypted RISC: A Secret Computer in Simulation.	IACR Cryptol. ePrint Arch.	2016	DBLP BibTeX RDF
17	Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Eric Rotenberg	AnyCore-1: A comprehensively adaptive 4-way superscalar processor.	Hot Chips Symposium	2016	DBLP DOI BibTeX RDF
17	Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Sungkwan Ku, Eric Rotenberg	AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores.	ISPASS	2016	DBLP DOI BibTeX RDF
17	Mario Schölzel, Tobias Koal, Sebastian Müller 0005, Stefan Scharoba, Stephanie Roder, Heinrich Theodor Vierhaus	A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors.	LATS	2016	DBLP DOI BibTeX RDF
17	Fahimeh Yazdanpanah, Mohammad Alaei	Design space exploration of hardware task superscalar architecture.	J. Supercomput.	2015	DBLP DOI BibTeX RDF
17	Ricardo A. Velásquez 0001, Pierre Michaud, André Seznec	BADCO: Behavioral Application-Dependent Superscalar Core Models.	Int. J. Parallel Program.	2015	DBLP DOI BibTeX RDF
17	Pierre Michaud, Andrea Mondelli, André Seznec	Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters.	ACM Trans. Archit. Code Optim.	2015	DBLP DOI BibTeX RDF
17	Arthur Perais, André Seznec	BeBoP: A cost effective predictor infrastructure for superscalar value prediction.	HPCA	2015	DBLP DOI BibTeX RDF
17	Görkem Asilioglu, Zhaoxiang Jin, Murat Köksal, Omkar Javeri, Soner Önder	LaZy superscalar.	ISCA	2015	DBLP DOI BibTeX RDF
17	Arthur Perais	Increasing the performance of superscalar processors through value prediction. (La prédiction de valeurs comme moyen d'augmenter la performance des processeurs superscalaires).		2015	RDF
17	Christopher Bailey 0002, Brendan Mullane	Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics.	VLSI Design	2014	DBLP DOI BibTeX RDF
17	Yuya Kora, Kyohei Yamaguchi, Hideki Ando	MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
17	Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout	Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance.	ACM Trans. Archit. Code Optim.	2014	DBLP DOI BibTeX RDF
17	Marcelo Brandalero, Antonio Carlos Schneider Beck	Potential of Using a Reconfigurable System on a Superscalar Core for ILP Improvements.	SBESC	2014	DBLP DOI BibTeX RDF
17	Xue Yang, Lixin Yu, Yunkai Feng	Design of SPARC V8 superscalar pipeline applied Tomasulo's algorithm.	ICDIP	2014	DBLP DOI BibTeX RDF
17	Jianqing Xiao, Pengwei Lv, Mian Lou, Xunying Zhang, Xubang Shen	A task-level superscalar microarchitecture for large scale chip multiprocessors.	RTCSA	2014	DBLP DOI BibTeX RDF
17	Wei Zhang 0044, Hang Zhang 0031, John C. Lach	Adaptive front-end throttling for superscalar processors.	ISLPED	2014	DBLP DOI BibTeX RDF
17	Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus	Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults.	DFT	2014	DBLP DOI BibTeX RDF
17	Blake Haugen, Jakub Kurzak, Asim YarKhan, Piotr Luszczek, Jack J. Dongarra	Parallel Simulation of Superscalar Scheduling.	ICPP	2014	DBLP DOI BibTeX RDF
17	Yuuki Shibata, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima	An implementation of Auto-Memoization mechanism on ARM-based superscalar processor.	ISSoC	2014	DBLP DOI BibTeX RDF
17	Fahimeh Yazdanpanah	Hardware design of task superscalar architecture.		2014	RDF
17	Davor Capalija, Tarek S. Abdelrahman	Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor.	IEEE Trans. Parallel Distributed Syst.	2013	DBLP DOI BibTeX RDF
17	Kiyeon Lee, Sangyeun Cho	Accurately modeling superscalar processor performance with reduced trace.	J. Parallel Distributed Comput.	2013	DBLP DOI BibTeX RDF
17	Krzysztof Marcinek, Witold A. Pleskacz	ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
17	Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo	Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization.	J. Signal Process. Syst.	2013	DBLP DOI BibTeX RDF
17	Stefano Di Carlo, Ernesto Sánchez 0001, Matteo Sonza Reorda	On the on-line functional test of the Reorder Buffer memory in superscalar processors.	DDECS	2013	DBLP DOI BibTeX RDF
17	Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu	A study on polymorphing superscalar processor dynamically to improve power efficiency.	ISVLSI	2013	DBLP DOI BibTeX RDF
17	Xue Yang, Lixin Yu, Wei Zhuang, Yingpan Wu, Li Hao	Design of instruction decode logic for dual-issue superscalar processor based on LEON2.	ICCE-Berlin	2013	DBLP DOI BibTeX RDF
17	Fahimeh Yazdanpanah, Daniel Jiménez-González, Carlos Álvarez-Martínez, Yoav Etsion, Rosa M. Badia	Analysis of the Task Superscalar Architecture Hardware Design.	ICCS	2013	DBLP DOI BibTeX RDF
17	Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu	On dynamic polymorphing of a superscalar core for improving energy efficiency.	ICCD	2013	DBLP DOI BibTeX RDF
17	Kosaku Fukuda, Lin Meng, Takeshi Kumaki, Takeshi Ogura	A CAM-Based Separated BTB for a Superscalar Processor.	CANDAR	2013	DBLP DOI BibTeX RDF
17	Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo	Dynamic BTB Resizing for Variable Stages Superscalar Architecture.	CANDAR	2013	DBLP DOI BibTeX RDF
17	D. Changdao, Mariagrazia Graziano, Ernesto Sánchez 0001, Matteo Sonza Reorda, Maurizio Zamboni, N. Zhifan	On the functional test of the BTB logic in pipelined and superscalar processors.	LATW	2013	DBLP DOI BibTeX RDF
17	Simone Corbetta, William Fornaciari	Performance/reliability trade-off in superscalar processors for aggressive NBTI restoration of functional units.	ACM Great Lakes Symposium on VLSI	2013	DBLP DOI BibTeX RDF
17	Ricardo Andrés Velásquez Vélez	Behavioral Application-dependent Superscalar Core Modeling (Modélisation comportementale dépend de l'application pour cœurs superscalairesBehavioral Application-dependent superscolor core modeling).		2013	RDF
17	Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg	FabScalar: Automating Superscalar Core Design.	IEEE Micro	2012	DBLP DOI BibTeX RDF
17	Kyohei Yamaguchi, Yuya Kora, Hideki Ando	Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification.	IEICE Trans. Inf. Syst.	2012	DBLP DOI BibTeX RDF
17	Arpad Gellert, Horia Calborean, Lucian Vintan, Adrian Florea	Multi-objective optimisations for a superscalar architecture with selective value prediction.	IET Comput. Digit. Tech.	2012	DBLP DOI BibTeX RDF
17	Mehdi Alipour, Mostafa E. Salehi	Performance-Optimum Superscalar Architecture for Embedded Applications	CoRR	2012	DBLP BibTeX RDF
17	Michael Andersch, Chi Ching Chi, Ben H. H. Juurlink	Using OpenMP superscalar for parallelization of embedded and consumer applications.	ICSAMOS	2012	DBLP DOI BibTeX RDF
17	Ricardo A. Velásquez 0001, Pierre Michaud, André Seznec	BADCO: Behavioral Application-Dependent Superscalar Core model.	ICSAMOS	2012	DBLP DOI BibTeX RDF
17	Jason Van Dyken, José G. Delgado-Frias	A superscalar processor for a medium-grain reconfigurable hardware.	MWSCAS	2012	DBLP DOI BibTeX RDF
17	Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg	A physical design study of fabscalar-generated superscalar cores.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
17	Mathieu Rosiere, Jean Lou Desbarbieux, Nathalie Drach, Franck Wajsbürt	An out-of-order superscalar processor on FPGA: The ReOrder Buffer design.	DATE	2012	DBLP DOI BibTeX RDF
17	Ying Zhang 0040, Ahmed Rezine, Petru Eles, Zebo Peng	Automatic Test Program Generation for Out-of-Order Superscalar Processors.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
17	Brandon H. Dwiel, Niket Kumar Choudhary, Eric Rotenberg	FPGA modeling of diverse superscalar processors.	ISPASS	2012	DBLP DOI BibTeX RDF
17	Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout	A mechanistic performance model for superscalar in-order processors.	ISPASS	2012	DBLP DOI BibTeX RDF
17	S. K. Fairooz, B. K. Madhavi	SoC Modeling for Video Coding with Superscalar Projection.	ACITY (2)	2012	DBLP DOI BibTeX RDF