Search results for "3DIC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Brandon Noia, Krishnendu Chakrabarty	Pre-bond testing of die logic and TSVs in high performance 3D-SICs.	3DIC	2011	DBLP DOI BibTeX RDF
1	Qian Zhao 0001, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi	A novel reconfigurable logic device base on 3D stack technology.	3DIC	2011	DBLP DOI BibTeX RDF
1	Shivam Priyadarshi, Jianchen Hu, Won Ha Choi, Samson Melamed, Xi Chen, W. Rhett Davis, Paul D. Franzon	Pathfinder 3D: A flow for system-level design space exploration.	3DIC	2011	DBLP DOI BibTeX RDF
1	Myat Thu Linn Aung, Eric Teck Heng Lim, Takefumi Yoshikawa, Tony Tae-Hyoung Kim	Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DIC.	3DIC	2011	DBLP DOI BibTeX RDF
1	Fa Xing Che, Wahyuaji Narottama Putra, A. Heryanto, A. Trigg, S. Gao, Chee Lip Gan	Numerical and experimental study on Cu protrusion of Cu-filled through-silicon vias (TSV).	3DIC	2011	DBLP DOI BibTeX RDF
1	Ryusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Yusuke Endo, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi	Effects of 3-D stacked vector cache on energy consumption.	3DIC	2011	DBLP DOI BibTeX RDF
1	Nam Hee Kwon, S. M. Hong, Yong-Won Cha, Sun Jae Lee, Han Gyul Lee, Areum Kim, Soo Won Kim, Chang Hyun Kim, Sung Gyu Pyo	Effect of planarity on the 3D integration in 3-D integrated CMOS image sensor.	3DIC	2011	DBLP DOI BibTeX RDF
1	Mariappan Murugesan, Hideto Hashiguchi, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi	W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress.	3DIC	2011	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures.	3DIC	2011	DBLP DOI BibTeX RDF
1	Mariappan Murugesan, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi	High density Cu-TSVs and reliability issues.	3DIC	2011	DBLP DOI BibTeX RDF
1	Taro Hayashi, Kazuo Kondo, Minoru Takeuchi, Yushi Suzuki, Takeyasu Saito, Naoki Okamoto, Masao Marunaka, Takayuki Tsuchiya, Masaru Bunya	3D interconnected technology by high speed copper electrodeposition using diallylamine levelers.	3DIC	2011	DBLP DOI BibTeX RDF
1	Ryohei Sato, Akihiro Tsukada, Yukihiro Sato, Yoshiharu Iwata, Hidenori Murata, Shigenobu Sekine, Ryuji Kimura, Keijiroh Kishi	Study on high performance and productivity of TSV's with new filling method and alloy for advanced 3D-SiP.	3DIC	2011	DBLP DOI BibTeX RDF
1	Kazuta Saito, Richard J. Webb, Blake R. Dronen	Advances of 3M™ wafer support system.	3DIC	2011	DBLP DOI BibTeX RDF
1	John H. Lau	Recent advances and new trends in nanotechnology and 3D integration for semiconductor industry.	3DIC	2011	DBLP DOI BibTeX RDF
1	Joseph Romen Cubillo, Roshan Weerasekera, Zaw Zaw Oo, En-Xiao Liu, Bob Conn, Surya Bhattacharya, Robert Patti	Interconnect design and analysis for Through Silicon Interposers (TSIs).	3DIC	2011	DBLP DOI BibTeX RDF
1	Fumiki Kato, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi	Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration.	3DIC	2011	DBLP DOI BibTeX RDF
1	Naoya Watanabe, Takumi Miyazaki, Masahiro Aoyagi, Kazuhiro Yoshikawa	Damage evaluation of wet-chemical silicon-wafer thinning process.	3DIC	2011	DBLP DOI BibTeX RDF
1	Y. H. Hu, C. S. Liu, M. J. Lii, Kenneth J. Rebibis, Anne Jourdain, Antonio La Manna, Gerald Beyer, Eric Beyne, C. H. Yu	3D stacking using Cu-Cu direct bonding.	3DIC	2011	DBLP DOI BibTeX RDF
1	Sayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Yasumitsu Orii, Katsuyuki Sakuma, Takahiro Kinoshita, Takashi Kawakami	Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration.	3DIC	2011	DBLP DOI BibTeX RDF
1	Xiaoyu Mi, Osamu Toyoda, Satoshi Ueda, Fumihiko Nakazawa	A 3D heterogeneous integration method using LTCC wafer for RF applications.	3DIC	2011	DBLP DOI BibTeX RDF
1	Akihiro Ikeda, Naoya Watanabe, Tanemasa Asano	High frequency signal transmission characteristics of cone bump interconnections.	3DIC	2011	DBLP DOI BibTeX RDF
1	Sebastien Mermoz, Loic Sanchez, Léa Di Cioccio, Jean Berthier, Emilie Deloffre, Christian Fretigny	Impact of containment and deposition method on sub-micron chip-to-wafer self-assembly yield.	3DIC	2011	DBLP DOI BibTeX RDF
1	Hideaki Ishihara	Evolutional Directions of Smart Automotive Systems and Semiconductors.	3DIC	2011	DBLP DOI BibTeX RDF
1	Xiaodong Wang, Dilip P. Vasudevan, Hsien-Hsin S. Lee	Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing.	3DIC	2011	DBLP DOI BibTeX RDF
1	Akihiro Noriki, Kang Wook Lee 0002, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi	Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI.	3DIC	2011	DBLP DOI BibTeX RDF
1	Fumihiko Nakazawa, Takeaki Shimanouchi, Tadashi Nakatani, Takashi Katsuki, Hisao Okuda, Osamu Toyoda, Satoshi Ueda	Effect of frequency in the 3D integration of a PZT-actuated MEMS switch using a single crystal silicon asymmetric beam.	3DIC	2011	DBLP DOI BibTeX RDF
1	Toshiaki Itabashi, Masashi Kotani, Melvin P. Zussman, K. Zoschke, T. Fischer, M. Topper, Hiroyuki Ishida	High temperature bonding solutions enabling thin wafer process and handling on 3D-IC manufacturing.	3DIC	2011	DBLP DOI BibTeX RDF
1	Elyse Rosenbaum, Vrashank Shukla, Min-Sun Keel	ESD protection networks for 3D integrated circuits.	3DIC	2011	DBLP DOI BibTeX RDF
1	Tomoji Nakamura, Hideki Kitada, Yoriko Mizushima, Nobuhide Maeda, Koji Fujimoto, Takayuki Ohba	Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects.	3DIC	2011	DBLP DOI BibTeX RDF
1	Yoshiaki Oizono, Yoshitaka Nabeshima, Takafumi Okumura, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda	PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure.	3DIC	2011	DBLP DOI BibTeX RDF
1	Toru Ikeda, Masatoshi Oka, Shinya Kawahara, Noriyuki Miyazaki, Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii, Fumiaki Yamada, Morihiro Kada	Combination between the nonlinear finite element analyses and the strain measurement using the digital image correlation for a new 3D SIC package.	3DIC	2011	DBLP DOI BibTeX RDF
1	Fumihiro Inoue, Harold Philipsen, Alex Radisic, Silvia Armini, Peter Leunissen, Hiroshi Miyake, Ryohei Arima, Tomohiro Shimizu, Toshiaki Ito, Hirofumi Seki, Yuko Shinozaki, Tomohiko Yamamoto, Shoso Shingubara	Low temperature through-Si via fabrication using electroless deposition.	3DIC	2011	DBLP DOI BibTeX RDF
1	Paul D. Franzon, W. Rhett Davis, Zheng Zhou 0004, Shivam Priyadarshi, Matthew Hogan, Tanay Karnik, Ganapti Srinavas	Coordinating 3D designs: Interface IP, standards or free form?	3DIC	2011	DBLP DOI BibTeX RDF
1	Teruyoshi Hatanaka, Koh Johguchi, Ken Takeuchi	A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives.	3DIC	2011	DBLP DOI BibTeX RDF
1	Hans-Günther Moser, Ladislav Andricek, Michael Beimforde, G. Liemann, Anna Macchiolo, Richard Nisius, Rainer Helmut Richter, Philipp Weigell	Development of pixel detectors for particle physics using SLID-ICV interconnection technology.	3DIC	2011	DBLP DOI BibTeX RDF
1	Andrej Ivankovic, Geert Van der Plas, V. Moroz, M. Choi, Vladimir Cherman, Abdelkarim Mercha, Paul Marchal, Marcel Gonzalez, Geert Eneman, Wenqi Zhang, Thibault Buisson, Mikael Detalle, Antonio La Manna, Diederik Verkest, Gerald Beyer, Eric Beyne, Bart Vandevelde, Ingrid De Wolf, Dirk Vandepitte	Analysis of microbump induced stress effects in 3D stacked IC technologies.	3DIC	2011	DBLP DOI BibTeX RDF
1	Hong-Yeol Lim, Gi-Ho Park	Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technology.	3DIC	2011	DBLP DOI BibTeX RDF
1	Farhad Mehdipour, Krishna Chaitanya Nunna, Lovic Gauthier, Koji Inoue, Kazuaki J. Murakami	A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack.	3DIC	2011	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila	HIBS - Novel inter-layer bus structure for stacked architectures.	3DIC	2011	DBLP DOI BibTeX RDF
1	Takafumi Fukushima, Yuki Ohara, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee 0002, Tetsu Tanaka, Mitsumasa Koyanagi	Temporary bonding strength control for self-assembly-based 3D integration.	3DIC	2011	DBLP DOI BibTeX RDF
1	Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kang Wook Lee 0002, Takafumi Fukushima, Mitsumasa Koyanagi	Chip-level TSV integration for rapid prototyping of 3D system LSIs.	3DIC	2011	DBLP DOI BibTeX RDF
1	Satoru Toyoda, A. Shibata, M. Harada, Takahide Murayama, Toshiyuki Sakuishi, M. Hatanaka, Yasuhiro Morikawa, Koukou Suu	TSV process solution for 3D-IC.	3DIC	2011	DBLP DOI BibTeX RDF
1	A. Ege Engin, N. Srinidhi Raghavan	Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design.	3DIC	2011	DBLP DOI BibTeX RDF
1	Yuki Ohara, Kang Wook Lee 0002, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi	Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration.	3DIC	2011	DBLP DOI BibTeX RDF
1	Kouji Kiyoyama, Kang Wook Lee 0002, Takafumi Fukushima, H. Naganuma, H. Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi	A very low area ADC for 3-D stacked CMOS image processing system.	3DIC	2011	DBLP DOI BibTeX RDF
1	Seyyed Hasan Moallempour, Seyyed Ahmad Razavi, Morteza Saheb Zamani	TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replication.	3DIC	2011	DBLP DOI BibTeX RDF
1	Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume	A built-in test circuit for open defects at interconnects between dies in 3D ICs.	3DIC	2011	DBLP DOI BibTeX RDF
1	Chao Zhang 0007, Guangyu Sun 0003	Fabrication cost analysis for 2D, 2.5D, and 3D IC designs.	3DIC	2011	DBLP DOI BibTeX RDF
1	Takanori Shuto, Naoya Watanabe, Akihiro Ikeda, Tanemasa Asano	Low-temperature bonding of LSI chips to PEN film using Au cone bump for heterogeneous integration.	3DIC	2011	DBLP DOI BibTeX RDF
1	Kuan-Neng Chen, Z. Xu, Fei Liu, Cheng-Ta Ko, Chuan-An Cheng, W. C. Huang, H. L. Lin, C. Cabral, Zhi-Cheng Hsiao, N. Klymko, Hsin-Chia Fu, Y. H. Chen, Jian-Qiang Lu, Wei-Chung Lo	Cu-based bonding technology for 3D integration applications.	3DIC	2011	DBLP DOI BibTeX RDF
1	Alain Phommahaxay, Anne Jourdain, Greet Verbinnen, Tobias Woitke, Peter Bisson, Markus Gabriel, Walter Spiess, Alice Guerrero, Jeremy McCutcheon, Rama Puligadda, Pieter Bex, Axel Van den Eede, Bart Swinnen, Gerald Beyer, Andy Miller, Eric Beyne	Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding.	3DIC	2011	DBLP DOI BibTeX RDF
1	Futoshi Furuta, Kenichi Osada	6 Tbps/W, 1 Tbps/mm2, 3D interconnect using adaptive timing control and low capacitance TSV.	3DIC	2011	DBLP DOI BibTeX RDF
1	Osamu Nakatsuka, Hideki Kitada, Young-Suk Kim, Yoriko Mizushima, Tomoji Nakamura, Takayuki Ohba, Shigeaki Zaima	Characterization of local strain around trough silicon via interconnects in wafer-on-wafer structures.	3DIC	2011	DBLP DOI BibTeX RDF
1	Sten Vollebregt, Ryoichi Ishihara, Johan van der Cingel, Kees Beenakker	Low-temperature bottom-up integration of carbon nanotubes for vertical interconnects in monolithic 3D integrated circuits.	3DIC	2011	DBLP DOI BibTeX RDF
1	Yuka Ito, Shinsuke Terada, Shinya Arai, Koji Choki, Takafumi Fukushima, Mitsumasa Koyanagi	High-bandwidth data transmission of new transceiver module through optical interconnection.	3DIC	2011	DBLP DOI BibTeX RDF
1	Won-Myoung Ki, Myong-Suk Kang, Sehoon Yoo, Chang-Woo Lee	Fabrication and bonding process of fine pitch Cu pillar bump on thin Si chip for 3D stacking IC.	3DIC	2011	DBLP DOI BibTeX RDF
1	H. Y. Li, L. Xie, L. G. Ong, A. Baram, I. Herer, Arnon Hirshberg, S. C. Chong, D. L. Kwong	Ultra-compact micro-coil realized via multilevel dense TSV coil for MEMs application.	3DIC	2011	DBLP DOI BibTeX RDF
1	Naoki Saito 0004, Naokazu Murata, Kinji Tamakawa, Ken Suzuki, Hideo Miura	Mechanical and electrical reliability of copper interconnections for 3DIC.	3DIC	2011	DBLP DOI BibTeX RDF
1	Manuel Suarez, Víctor M. Brea 0001, F. Pardo, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez	A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors.	3DIC	2011	DBLP DOI BibTeX RDF
1	Masanori Hayase, Naoki Mizukoshi, Masayuki Nagao	Copper deep via superfilling by selective accelerator deactivation.	3DIC	2011	DBLP DOI BibTeX RDF
1	Revanth Nadipalli, Ji Fan, Holden King Ho Li, Keng Hoong Wee, Hao Yu 0001, Chuan Seng Tan	3D integration of MEMS and CMOS via Cu-Cu bonding with simultaneous formation of electrical, mechanical and hermetic bonds.	3DIC	2011	DBLP DOI BibTeX RDF
1	Dau Fatt Lim, K. C. Leong, Chuan Seng Tan	Selection of underfill material in Cu hybrid bonding and its effect on the transistor keep-out-zone.	3DIC	2011	DBLP DOI BibTeX RDF
1	Erik Vick, Scott H. Goodwin, Garry Cunnigham, Dorota Temple	Vias-last process technology for thick 2.5D Si interposers.	3DIC	2011	DBLP DOI BibTeX RDF
1	Keith Buchanan, Dave Thomas, Hefin Griffiths, Kathrine Crook, Daniel Archard, Mark Carruthers, Masahiko Tanaka	Plasma etch and dielectric deposition processes for TSV Reveal.	3DIC	2011	DBLP DOI BibTeX RDF
1	Gyujei Lee, Suk-woo Jeon, Kwang-yoo Byun, Dongil Kwon	Mechanical characterization of residual stress around TSV through instrumented indentation algorithm.	3DIC	2011	DBLP DOI BibTeX RDF
1	Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda	Void reduction in wafer bonding by simultaneously formed ventilation channels.	3DIC	2011	DBLP DOI BibTeX RDF
1	Sung-Geun Kang, Youngrae Kim, Eun-Sol Kim, Naeun Lim, Teakgyu Jeong, Jieun Lee, Sarah Eunkyung Kim, Sungdong Kim	Evaluation of wafer level Cu bonding for 3D integration.	3DIC	2011	DBLP DOI BibTeX RDF
1	Ran Wang, Gary Charles, Paul D. Franzon	Modeling and compare of through-silicon-via (TSV) in high frequency.	3DIC	2011	DBLP DOI BibTeX RDF
1	Nobuhide Maeda, Young-Suk Kim, Y. Hikosaka, T. Eshita, Hideki Kitada, K. Fujimoto, Yoriko Mizushima, K. Suzuki, Tadao Nakamura, Akihito Kawai, Kazuhisa Arai, Takayuki Ohba	Development of ultra-thinning technology for logic and memory heterogeneous stack applications.	3DIC	2011	DBLP DOI BibTeX RDF
1	Jae Hak Lee, Choong D. Yoo, Jun-Yeob Song, Seung S. Lee, Sun-Rak Kim	A study on the edge traces technique for 3D stack chip.	3DIC	2011	DBLP DOI BibTeX RDF
1	Andy Heinig, Christoph Sohrmann	Multi-step approach for thermal optimization of 3D-IC and package.	3DIC	2011	DBLP DOI BibTeX RDF
1	Xin Liu 0015, Lei Wang 0070, Mini Jayakrishnan, Jingjing Lan, Hongyu Li, Chong Ser Choong, M. Kumarasamy Raja, Yongxin Guo, Wang Ling Goh, Jin He, Shan Gao, Minkyu Je	A miniaturized heterogeneous wireless sensor node in 3DIC.	3DIC	2011	DBLP DOI BibTeX RDF
1	Tadatomo Suga, Ryuichi Kondoh	Low temperature bonding for 3D interconnects.	3DIC	2011	DBLP DOI BibTeX RDF
1	Xiaowu Zhang, Ranjan Rajoo, F. X. Che, C. S. Selvanayagam, W. K. Choi, Shan Gao, Guo-Qiang Lo, Dim-Lee Kwong	A low stress bond pad design optimization of low temperature solder interconnections on TSVs for MEMS applications.	3DIC	2011	DBLP DOI BibTeX RDF
1	Byung-Hyun Kwak, Sung-Hyuk Kim, Young-Bae Park	Current stressing effect on interfacial reaction characteristics of Cu pillar/Sn-3.5Ag microbumps for 3D integration.	3DIC	2011	DBLP DOI BibTeX RDF
1	Deepak C. Sekar, Zvi Or-Bach	Monolithic 3D-ICs with single crystal silicon layers.	3DIC	2011	DBLP DOI BibTeX RDF
1	Mauro Scandiuzzo, Roberto Cardu, Salvatore Cani, Simone Spolzino, Luca Perugini, Eleonora Franchi, Roberto Canegallo, Roberto Guerrieri	3D system on chip memory interface based on modeled capacitive coupling interconnections.	3DIC	2010	DBLP DOI BibTeX RDF
1	Erik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario Konijnenburg	3D DfT architecture for pre-bond and post-bond testing.	3DIC	2010	DBLP DOI BibTeX RDF
1	Kenzo Inagaki	3D R&D technology for the future voyage in Japan.	3DIC	2010	DBLP DOI BibTeX RDF
1	Rebha El Farhane, Myriam Assous, Patrick Leduc, Aurélie Thuaire, David Bouchu, Hélène Feldis, Nicolas Sillon	A successful implementation of dual damascene architecture to copper TSV for 3D high density applications.	3DIC	2010	DBLP DOI BibTeX RDF
1	Anne Jourdain, Thibault Buisson, Alain Phommahaxay, Mark Privett, Dan Wallace, Sumant Sood, Peter Bisson, Eric Beyne, Youssef Travaly, Bart Swinnen	300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications.	3DIC	2010	DBLP DOI BibTeX RDF
1	Christophe Zinck	Keynote speakers day 1: 3D integration with TSV interconnects: Technology trends & market analysis.	3DIC	2010	DBLP DOI BibTeX RDF
1	Steve Lipa, Thorlindur Thorolfsson, Paul D. Franzon	The NCSU Tezzaron design kit.	3DIC	2010	DBLP DOI BibTeX RDF
1	Grzegorz Deptuch, Marcel Demarteau, Jim Hoff, Ronald Lipton, Alpana Shenai, Raymond Yarema, Tom Zimmerman 0002	Pixel detectors in 3D technologies for high energy physics.	3DIC	2010	DBLP DOI BibTeX RDF
1	Gerrit Oosterhuis, Bert Huis in 't Veld, Gerald Ebberink, Daniël Arnaldo del Cerro, Edwin van den Eijnden, Peter Chall, Ben van der Zon	Additive interconnect fabrication by picosecond Laser Induced Forward Transfer.	3DIC	2010	DBLP DOI BibTeX RDF
1	Moongon Jung, Sung Kyu Lim	A study of IR-drop noise issues in 3D ICs with through-silicon-vias.	3DIC	2010	DBLP DOI BibTeX RDF
1	Jean-François Pratte, Marc-André Tétrault, Réjean Fontaine	High sensitivity fully digital photodetector.	3DIC	2010	DBLP DOI BibTeX RDF
1	Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli	Performance analysis of 3-D monolithic integrated circuits.	3DIC	2010	DBLP DOI BibTeX RDF
1	Xiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu, Chung-Kuan Cheng	Enabling power distribution network analysis flows for 3D ICs.	3DIC	2010	DBLP DOI BibTeX RDF
1	Harry Hedler, Thomas Scheiter, Markus Schieber, Armin Klumpp, Peter Ramm	High performance 3D interconnects based on electrochemical etch and liquid metal fill.	3DIC	2010	DBLP DOI BibTeX RDF
1	Peter Schneider, Andy Heinig, Robert Fischbach, Jens Lienig, Sven Reitz, Jörn Stolle, Andreas Wilde	Integration of multi physics modeling of 3D stacks into modern 3D data structures.	3DIC	2010	DBLP DOI BibTeX RDF
1	Weng Hong Teh, C. Deeb, J. Burggraf, D. Arazi, R. Young, C. Senowitz, A. Buxbaum	Post-bond sub-500 nm alignment in 300 mm integrated face-to-face wafer-to-wafer Cu-Cu thermocompression, Si-Si fusion and oxideoxide fusion bonding.	3DIC	2010	DBLP DOI BibTeX RDF
1	Vance Tyree	3DIC multi-project-wafer program: A collaboration to provide fabrication access.	3DIC	2010	DBLP DOI BibTeX RDF
1	Valerio Re	3D ICs and pixel sensors: The Italian VIPIX project and the European AIDA WP3 project.	3DIC	2010	DBLP DOI BibTeX RDF
1	Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda	Wafer-level hybrid bonding technology with copper/polymer co-planarization.	3DIC	2010	DBLP DOI BibTeX RDF
1	Young-Joon Lee, Sung Kyu Lim	Timing analysis and optimization for 3D stacked multi-core microprocessors.	3DIC	2010	DBLP DOI BibTeX RDF
1	Hanhua Qian, Xiwei Huang, Hao Yu 0001, Chip-Hong Chang	Real-time thermal management of 3D multi-core system with fine-grained cooling control.	3DIC	2010	DBLP DOI BibTeX RDF
1	Chuichi Miyazaki, Haruo Shimamoto, Toshihide Uematsu, Yoshiyuki Abe, Kosuke Kitaichi, Tadahiro Morifuji, Shoji Yasunaga	Development of high accuracy wafer thinning and pickup technology for thin wafer.	3DIC	2010	DBLP DOI BibTeX RDF
1	Ladislav Andricek, Michael Beimforde, Armin Klumpp, Anna Macchiolo, Karl-Reinhard Merkel, Hans-Günther Moser, Richard Nisius, Rainer Helmut Richter, Josef Weber, Philipp Weigell, Robert Wieland	Application of the SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC.	3DIC	2010	DBLP DOI BibTeX RDF
1	Fumihiro Inoue, Takumi Yokoyama, Hiroshi Miyake, Shukichi Tanaka, Toshifumi Terui, Tomohiro Shimizu, Shoso Shingubara	All-wet fabrication technology for high aspect ratio TSV using electroless barrier and seed layers.	3DIC	2010	DBLP DOI BibTeX RDF

Publications at "3DIC"( http://dblp.L3S.de/Venues/3DIC )