Search results for "ARC"

Hits ?▲	Authors	Title	Venue	Year	Link
28	Vanderlei Bonato, Christos Bouganis, Marek Gorgon (eds.)	Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings	ARC	2016	DBLP DOI BibTeX RDF
28	Mahnaz Mohammadi, Rohit Ronge, Sanjay S. Singapuram, S. K. Nandy 0001	Performance Evaluation of Feed-Forward Backpropagation Neural Network for Classification on a Reconfigurable Hardware Architecture.	ARC	2016	DBLP DOI BibTeX RDF
28	Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker 0001	A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems.	ARC	2016	DBLP DOI BibTeX RDF
28	Leonardo P. Santos, Gabriel L. Nazar, Luigi Carro	Low Cost Dynamic Scrubbing for Real-Time Systems.	ARC	2016	DBLP DOI BibTeX RDF
28	Stephanie Friederich, Niclas Lehmann, Jürgen Becker 0001	Adaptive Bandwidth Router for 3D Network-on-Chips.	ARC	2016	DBLP DOI BibTeX RDF
28	Jeckson Dellagostin Souza, João Victor Gomes Cachola, Luigi Carro, Mateus Beck Rutzig, Antonio Carlos Schneider Beck	Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System.	ARC	2016	DBLP DOI BibTeX RDF
28	Naru Sugimoto, Takaaki Miyajima, Ryotaro Sakai, Yasunori Osana, Naoyuki Fujita, Hideharu Amano	Zynq Cluster for CFD Parametric Survey.	ARC	2016	DBLP DOI BibTeX RDF
28	Evangelinos P. Mariatos, Christos P. Antonopoulos, Nikolaos S. Voros	EEG Feature Extraction Accelerator Enabling Long Term Epilepsy Monitoring Based on Ultra Low Power WSNs.	ARC	2016	DBLP DOI BibTeX RDF
28	Markus Weinhardt	Comparing Register-Transfer-, C-, and System-Level Implementations of an Image Enhancement Algorithm.	ARC	2016	DBLP DOI BibTeX RDF
28	Mário Lopes Ferreira, Amin Barahimi, João Canas Ferreira	Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications.	ARC	2016	DBLP DOI BibTeX RDF
28	José L. Núñez-Yáñez	Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application.	ARC	2016	DBLP DOI BibTeX RDF
28	Colm Kelly, Fahad Manzoor Siddiqui, Burak Bardak, Yun Wu, Roger F. Woods, Karen Rafferty	FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG.	ARC	2016	DBLP DOI BibTeX RDF
28	Yudai Shirakura, Taisei Segawa, Yuichiro Shibata, Kenichi Morimoto, Masaharu Tanaka, Masanori Nobe, Hidenori Maruta, Fujio Kurokawa	A Redundant Design Approach with Diversity of FPGA Resource Mapping.	ARC	2016	DBLP DOI BibTeX RDF
28	Masahito Oishi, Yoshiki Hayashida, Ryo Fujita, Yuichiro Shibata, Kiyoshi Oguri	A Comparison of Machine Learning Classifiers for FPGA Implementation of HOG-Based Human Detection.	ARC	2016	DBLP DOI BibTeX RDF
28	Marlon Wijeyasinghe, David Thomas 0001	A Multi-codec Framework to Enhance Data Channels in FPGA Streaming Systems.	ARC	2016	DBLP DOI BibTeX RDF
28	Jones Yudi Mori, Frederik Kautz, Michael Hübner 0001	Efficient Camera Input System and Memory Partition for a Vision Soft-Processor.	ARC	2016	DBLP DOI BibTeX RDF
28	James J. Davis 0001, Peter Y. K. Cheung	Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators.	ARC	2016	DBLP DOI BibTeX RDF
28	Karim M. Abdellatif, Christian Cornesse, Jacques J. A. Fournier, Bruno Robisson	New Partitioning Approach for Hardware Trojan Detection Using Side-Channel Measurements.	ARC	2016	DBLP DOI BibTeX RDF
28	Tomasz Kryjak, Marek Gorgon, Mateusz Komorkiewicz	An Efficient Hardware Architecture for Block Based Image Processing Algorithms.	ARC	2016	DBLP DOI BibTeX RDF
28	Shaojun Wang, Xinyu Niu, Ning Ma, Wayne Luk, Philip H. W. Leong, Yu Peng	A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification.	ARC	2016	DBLP DOI BibTeX RDF
28	Shreyas G. Singapura, Yi-Hua E. Yang, Anand V. Panangadan, Tamás Németh, Peter Ng, Viktor K. Prasanna	FPGA-Based Acceleration of Pattern Matching in YARA.	ARC	2016	DBLP DOI BibTeX RDF
28	Christoforos Kachris, Dimitrios Soudris, Georgi Gaydadjiev, Huy-Nam Nguyen, Dimitrios S. Nikolopoulos, Angelos Bilas, Neil Morgan, Christos Strydis, Christos Tsalidis, John Balafas, Ricardo Jiménez-Peris, Alexandre Almeida	The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres.	ARC	2016	DBLP DOI BibTeX RDF
28	Abiel Aguilar-González, Miguel O. Arias-Estrada	An FPGA Stereo Matching Processor Based on the Sum of Hamming Distances.	ARC	2016	DBLP DOI BibTeX RDF
28	Bruno da Silva 0001, Jan Lemeire, An Braeken, Abdellah Touhafi	A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis.	ARC	2016	DBLP DOI BibTeX RDF
28	Falco K. Bapp, Oliver Sander, Timo Sandmann, Hannes Stoll, Jürgen Becker 0001	Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures.	ARC	2016	DBLP DOI BibTeX RDF
28	Jones Yudi Mori, André Werner 0001, Arij Shallufa, Florian Fricke, Michael Hübner 0001	A Design Methodology for the Next Generation Real-Time Vision Processors.	ARC	2016	DBLP DOI BibTeX RDF
28	Konrad Häublein, Christian Hartmann 0003, Marc Reichenbach, Dietmar Fey	Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks.	ARC	2016	DBLP DOI BibTeX RDF
28	Jorge L. Tonfat, Lucas A. Tambara, André Flores dos Santos, Fernanda Gusmão de Lima Kastensmidt	Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors.	ARC	2016	DBLP DOI BibTeX RDF
28	Mohammad Tahghighi, Sharad Sinha, Wei Zhang 0012	Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA.	ARC	2016	DBLP DOI BibTeX RDF
28	Arthur Spierer, Andres Upegui	Real-Time Audio Group Delay Correction with FFT Convolution on FPGA.	ARC	2016	DBLP DOI BibTeX RDF
28	Bilal Habib, Kris Gaj	A Comprehensive Set of Schemes for PUF Response Generation.	ARC	2016	DBLP DOI BibTeX RDF
28	Vitor Coimbra, Marcus Vinicius Lamar	Design and Optimization of Digital Circuits by Artificial Evolution Using Hybrid Multi Chromosome Cartesian Genetic Programming.	ARC	2016	DBLP DOI BibTeX RDF
28	Kentaro Sano, Dimitrios Soudris, Michael Hübner 0001, Pedro C. Diniz (eds.)	Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings	ARC	2015	DBLP DOI BibTeX RDF
28	Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos	Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures.	ARC	2015	DBLP DOI BibTeX RDF
28	Ioannis Papaefstathiou, Gregory Chrysos, Lambros Sarakis	COSSIM: A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator.	ARC	2015	DBLP DOI BibTeX RDF
28	Ren Chen, Viktor K. Prasanna	DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems.	ARC	2015	DBLP DOI BibTeX RDF
28	Hichem Ben Fekih, Ahmed Elhossini, Ben H. H. Juurlink	An Efficient and Flexible FPGA Implementation of a Face Detection System.	ARC	2015	DBLP DOI BibTeX RDF
28	Philipp A. Hartmann, Kim Grüttner, Wolfgang Nebel	Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties.	ARC	2015	DBLP DOI BibTeX RDF
28	João Carlos Resende, Ricardo Chaves	Dual CLEFIA/AES Cipher Core on FPGA.	ARC	2015	DBLP DOI BibTeX RDF
28	George Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, Dionisios N. Pnevmatikatos	Hardware Task Scheduling for Partially Reconfigurable FPGAs.	ARC	2015	DBLP DOI BibTeX RDF
28	Retsu Moriwaki, Hiroyuki Ito, Kouta Akagi, Minoru Watanabe, Akifumi Ogiwara	Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array.	ARC	2015	DBLP DOI BibTeX RDF
28	Zoltán Endre Rákossy, Dominik Stengele, Axel Acosta-Aponte, Saumitra Chafekar, Paolo Bientinesi, Anupam Chattopadhyay	Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA.	ARC	2015	DBLP DOI BibTeX RDF
28	Thiago Baldissera Biazus, Mateus Beck Rutzig	Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks.	ARC	2015	DBLP DOI BibTeX RDF
28	Paulo Matias, Rafael Tuma Guariento, Lírio Onofre Baptista de Almeida, Jan Frans Willem Slaets	Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments.	ARC	2015	DBLP DOI BibTeX RDF
28	Shimpei Sato, Kenji Kise	ArchHDL: A Novel Hardware RTL Design Environment in C++.	ARC	2015	DBLP DOI BibTeX RDF
28	Fynn Schwiegelshohn, Eugen Ossovski, Michael Hübner 0001	A Fully Parallel Particle Filter Architecture for FPGAs.	ARC	2015	DBLP DOI BibTeX RDF
28	Rehan Ahmed, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas	Hierarchical Dynamic Power-Gating in FPGAs.	ARC	2015	DBLP DOI BibTeX RDF
28	Hiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao	A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank.	ARC	2015	DBLP DOI BibTeX RDF
28	Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul	Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform.	ARC	2015	DBLP DOI BibTeX RDF
28	Jens Rettkowski, Philipp Wehner, Marc Schülper, Diana Göhringer	A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context.	ARC	2015	DBLP DOI BibTeX RDF
28	Tobias Wiersema, Sen Wu 0005, Marco Platzner	On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.	ARC	2015	DBLP DOI BibTeX RDF
28	Takuma Usui, Ryohei Kobayashi, Kenji Kise	A Challenge of Portable and High-Speed FPGA Accelerator.	ARC	2015	DBLP DOI BibTeX RDF
28	Shreyas G. Singapura, Anand V. Panangadan, Viktor K. Prasanna	Towards Performance Modeling of 3D Memory Integrated FPGA Architectures.	ARC	2015	DBLP DOI BibTeX RDF
28	Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid	Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization.	ARC	2015	DBLP DOI BibTeX RDF
28	Zaid Al-Khatib, Samar Abdi	Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA.	ARC	2015	DBLP DOI BibTeX RDF
28	Luca Sterpone, Boyang Du	SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs.	ARC	2015	DBLP DOI BibTeX RDF
28	Salma Hesham, Jens Rettkowski, Diana Göhringer, Mohamed A. Abd El Ghany	Survey on Real-Time Network-on-Chip Architectures.	ARC	2015	DBLP DOI BibTeX RDF
28	Shinya Takamaeda-Yamazaki	Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL.	ARC	2015	DBLP DOI BibTeX RDF
28	Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner 0001, Diana Göhringer, Maria Dagioglou, Theodoros Giannakopoulos, Stasinos Konstantopoulos, Vangelis Karkaletsis	Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective.	ARC	2015	DBLP DOI BibTeX RDF
28	Ian Graves, Adam M. Procter, William L. Harrison, Michela Becchi, Gerard Allwein	Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation.	ARC	2015	DBLP DOI BibTeX RDF
28	Tobias Strauch	The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs.	ARC	2015	DBLP DOI BibTeX RDF
28	Yaman Umuroglu, Magnus Jahre	A Vector Caching Scheme for Streaming FPGA SpMV Accelerators.	ARC	2015	DBLP DOI BibTeX RDF
28	Pavlos Giakoumakis, Grigorios Chrysos 0001, Apostolos Dollas, Ioannis Papaefstathiou	Acceleration of Data Streaming Classification using Reconfigurable Technology.	ARC	2015	DBLP DOI BibTeX RDF
28	Vasileios Tsoutsouras, Sotirios Xydis, Dimitrios Soudris, Leonidas Lymperopoulos	SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring.	ARC	2015	DBLP DOI BibTeX RDF
28	Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker 0001	A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware.	ARC	2015	DBLP DOI BibTeX RDF
28	Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios, Dimitrios Soudris	Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures.	ARC	2015	DBLP DOI BibTeX RDF
28	Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume	Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture.	ARC	2015	DBLP DOI BibTeX RDF
28	Michael Metzner, Jesus Lizarraga, Christophe Bobda	Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays.	ARC	2015	DBLP DOI BibTeX RDF
28	Zeyad Aklah, David Andrews 0001	A Flexible Multilayer Perceptron Co-processor for FPGAs.	ARC	2015	DBLP DOI BibTeX RDF
28	Lucas A. Tambara, Felipe Almeida, Paolo Rech, Fernanda Lima Kastensmidt, Giovanni Bruni, Christopher Frost 0002	Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects.	ARC	2015	DBLP DOI BibTeX RDF
28	Xerach Peña, Fernando Rincón, Julio Dondo, Julián Caba, Juan Carlos López 0001	Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components.	ARC	2015	DBLP DOI BibTeX RDF
28	Philipp Gorski, Tim Wegner, Dirk Timmermann	Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip.	ARC	2015	DBLP DOI BibTeX RDF
28	Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos 0001, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker 0001	TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools.	ARC	2015	DBLP DOI BibTeX RDF
28	Ernesto Villegas Castillo, Gabriele Miorandi, Davide Bertozzi, Jiang Chau Wang	DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost.	ARC	2015	DBLP DOI BibTeX RDF
28	Markus Happe, Andreas Traber, Ariane Keller	Preemptive Hardware Multitasking in ReconOS.	ARC	2015	DBLP DOI BibTeX RDF
28	Andreas Raptopoulos, Sotirios Xydis, Dimitrios Soudris	Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach.	ARC	2015	DBLP DOI BibTeX RDF
28	Nele Mentens, Jochen Vandorpe, Jo Vliegen, An Braeken, Bruno da Silva 0001, Abdellah Touhafi, Alois Kern, Stephan Knappmann, Jens Rettkowski, Muhammed Al Kadi, Diana Göhringer, Michael Hübner 0001	DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications.	ARC	2015	DBLP DOI BibTeX RDF
28	Anupam Chattopadhyay, Xiaolin Chen	A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures.	ARC	2015	DBLP DOI BibTeX RDF
28	Ekawat Homsirikamol, Kris Gaj	Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study.	ARC	2015	DBLP DOI BibTeX RDF
28	Maikon Adiles Fernandez Bueno, Carlos R. P. Almeida Jr., José A. M. de Holanda, Eduardo Marques	Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs.	ARC	2015	DBLP DOI BibTeX RDF
28	Bilal Habib, Jens-Peter Kaps, Kris Gaj	Efficient SR-Latch PUF.	ARC	2015	DBLP DOI BibTeX RDF
28	George Lentaris, Ioannis Stamoulias, Dionysios Diamantopoulos, Konstantinos Maragos 0001, Kostas Siozios, Dimitrios Soudris, Marcos Avilés Rodrigálvarez, Manolis I. A. Lourakis, Xenophon Zabulis, Ioannis Kostavelis, Lazaros Nalpantidis, Evangelos Boukas, Antonios Gasteratos	SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms.	ARC	2015	DBLP DOI BibTeX RDF
28	Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, Mitsuhisa Sato	Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing.	ARC	2015	DBLP DOI BibTeX RDF
28	Diana Goehringer, Marco Domenico Santambrogio, João M. P. Cardoso, Koen Bertels (eds.)	Reconfigurable Computing: Architectures, Tools, and Applications - 10th International Symposium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Proceedings	ARC	2014	DBLP DOI BibTeX RDF
28	Giuseppe Massari, Edoardo Paone, Michele Scandale, Patrick Bellasi, Gianluca Palermo, Vittorio Zaccaria, Giovanni Agosta, William Fornaciari, Cristina Silvano	Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures.	ARC	2014	DBLP DOI BibTeX RDF
28	Tassadaq Hussain, Oscar Palomar, Osman S. Ünsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Amna Haider	Stand-Alone Memory Controller for Graphics System.	ARC	2014	DBLP DOI BibTeX RDF
28	Ihsen Alouani, Mazen A. R. Saghir, Smaïl Niar	ARABICA: A Reconfigurable Arithmetic Block for ISA Customization.	ARC	2014	DBLP DOI BibTeX RDF
28	Neil Scicluna, Christos-Savvas Bouganis	FPGA-Based Parallel DBSCAN Architecture.	ARC	2014	DBLP DOI BibTeX RDF
28	Pascal Sasdrich, Tim Güneysu	Efficient Elliptic-Curve Cryptography Using Curve25519 on Reconfigurable Devices.	ARC	2014	DBLP DOI BibTeX RDF
28	Chao Wang 0003, Xi Li 0003, Huizhen Zhang, Liang Shi, Xuehai Zhou	Instruction Extension and Generation for Adaptive Processors.	ARC	2014	DBLP DOI BibTeX RDF
28	Umar Ibrahim Minhas, Samuel Bayliss, George A. Constantinides	GPU vs FPGA: A Comparative Analysis for Non-standard Precision.	ARC	2014	DBLP DOI BibTeX RDF
28	Takashi Yoza, Minoru Watanabe	Enhanced Radiation Tolerance of an Optically Reconfigurable Gate Array by Exploiting an Inversion/Non-inversion Implementation.	ARC	2014	DBLP DOI BibTeX RDF
28	Jecel Mattos de Assumpção Jr., Merik Voswinkel, Eduardo Marques	Adapting Processor Grain via Reconfiguration.	ARC	2014	DBLP DOI BibTeX RDF
28	Rui Policarpo Duarte, Christos-Savvas Bouganis	A Unified Framework for Over-Clocking Linear Projections on FPGAs under PVT Variation.	ARC	2014	DBLP DOI BibTeX RDF
28	Jie Li 0004, Amin Salighehdar, Narayan Ganesan	Simulation of Complex Biochemical Pathways in 3D Process Space via Heterogeneous Computing Platform: Preliminary Results.	ARC	2014	DBLP DOI BibTeX RDF
28	Rinse Wester, Jan Kuper	Design Space Exploration of a Particle Filter Using Higher-Order Functions.	ARC	2014	DBLP DOI BibTeX RDF
28	Kaoru Hamasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri	FPGA Implementation of a Video Based Abnormal Action Detection System with Real-Time Cubic Higher Order Local Auto-Correlation Analysis.	ARC	2014	DBLP DOI BibTeX RDF
28	B. Chagun Basha, Stanislaw J. Piestrak, Sébastien Pillement	Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs.	ARC	2014	DBLP DOI BibTeX RDF
28	Christopher Pöpper, Oliver Mischke, Tim Güneysu	MicroACP - A Fast and Secure Reconfigurable Asymmetric Crypto-Processor - -Overhead Evaluation of Side-Channel Countermeasures-.	ARC	2014	DBLP DOI BibTeX RDF
28	Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado	Accelerating Heap-Based Priority Queue in Image Coding Application Using Parallel Index-Aware Tree Access.	ARC	2014	DBLP DOI BibTeX RDF