Search results for "ASYNC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster	Synchronous Interlocked Pipelines.	ASYNC	2002	DBLP DOI BibTeX RDF	progressive stalls, synchronous, Pipeline, asynchronous, clock gating, elastic, interlocked
1	George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson 0001	Point to Point GALS Interconnect.	ASYNC	2002	DBLP DOI BibTeX RDF
1	Metehan Özcan, Masashi Imai, Takashi Nanya	Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits.	ASYNC	2002	DBLP DOI BibTeX RDF
1	Mark R. Greenstreet, Brian de Alwis	How to Achieve Worst-Case Performance.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Ivan E. Sutherland, Jon K. Lexau	Designing Fast Asynchronous Circuits.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Alexandre Yakovlev, Fei Xia, Delong Shang	Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Chris J. Myers, Hans M. Jacobson	Efficient Exact Two-Level Hazard-Free Logic Minimization.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri	PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Ivan E. Sutherland, Scott Fairbanks	GasP: A Minimal FIFO Control.	ASYNC	2001	DBLP DOI BibTeX RDF
1		7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA	ASYNC	2001	DBLP BibTeX RDF
1	William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland	FLEETzero: An Asynchronous Switching Experiment.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Ajay Koche	Testing Asynchronous Circuits: Help is on the Way!	ASYNC	2001	DBLP DOI BibTeX RDF
1	Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno	Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Tony Werner, Venkatesh Akella	An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism.	ASYNC	2001	DBLP DOI BibTeX RDF
1	David W. Lloyd, Jim D. Garside	A Practical Comparison of Asynchronous Design Styles.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Mike J. G. Lewis, L. E. M. Brackenbury	Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Ad M. G. Peeters, Kees van Berkel 0001	Synchronous Handshake Circuits.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Kevin Normoyle	Where are the Async Millionaires?	ASYNC	2001	DBLP DOI BibTeX RDF
1	Bill Athas	Asynchronous Design and the Pursuit of Low Power.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Gianluca Cornetta, Jordi Cortadella	A Multi-Radix Approach to Asynchronous Division.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Robert Berks, Radu Negulescu	Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Joep L. W. Kessels, Ad M. G. Peeters, Torsten Kramer, Markus Feuser, Klaus Ully	Designing an Asynchronous Bus Interface.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Jo C. Ebergen	Squaring the FIFO in GasP.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Rajit Manohar	An Analysis of Reshuffled Handshaking Expansions.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Daranee Hormdee, Jim D. Garside	AMULET3i Cache Architecture.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Peter A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber	A Low-Power Self-Timed Viterbi Decoder.	ASYNC	2001	DBLP DOI BibTeX RDF
1	W. J. Bainbridge, Stephen B. Furber	Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Montek Singh, Steven M. Nowick	High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths.	ASYNC	2000	DBLP DOI BibTeX RDF	fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design
1	Charles E. Molnar, Ian W. Jones	Simple Circuits that Work for Complicated Reasons.	ASYNC	2000	DBLP DOI BibTeX RDF	MUTEX, Delay measurement technique, Latch control circuit, Charlie Box, Asynchronous, FIFO, Arbiter, Micropipeline
1	Willem C. Mallon	On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism.	ASYNC	2000	DBLP DOI BibTeX RDF	{Communicating Processes}, {Computer Aided Design}, Meta-stability, Formal Methods, Handshake Protocol, Delay-Insensitivity
1	Jens Muttersbach, Thomas Villiger, Wolfgang Fichtner	Practical Design of Globally-Asynchronous Locally-Synchronous Systems.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Fei Xia, Alexandre Yakovlev, Delong Shang, Alexandre V. Bystrov, Albert Koelmans, D. J. Kinniment	Asynchronous Communication Mechanisms Using Self-Timed Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Oliver Hauck, A. Katoch, Sorin A. Huss	VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee	Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Michiel M. Ligthart, Karl Fant, Ross Smith, Alexander Taubin, Alex Kondratyev	Asynchronous Design Using Commercial HDL Synthesis Tools.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev	Formal Verification of Safety Properties in Timed Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	Formal verification, asynchronous circuits, timing analysis
1	Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva	High-Level Asynchronous System Design Using the ACK Framework.	ASYNC	2000	DBLP DOI BibTeX RDF
1		6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel	ASYNC	2000	DBLP BibTeX RDF
1	George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson 0001	An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
1	Ivan Blunno, Luciano Lavagno	Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Igor Benko, Jo C. Ebergen	Composing Snippets.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Mike J. G. Lewis, L. E. M. Brackenbury	An Instruction Buffer for a Low-Power DSP.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Alexandre V. Bystrov, D. J. Kinniment, Alexandre Yakovlev	Priority Arbiters.	ASYNC	2000	DBLP DOI BibTeX RDF	dynamic priority, asynchronous circuits, concurrent systems, arbiters, static priority
1	Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm	Applying Asynchronous Circuits in Contactless Smart Cards.	ASYNC	2000	DBLP DOI BibTeX RDF	low-power asynchronous circuits, contactless devices, DES cryptography, smart cards
1	Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, Siamak Mohammadi, J. S. Pepper, Steve Temple, John V. Woods, Jianwei Liu, O. Petli	AMULET3i - An Asynchronous System-on-Chip.	ASYNC	2000	DBLP DOI BibTeX RDF
1	Tiberiu Chelcea, Steven M. Nowick	Low-Latency Asynchronous FIFO's Using Token Rings.	ASYNC	2000	DBLP DOI BibTeX RDF	VLSI, asynchronous, FIFO, low-latency, digital design, token ring
1	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
1	Willem C. Mallon, Jan Tijmen Udding, Tom Verhoeff	Analysis and Applications of the XDI model.	ASYNC	1999	DBLP DOI BibTeX RDF	Verification, Factorization, Derivation, Communicating Processes, Delay Insensitivity
1	David A. Kearney	Theoretical Limits on the Data Dependent Performance of Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Märt Saarepera, Tomohiro Yoneda	A Self-Timed Implementation of Boolean Functions.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Per Arne Karlsen, Per Torstein Røine	A Timing Verifier and Timing Profiler for Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury	Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Tod Amon, Henrik Hulgaard	Symbolic Time Separation of Events.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Bill Coates 0001, Jo C. Ebergen, Jon K. Lexau, Scott Fairbanks, Ian W. Jones, Alex Ridgway, David Money Harris, Ivan E. Sutherland	A Counterflow Pipeline Experiment.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Oliver Hauck, M. Garg, Sorin A. Huss	Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Wendy Belluomini, Chris J. Myers, H. Peter Hofstee	Verification of Delayed-Reset Domino Circuits Using ATACS.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Rajit Manohar, Tak-Kwan Lee, Alain J. Martin	Projection: A Synthesis Technique for Concurrent Systems.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Mark R. Greenstreet, Tarik Ono-Tesfaye	A Fast, asP*, RGD Arbiter.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Mark R. Greenstreet	Real-Time Merging.	ASYNC	1999	DBLP DOI BibTeX RDF	bounded-time, receptive mixer, real-time, merging, arbitration, metastability
1	Ken S. Stevens, Shai Rotem, Ran Ginosar	Relative Timing.	ASYNC	1999	DBLP DOI BibTeX RDF
1	David W. Lloyd, Jim D. Garside, D. A. Gilbert	Memory Faults in Asynchronous Microprocessors.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Jim D. Garside, Stephen B. Furber, S.-H. Chung	AMULET3 Revealed.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Marc Renaudin, Pascal Vivet, Frédéric Robin	A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun	RAPPID: An Asynchronous Instruction Length Decoder.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Aiguo Xie, Sangyun Kim 0001, Peter A. Beerel	Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Tomohiro Yoneda, Hiroshi Ryu	Timed Trace Theoretic Verification Using Partial Order Reduction.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Alexander Taubin, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno	Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Jochen Beister, Gernot Eckstein, Ralf Wollowski	From STG to Extended-Burst-Mode Machines.	ASYNC	1999	DBLP DOI BibTeX RDF
1		5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 19-22 April 1999, Barcelona, Spain	ASYNC	1999	DBLP BibTeX RDF
1	Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet	Verifying a Self-Timed Divider.	ASYNC	1998	DBLP DOI BibTeX RDF	model checking, refinement, asynchronous, hardware verification, timing verification, self-timed, speed-independence
1		4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA	ASYNC	1998	DBLP BibTeX RDF
1	Marc Renaudin, Pascal Vivet, Frédéric Robin	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.	ASYNC	1998	DBLP DOI BibTeX RDF	asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
1	Aiguo Xie, Peter A. Beerel	Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression.	ASYNC	1998	DBLP DOI BibTeX RDF	stationary analysis, state compression, performance evaluation, Asynchronous systems, power estimation, convergence rate, Markov chain models, feedback vertex set
1	Kåre Tais Christensen, Peter Jensen, Peter Korger, Jens Sparsø	The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core.	ASYNC	1998	DBLP DOI BibTeX RDF	Asynchronous circuits and systems, low-power, microprocessor design
1	W. J. Bainbridge, Stephen B. Furber	Asynchronous Macrocell Interconnect using MARBLE.	ASYNC	1998	DBLP DOI BibTeX RDF	Macrocell Bus, VLSI, Interconnect, Asynchronous
1	William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland	A FIFO Data Switch Design Experiment.	ASYNC	1998	DBLP DOI BibTeX RDF	Data Switch, P**3, Asynchronous, FIFO
1	Michael Theobald, Steven M. Nowick	An Implicit Method for Hazard-Free Two-Level Logic Minimization.	ASYNC	1998	DBLP DOI BibTeX RDF	hazard-free, two-level, dynamic-hazard-free prime implicants, asynchronous, BDD, logic minimization, implicit
1	Hans van Gageldonk, Kees van Berkel 0001, Ad M. G. Peeters, Daniel Baumann, Daniel Gloor, Gerhard Stegmann	An Asynchronous Low-Power 80C51 Microcontroller.	ASYNC	1998	DBLP DOI BibTeX RDF	VLSI-programming, low-power, microcontrollers, asynchronous design
1	Willem C. Mallon, Jan Tijmen Udding	Building Finite Automata from DI Specifications.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Nigel C. Paver, Paul Day, Craig Farnsworth, Dave L. Jackson, Warren A. Lien, Jianwei Liu	A Low-Power, Low-Noise, Configurable Self-Timed DSP.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Jo C. Ebergen, Scott Fairbanks, Ivan E. Sutherland	Predicting Performance of Micropipelines Using Charlie Diagrams.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya	Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic.	ASYNC	1998	DBLP DOI BibTeX RDF	pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit
1	Kevin W. James, Kenneth Y. Yun	Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Stanislaw J. Piestrak	Membership Test Logic for Delay-Insensitive Codes.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Martin Benes 0002, Steven M. Nowick, Andrew Wolfe	A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors.	ASYNC	1998	DBLP DOI BibTeX RDF	Huffman encoding, embedded systems, asynchronous, embedded processors, dynamic logic, hazards, digital design
1	Tom Verhoeff	Analyzing Specifications for Delay-Insensitive Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Per Torstein Røine	An Asynchronous PRBS Error Checker for Testing High-Speed Self-Clocked Serial Links.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang	An Asynchronous 2-D Discrete Cosine Transform Chip.	ASYNC	1998	DBLP DOI BibTeX RDF	DCT, asynchronous, threshold logic, bit-serial
1	D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao	Towards Asynchronous A-D Conversion.	ASYNC	1998	DBLP DOI BibTeX RDF	analogue to digital conversion, synchronisers, asynchronous circuits, arbitration, signal transition graphs, metastability
1	Radu Negulescu, Ad M. G. Peeters	Verification of Speed-Dependences in Single-Rail Handshake Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF	single-rail, isochronic forks, verification, timing, asynchronous circuits, progress, speed-independent circuits, process spaces, handshake circuits
1	Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun	Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Bruce W. Hunt, Kenneth S. Stevens, Bruce W. Suter, Donald S. Gelosh	A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications.	ASYNC	1998	DBLP DOI BibTeX RDF	Radiation Tolerant, VLSI, FFT, Asynchronous
1	Z. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno	Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology.	ASYNC	1998	DBLP DOI BibTeX RDF
1	Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell	Delay Insensitive Logic for RSFQ Superconductor Technology.	ASYNC	1997	DBLP DOI BibTeX RDF
1	David A. Kearney, Neil W. Bergmann	Bundled Data Asynchronous Multipliers with Data Dependent Computation Times.	ASYNC	1997	DBLP DOI BibTeX RDF	asynchronous logic data dependent performance multiplier
1	D. A. Gilbert, Jim D. Garside	A Result Forwarding Mechanism for Asynchronous Pipelined Systems.	ASYNC	1997	DBLP DOI BibTeX RDF	dependency, asynchronous, Exception, reorder buffer
1	Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun	Timing Analysis of Extended Burst-Mode Circuits.	ASYNC	1997	DBLP DOI BibTeX RDF	Extended burst-mode circuits, 3D design style, global timing constraints, uncertain component delays, thirteen-valued signal algebra, polynomial-time
1	Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella, Luciano Lavagno	Partial order based approach to synthesis of speed-independent circuits.	ASYNC	1997	DBLP DOI BibTeX RDF	approximation, synthesis, asynchronous circuits, unfolding, Signal Transition Graph
1	Gensoh Matsubara, Nobuhiro Ide	A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit.	ASYNC	1997	DBLP DOI BibTeX RDF	floating point, division, square root, self-timed

Publications at "ASYNC"( http://dblp.L3S.de/Venues/ASYNC )