Search results for "CMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Liangxiu Han, Asen Asenov, Dave Berry, Campbell Millar, Gareth Roy, Scott Roy, Richard O. Sinnott, Gordon Stewart 0002	Towards a Grid-Enabled Simulation Framework for Nano-CMOS Electronics.	eScience	2007	DBLP DOI BibTeX RDF
18	Ming-Dou Ker, Hung-Tai Liao	Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Alexander Fish, Tomer Rothschild, Avichay Hodes, Yonatan Shoshan, Orly Yadid-Pecht	Low Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB2C) Approach.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Adrian Tang 0002, Fei Yuan 0005, Eddie Law	A New CMOS BPSK Modulator with Optimal Transaction Bandwidth Control.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria	Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Minsik Ahn, Chang-Ho Lee, Joy Laskar	CMOS High Power SPDT Switch using Multigate Structure.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Joan Lluís Lopez, Jordi Teva, Arantxa Uranga, Francesc Torres 0001, Jaume Verd, Gabriel Abadal, Núria Barniol, Jaume Esteve, Francesc Pérez-Murano	Mixing in a 220MHz CMOS-MEMS.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Bradley A. Minch	Low-Voltage Wilson Current Mirrors in CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
18	José C. García 0001, Juan A. Montiel-Nelson, Saeid Nooshabadi	Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Hsiao Wei Su, Zhi Hua Wang	The Impact of Different Gain Control Methods on Performance of CMOS Variable-Gain LNA.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Shubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, Ramesh Harjani	High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Behzad Razavi	CMOS Transceivers at 60 GHz and Beyond1.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Georges G. E. Gielen	Future trends for wireless communication frontends in nanometer CMOS.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	RF frontends, wireless sensor networks, wireless communication, integrated circuits, reconfigurable hardware
18	Jeong-A Im, Dae Woong Kim, Ki-Sang Hong	Digital Video Stabilization Algorithm for CMOS Image Sensor.	ICIP	2006	DBLP DOI BibTeX RDF
18	Bilge Saglam Akgul, Lakshmi N. Chakrapani, Pinar Korkmaz, Krishna V. Palem	Probabilistic CMOS Technology: A Survey and Future Directions.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
18	Dmitri B. Strukov, Konstantin K. Likharev	A reconfigurable architecture for hybrid CMOS/Nanodevice circuits.	FPGA	2006	DBLP DOI BibTeX RDF	integrated hybrid circuits, architecture, programmable logic, nanoelectronics, programmable interconnect
18	Lakshmi N. Chakrapani, Bilge Saglam Akgul, Suresh Cheemalavagu, Pinar Korkmaz, Krishna V. Palem, Balasubramanian Seshasayee	Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology.	DATE	2006	DBLP DOI BibTeX RDF
18	Kambiz K. Moez, Mohammad Ibrahim Elmasry	A novel loss compensation technique for broadband CMOS distributed amplifiers.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Omer Can Akgun, Yusuf Leblebici	Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Ranjith Kumar, Volkan Kursun	Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Saeed Saeedi, Saeid Mehrmanesh, Armin Tajalli, Seyed Mojtaba Atarodi	A technique to suppress tail current flicker noise in CMOS LC VCOs.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Baoyong Chi, Bingxue Shi, Zhihua Wang 0001	A CMOS down-conversion micromixer for IEEE 802.11b WLAN transceivers.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Yijun Zhou, Michael Yan Wah Chia	A wide band CMOS RF power detector.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Francisco Tejada, Andreas G. Andreou, Philippe O. Pouliquen	Stacked, standing wave detectors in 3D SOI-CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Yijin Wang, Ming Hsing, Chen Xu, Jiong Li, Mansun Chan	A single chip micro-DNA-array system based on CMOS image sensor technology.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Anis Nurashikin Nordin, Mona E. Zaghloul	Design and implementation of a 1GHz CMOS resonator utilizing surface acoustic wave.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Pablo Sergio Mandolesi, Pedro Julián, Andreas G. Andreou	A simplicial CNN visual processor in 3D SOI-CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Matti Paavola, Mika Laiho, Mikko Saukoski, Kari Halonen	A 3µW, 2 MHz CMOS frequency reference for capacitive sensor applications.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Massimo Alioto, Gaetano Palumbo, Massimo Poli	Efficient output transition time modeling in CMOS gates with ramp/exponential inputs.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Arantxa Uranga, Jordi Teva, Jaume Verd, Joan Lluís Lopez, Francesc Torres 0001, Gabriel Abadal, Núria Barniol, Jaume Esteve, Francesc Pérez-Murano	CMOS integrated MEMS resonator for RF applications.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Erhan Ozalevli, Paul E. Hasler	A tunable floating gate CMOS resistor for low-power and low-voltage applications.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Ta-Tao Hsu, Chien-Nan Kuo	Low voltage 2-mW 6~10.6-GHz ultra-wideband CMOS mixer with active balun.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Tung N. Pham, Earl E. Swartzlander Jr.	Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology.	ASAP	2006	DBLP DOI BibTeX RDF
18	H.-S. Philip Wong	Device and Technology Challenges for Nanoscale CMOS.	ISQED	2006	DBLP DOI BibTeX RDF
18	Hsin-Chyh Hsu, Ming-Dou Ker	Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask.	ISQED	2006	DBLP DOI BibTeX RDF
18	Woochul Jeon, John Melngailis, Robert W. Newcomb	CMOS Schottky diode microwave power detector fabrication, Spice modeling, and applications.	DELTA	2006	DBLP DOI BibTeX RDF
18	Supriya S. Shanbhag	CMOS Integrated Circuit for Sensing Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler	Hybrid CMOS/Molecular Electronic Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Yasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekine, Michio Yokoyama	2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Chris Siu, Soraya Kasnavi, Kris Iniewski, Frederic Nabki	RF CMOS Circuits for Ad-Hoc Networks and Wearable Computing.	DSD	2005	DBLP DOI BibTeX RDF
18	Abdelkarim Mercha	Technology and architecture for deep submicron RF CMOS technology.	SBCCI	2005	DBLP DOI BibTeX RDF
18	Honghao Ji, Pamela Abshire, M. Urdaneta, Elisabeth Smela	CMOS contact imager for monitoring cultured cells.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
18	T. Hasan, Torsten Lehmann, Chee Yee Kwok	A 5V charge pump in a standard 1.8-V 0.18-µm CMOS process.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
18	Xuefeng Yu, Foster F. Dai, Yin Shi, Ronghua Zhu	2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
18	Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan	Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Shouli Yan, Jingyu Hu, Tongyu Song	Novel and robust constant-gm technique for rail-to-rail CMOS amplifier input stages.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Tadayoshi Enomoto, Nobuaki Kobayashi	A low dynamic power and low leakage power CMOS square-root circuit.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
18	Erhan Ozalevli, Paul E. Hasler	Programmable floating-gate CMOS resistors.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi	CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.	ASP-DAC	2004	DBLP DOI BibTeX RDF
18	Vojkan Vidojkovic, Johan van der Tang, Eric Hanssen, Arjan J. Leeuwenburgh, Arthur H. M. van Roermund	Low voltage, low power folded-switching mixer with current-reuse in 0.18µm CMOS.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
18	Seoung-Jae Yoo, Arun Ravindran, Mohammed Ismail 0001	A low voltage CMOS transresistance-based variable gain amplifier.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
18	Chin-Long Wey, Mohammad Athar Khalil, Jim Liu, Gregory Wierzba	Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	IC reliability
18	Alexandre Schmid, Yusuf Leblebici	A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies.	DFT	2004	DBLP DOI BibTeX RDF
18	Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman	High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.	ISQED	2004	DBLP DOI BibTeX RDF
18	Narender Hanchate, Nagarajan Ranganathan	A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.	VLSI Design	2004	DBLP DOI BibTeX RDF
18	Li Ding 0002, Pinaki Mazumder	A novel technique to improve noise immunity of CMOS dynamic logic circuits.	DAC	2004	DBLP DOI BibTeX RDF	domino logic style, negative differential resistance, noise-tolerant design, digital integrated circuits, dynamic circuits
18	Khalid H. Abed, Raymond E. Siferd	CMOS VLSI Implementation of a Low-Power Logarithmic Converter.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Anti-logarithm, binary logarithms, floating-point normalization, leading-one detector, elementary functions, logarithmic number system, low-power circuits
18	Se-Hyun Yang, Babak Falsafi	Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches.	MICRO	2003	DBLP DOI BibTeX RDF
18	Julio Arlindo Pinto Azevedo, Tales Cleber Pimenta	Design of a Low Noise Amplifier for CDMA Transceivers at 900MHz in CMOS 0.35 µm.	SBCCI	2003	DBLP DOI BibTeX RDF
18	Alessandra Nardi, Haibo Zeng 0001, Joshua L. Garrett, Luca Daniel, Alberto L. Sangiovanni-Vincentelli	A Methodology for the Computation of an Upper Bound on Nose Current Spectrum of CMOS Switching Activity.	ICCAD	2003	DBLP DOI BibTeX RDF
18	Farid Boussaïd, Amine Bermak, Abdesselam Bouzerdoum	Programmable Multi-Task On-Chip Processing for CMOS Imagers.	ICMENS	2003	DBLP DOI BibTeX RDF
18	Ertan Zencir, Numan Sadi Dogan, Ercument Arvas, Mohammed Ketel	A low-power low-noise amplifier in 0.35µm SOI CMOS technology.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	C. Tongchoi, Mitchai Chongcheawchamnan, Apisak Worapishet	Lumped element based Doherty power amplifier topology in CMOS process.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang	A novel hybrid pass logic with static CMOS output drive full-adder cell.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	Antonio Jesús Torralba Silgado, Ramón González Carvajal, Juan Antonio Gómez Galán, Jaime Ramírez-Angulo	A new compact low-power high slew rate class AB CMOS buffer.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	P. Sirinamaratana, N. Wongkomet	A 0.7µm CMOS anti-aliasing filter for non-oversampled video signal applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	F. Hashemi, Khayrollah Hadidi, Abdollah Khoei	Design of a CMOS image sensor with pixel-level ADC in 0.35µm process.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
18	Joon-Jea Sung, Guen-Soon Kang, Suki Kim	A CMOS infrared optical signal processor for remote control.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	Rafik S. Guindi, Farid N. Najm	Design Techniques for Gate-Leakage Reduction in CMOS Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
18	Rajiv V. Joshi, Kaushik Roy 0001	Design of Deep Sub-Micron CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
18	Bedabrata Pain, Bruce Hancock, Thomas Cunningham, Guang Yang 0003, Suresh Seshadri, Julie Heynssens, Chris Wrigley	CMOS Digital Imager Design from a System-on-a-chip Perspective.	VLSI Design	2003	DBLP DOI BibTeX RDF
18	Abhisek Dixit, V. Ramgopal Rao	A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime.	VLSI Design	2003	DBLP DOI BibTeX RDF
18	Geun Rae Cho, Tom Chen 0001	On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment.	VLSI Design	2003	DBLP DOI BibTeX RDF
18	Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne	Transition time modeling in deep submicron CMOS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
18	Ashish Syal, Victor Lee, André Ivanov, Josep Altet	CMOS Differential and Absolute Thermal Sensors.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	differential thermal sensors, absolute thermal sensors, IDDQ, thermal testing
18	Alice Wang, Anantha P. Chandrakasan, Stephen V. Kosonocky	Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits.	ISVLSI	2002	DBLP DOI BibTeX RDF
18	Sandro A. P. Haddad, Wouter A. Serdijn	High-frequency dynamic translinear and log-domain circuits in CMOS technology.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
18	Weidong Guo, Robert J. Huber, Kent F. Smith	A current steering CMOS folding amplifier.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
18	Lige Wang, M. N. El-Gamal	A CMOS companding-based third order Chebyshev filter.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
18	Fernando Silveira, Denis Flandre	A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
18	M. Nakamura, Toshimasa Matsuoka, Kenji Taniguchi 0001	CMOS phase-shift VCO for short-range wireless communication.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
18	Xuguang Zhang, Ezz I. El-Masry	A high-performance, low-voltage, body-driven CMOS current mirror.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
18	Hwang-Cherng Chow, Yung-Kuo Ho	New pixel-shared design and split-path readout of CMOS image sensor circuits.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
18	Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto	CMOS Circuit Technology for Precise GHz Timing Generator.	ITC	2002	DBLP DOI BibTeX RDF
18	Jaume Segura 0001, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins	Parametric Failures in CMOS ICs - A Defect-Based Analysis.	ITC	2002	DBLP DOI BibTeX RDF
18	Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin	Delay and current estimation in a CMOS inverter with an RC load.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
18	Geoffrey D. Duerden, Gordon W. Roberts, M. Jamal Deen	The development of bipolar log domain filters in a standard CMOS process.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
18	Yong-In Park, Soundarapandian Karthikeyan, Frank (Ching-Yuh) Tsay, Eduardo Bartolome	A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
18	Stefan Getzlaff, Jörg Schreiter, Achim Graupner, René Schüffny	A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
18	Alexander Fish, Orly Yadid-Pecht	CMOS current/voltage mode winner-take-all circuit with spatial filtering.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
18	Ashish Syal, Victor Lee, André Ivanov, Josep Altet	CMOS Differential and Absolute Thermal Sensors.	IOLTW	2001	DBLP DOI BibTeX RDF
18	Akira Matsuzawa	High Quality Analog CMOS and Mixed Signal LSI Design.	ISQED	2001	DBLP DOI BibTeX RDF
18	Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder	Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.	ISMVL	2000	DBLP DOI BibTeX RDF	signed-digit adder, negative differential-resistance devices, NDR devices, multiple-valued logic, resonant-tunneling diodes, redundant number systems, RTDs
18	Hyeon Kyeong Seong, Jai Seok Choi, Boo Sik Shin, Heung-Soo Kim	Implementation of Multiple-Valued Multiplier on GF(3m) Using Current Mode CMOS.	ISMVL	2000	DBLP DOI BibTeX RDF
18	Vjekoslav Svilan, Masataka Matsui, James B. Burr	Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS.	ISLPED	2000	DBLP DOI BibTeX RDF
18	Russell E. Henning, Chaitali Chakrabarti	Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design.	VLSI Design	2000	DBLP DOI BibTeX RDF	statistical parameters, high-level synthesis, Low power design, data models, transition activity
18	Jeff Y. F. Hsieh, Teresa H.-Y. Meng	Low-Power Parallel Video Compression Architecture for a Single-Chip Digital CMOS Camera.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
18	Viera Stopjaková, Hans A. R. Manhaeve, M. Sidiropulos	On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC.	DATE	1999	DBLP DOI BibTeX RDF
18	Fred J. Pollack	New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies.	MICRO	1999	DBLP DOI BibTeX RDF
18	Andreas Teuner, Matthias Hillebrand, Bedrich J. Hosticka, S.-B. Park, José Emilio Santos Conde, Nenad Stevanovic	Surveillance Sensor Systems Using CMOS Imagers.	ICIAP	1999	DBLP DOI BibTeX RDF