Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Paolo Roberto Grassi, Mariagiovanna Sami, Ettore Speziale, Michele Tartara |
Analyzing the Sensitivity to Faults of Synchronization Primitives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 349-355, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Noor M. Nayeem, Jacqueline E. Rice |
Online Fault Detection in Reversible Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 426-434, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Seyab Khan, Nor Zaidi Haron, Said Hamdioui, Francky Catthoor |
NBTI Monitoring and Design for Reliability in Nanoscale Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 68-76, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Cristiana Bolchini, Antonio Miele |
An Application-Level Dependability Analysis Framework for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 171-178, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Glenn H. Chapman, Bonnie L. Gray, Vijay K. Jain |
Creating Defect Tolerance in Microfluidic Capacitive/Photonic Biosensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 181-189, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Md. Muwyid U. Khan, Pritish Narayanan, Priyamvada Vijayakumar, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz |
Biased Voting for Improved Yield in Nanoscale Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 79-85, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Masashi Imai, Tomohiro Yoneda |
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 463-471, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Nivesh Rai, Hamidreza Hashempour, Yizi Xing, Bram Kruseman, Said Hamdioui |
A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 139-145, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Javier Carretero, Jaume Abella 0001, Xavier Vera, Pedro Chaparro |
Control-Flow Recovery Validation Using Microarchitectural Invariants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 209-216, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 302-308, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Rudrajit Datta, Nur A. Touba |
Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes - A Graph Theoretic Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 367-373, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jorge Luis Lagos-Benites, Michelangelo Grosso, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini, V. A. Avantaggiati |
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 391-398, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Erik MacLean, Vijay K. Jain |
A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 243-251, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis |
A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 131-138, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Mehran Mozaffari Kermani, Arash Reyhani-Masoleh |
Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 325-331, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch |
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 226-232, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh |
A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 277-285, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Rudrajit Datta, Nur A. Touba |
X-Stacking - A Method for Reducing Control Data for Output Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 332-338, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Hiroshi Kutami, Yusuke Fukushima, Masaru Fukushi, Ikuko Eguchi Yairi, Takeshi Hattori |
Route-Aware Task Mapping Method for Fault-Tolerant 2D-Mesh Network-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 472-480, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Masato Inoue, Haruhiko Kaneko |
Deletion/Insertion/Reversal Error Correcting Codes for Bit-Patterned Media Recording. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 286-293, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Masoud Zamani, Hossein Pedram, Fabrizio Lombardi |
Templated-Based Asynchronous Design for Testable and Fail-Safe Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 146-152, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Shuai Wang |
Characterizing System-Level Vulnerability for Instruction Caches against Soft Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 356-363, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga |
A Soft Error Tolerance Estimation Method for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 268-276, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ahmed Awad, Abdallatif S. Abu-Issa, Said Hamdioui |
Reducing Test Power for Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 112-119, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Vijay K. Jain, Glenn H. Chapman |
Enhanced Defect Tolerance through Matrixed Deployment of Intelligent Sensors for the Smart Power Grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 235-242, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Dan Alexandrescu, Enrico Costenaro, Michael Nicolaidis |
A Practical Approach to Single Event Transients Analysis for Highly Complex Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 155-163, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Daniele Giaffreda, Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra |
Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 252-258, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Daniel B. Limbrick, Suge Yue, William H. Robinson, Bharat L. Bhuva |
Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 103-111, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Geunho Cho, Fabrizio Lombardi |
On the Delay Analysis of Defective CNTFETs with Undeposited CNTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 419-425, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Sreenivas Gangadhar, Spyros Tragoudas |
A Probabilistic Approach to Diagnose SETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 261-267, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Glenn H. Chapman, Jenny Leung, Ana I. L. Namburete, Israel Koren, Zahava Koren |
Predicting Pixel Defect Rates Based on Image Sensor Parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011, pp. 408-416, 2011, IEEE Computer Society, 978-1-4577-1713-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Irith Pomeranz, Sudhakar M. Reddy |
Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 349-357, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kazuteru Namba, Hideo Ito |
Soft Error Tolerant BILBO FF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 73-81, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Marc Hunger, Sybille Hellebrand |
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 101-108, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Salvatore Campagna, Moazzam Hussain, Massimo Violante |
Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 44-51, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz |
Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 24-31, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Cristiana Bolchini, Antonio Miele |
Reliability-Driven System-Level Synthesis of Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 35-43, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Bishnu Prasad Das, Hidetoshi Onodera |
Warning Prediction Sequential for Transient Error Prevention. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 382-390, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Daniele Rossi 0001, Martin Omaña 0001, Cecilia Metra |
Transient Fault and Soft Error On-die Monitoring Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 391-398, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Cristiana Bolchini, Luca Fossati, David Merodio Codinachs, Antonio Miele, Chiara Sandionigi |
A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 191-199, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yoshiyuki Nakamura, Masashi Tanaka |
A Multi-dimensional Iddq Testing Method Using Mahalanobis Distance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 303-309, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Vijay K. Jain, Glenn H. Chapman |
Massively Deployable Intelligent Sensors for the Smart Power Grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 319-327, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yusuke Fukushima, Masaru Fukushi, Ikuko Eguchi Yairi, Takeshi Hattori |
A Hardware-Oriented Fault-Tolerant Routing Algorithm for Irregular 2D-Mesh Network-on-Chip without Virtual Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 52-59, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Nor Zaidi Haron, Said Hamdioui |
High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 144-151, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Nor Azura Zakaria, Edward V. Bautista Jr., Suhaimi Bahisham Jusoh, Weng Fook Lee, Xiaoqing Wen |
Case Studies on Transition Fault Test Generation for At-speed Scan Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 180-188, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Hassan Ebrahimi, Morteza Saheb Zamani, Seyyed Ahmad Razavi |
A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 218-224, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Bijan Ansari, Ingrid Verbauwhede |
A Hybrid Scheme for Concurrent Error Detection of Multiplication over Finite Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 399-407, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen |
Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 331-339, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe |
Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 3, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ming Zhu, Liyi Xiao, Shuhao Li, Yanjing Zhang |
Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 129-135, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Zahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi |
An Analytical Error Model for Pattern Clipping in DNA Self-Assembly. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 7-15, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kensuke Tai, Masato Kitakami |
Prolongation of Lifetime and the Evaluation Method of Dependable SSD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 373-381, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Luca Amati, Cristiana Bolchini, Fabio Salice |
Test Selection Policies for Faster Incremental Fault Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 310-318, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Navaneeth Rameshan, Vijay Laxmi, Manoj Singh Gaur, Mushtaq Ahmed, Krishan Kumar Paliwal |
Minimal Path, Fault Tolerant, QoS Aware Routing with Node and Link Failure in 2-D Mesh NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 60-66, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang |
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 358-366, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Daisaku Seto, Minoru Watanabe |
Recovery Method for a Laser Array Failure on Dynamic Optically Reconfigurable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 411-419, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Geunho Cho, Fabrizio Lombardi, Yong-Bin Kim |
Modelling a CNTFET with Undeposited CNT Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 289-296, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Tatsuya Suto, Kenji Ichijo, Yoshio Yoshioka |
Design and Evaluation of Burst-Mode Asynchronous 8-Bit Microprocessor Using Standard FPGA Development System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 172-179, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Nobuyasu Kanekawa |
Industrial Approach for Dependability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 299, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yasuo Sato |
Circuit Failure Prediction by Field Test - A New Task of Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 69-70, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Pilin Junsangsri, Fabrizio Lombardi |
Time/Temperature Degradation of Solar Cells under the Single Diode Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 240-248, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Takashi Aikyo |
Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 227, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Tomoyuki Nagase, Kenji Ichijo, Akiko Narita, Yoshio Yoshioka |
CFBLT: A Closed Feed Back Loop Type Queuing System; Modeling and Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 109-114, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | NurQamarina MohdNoor, Azilah Saparon, Yusrina Yusof |
Programmable MBIST Merging FSM and Microcode Techniques Using Macro Commands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 115-121, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Eduardo Luis Rhod, Luca Sterpone, Luigi Carro |
A New Soft-Error Resilient Voltage-Mode Quaternary Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 200-208, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kunihito Yamamori, Keisuke Tashiro, Masamichi Kusano, Ikuo Yoshihara |
A Design of Self-Defect-Compensatable Hardware Neuron for Multi-layer Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 82-89, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Payman Zarkesh-Ha, Ali Arabi M. Shahi |
Logic Gate Failure Characterization for Nanoelectronic EDA Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 16-23, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Anant Narayan Hariharan, Salvatore Pontarelli, Marco Ottavi, Fabrizio Lombardi |
Modeling Open Defects in Nanometric Scale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 249-257, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mario Schölzel, Sebastian Müller 0005 |
Combining Hardware- and Software-Based Self-Repair Methods for Statically Scheduled Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 90-98, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang |
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 340-348, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Chun-Lung Hsu, Chen-Wei Lan, Yu-Chih Lo, Yu-Sheng Huang |
Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 136-143, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Dan Zhu, Tun Li, Sikun Li |
An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 209-217, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Martin Omaña 0001, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam 0001, Asifur Rahman |
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 265-272, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kazuteru Namba, Masatoshi Sakata, Hideo Ito |
Single Event Induced Double Node Upset Tolerant Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 280-288, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Noriaki Takagi |
A Study of eSRAM Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 369, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Xiaoqing Wen |
Low-Power Testing for Low-Power Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 261, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz |
Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 273-279, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mahroo Zandrahimi, Alireza Zarei, Hamid R. Zarandi |
A Probabilistic Method to Detect Anomalies in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 152-159, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Min-Ju Chan, Chun-Lung Hsu |
A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 122-128, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Salvatore Pontarelli, Marco Ottavi, Adelio Salsano |
Error Detection and Correction in Content Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 420-428, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Srikanth V. Devarapalli, Payman Zarkesh-Ha, Steven C. Suddarth |
SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 167-171, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Erik MacLean, Vijay K. Jain |
Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 438-446, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | |
25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010 ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![IEEE Computer Society, 978-1-4244-8447-8 The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
1 | Glenn H. Chapman, Jenny Leung, Israel Koren, Zahava Koren |
Tradeoffs in Imager Design with Respect to Pixel Defect Rates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 231-239, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Navid Farazmand, Masoud Zamani, Mehdi Baradaran Tahoori |
Online Multiple Fault Detection in Reversible Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 429-437, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Osnat Keren, Ilya Levin, Mark G. Karpovsky |
Duplication Based One-to-Many Coding for Trojan HW Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010, pp. 160-166, 2010, IEEE Computer Society, 978-1-4244-8447-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Naveed A. Sherwani |
Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 123-123, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Sybille Hellebrand, Marc Hunger |
Are Robust Circuits Really Robust? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 77-77, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Li-C. Wang |
Data Learning Techniques for Functional/System Fmax Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 451-451, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Marcelo Lubaszewski |
Can Functional Test Achieve Low-cost Full Coverage of NoC Faults? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 224-224, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Irith Pomeranz, Sudhakar M. Reddy |
On-chip Generation of the Second Primary Input Vectors of Broadside Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 38-46, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Norman P. Jouppi |
Resilience Challenges for Exascale Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 379-379, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Snehal Udar, Dimitri Kagaris |
Minimizing Observation Points for Fault Location. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 263-267, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Shih-Hsin Hu, Tung-Yeh Wu, Jacob A. Abraham |
SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 136-144, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi |
Errors in DNA Self-Assembly by Synthesized Tile Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 112-120, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | D. M. H. Walker |
Challenges in Delay Testing of Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 81-82, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin |
Reduced Precision Checking for a Floating Point Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 145-152, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis 0001 |
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 254-262, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi |
Optimizing Parametric BIST Using Bio-inspired Computing Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 268-276, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi |
A Novel Hardened Design of a CMOS Memory Cell at 32nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 58-64, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|