Search results for "DSPs"

Found 410 publication records. Showing 410 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Vojin Zivojnovic, Steven W. K. Tjiang, Heinrich Meyr	Compiled Simulation of Programmable DSP Architectures.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
11	Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta	An RTL methodology to enable low overhead combinational testing.	ED&TC	1997	DBLP DOI BibTeX RDF
11	Chouki Aktouf, Ghassan Al Hayek, Chantal Robach	Concurrent testing of VLSI digital signal processors using mutation based testing.	DFT	1997	DBLP DOI BibTeX RDF	VLSI digital signal processor, software technique, hardware device, fault latency, computation, DSP, fault coverage, Mutation testing, digital signal processing chips, concurrent testing
11	Aarti Gupta, Sharad Malik, Pranav Ashar	Toward Formalizing a Validation Methodology Using Simulation Coverage.	DAC	1997	DBLP DOI BibTeX RDF
11	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001	Low power realization of FIR filters using multirate architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips
11	Brian Schoner, John D. Villasenor, Steve Molloy, Rajeev Jain	Techniques for FPGA Implementation of Video Compression Systems.	FPGA	1995	DBLP DOI BibTeX RDF
11	Brian A. Box, John Nieznanski	Common processor element packaging for CHAMP.	FCCM	1995	DBLP DOI BibTeX RDF
11	Ashok Sudarsanam, Sharad Malik	Memory bank and register allocation in software synthesis for ASIPs.	ICCAD	1995	DBLP DOI BibTeX RDF
11	Michael S. Moore, Jim Nichols	Model-based synthesis of a real-time image processing system.	ICECCS	1995	DBLP DOI BibTeX RDF	utility programs, MIRTIS environment, model-based synthesis, real-time image processing system, very high performance implementations, automatic data parallelization, split-and-merge processing model, parallel hardware architecture, C40 DSP network, high level programming interface, running application control, real-time systems, parallel algorithms, image processing, parallel programming, parallel architectures, graphical user interfaces, software tools, programming environments, application program interfaces, merging, model building, program control structures, graphical tools
11	Krste Asanovic, Nelson Morgan, John Wawrzynek	Using simulations of reduced precision arithmetic to design a neuro-microprocessor.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF

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