Search results for "EURO-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Gerald Musgrave (eds.)	Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992	EURO-DAC	1992	DBLP BibTeX RDF
1	Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida	An optimal channel pin assignment with multiple intervals for building block layout.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Masaharu Imai, Jun Sato, Alauddin Alomary, Nobuyuki Hikichi	An integer programming approach to instruction implementation method selection problem.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Donatella Sciuto, Giuseppe Zaza	A multi level testability assistant for VLSI design.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy	SPADES: a simulator for path delay faults in sequential circuits.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	A. J. W. M. ten Berg	Flexible controlpath microarchitecture synthesis based on artificial intelligence.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin	Performance-driven interconnection optimization for microarchitecture synthesis.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Bogdan J. Falkowski, Ingo Schäfer, Marek A. Perkowski	Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functions.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Henning Spruth, Georg Sigl	Parallel algorithms for slicing based final placement.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Shen Lin 0001, Ernest S. Kuh	Transient simulation of lossy coupled transmission lines.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Nagisa Ishiura, Shuzo Yajima	Linear time fault simulation algorithm using a content addressable memory.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Michiel Kraak, Ralph H. J. M. Otten	Tackling cost optimization in testable design by forward inferencing.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	A. Stoll, Jörg Biesenack, Steffen Rumler	Flexible timing specification in a VHDL synthesis subset.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Alex N. D. Zamfirescu, Cary Ussery	VHDL and fuzzy logic if-then rules.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Donald A. Lobo, Barry M. Pangrle	Generating pipelined datapaths using reduction techniques to shorten critical paths.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Soohong Kim, Robert Michael Owens, Mary Jane Irwin	PERFLEX: a performance driven module generator.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	M. T. L. Schaefer, W. U. Klein	Correctness verification of concurrent controller specifications.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Gabriele Umbreit	Providing a VHDL-interface for proof systems.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Udo Mahlstedt, Matthias Heinitz, Jürgen Alt	Test generation for IDDQ testing and leakage fault detection in CMOS circuits.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Peter Windirsch, Hans-Jürgen Herpel, A. Laudenbach, Manfred Glesner	Application-specific microelectronics for mechatronic systems.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Julio Septién, Daniel Mozos, Francisco Tirado, Román Hermida, Milagros Fernández	Heuristics for branch-and-bound global allocation.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Bernd Becker 0001, Rolf Drechsler	A time optimal robust path-delay-fault self-testable adder.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Marc Laurentin, Alain Greiner, Roland Marbot	DESB, a functional abstractor for CMOS VLSI circuits.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Matthias Mutz	Verification of digital circuits based on formal semantics of a hardware description language.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Kei-Yong Khoo, Jason Cong	A fast multilayer general area router for MCM designs.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Robert A. Cottrell, Kevin Nolan, Mark Brown	VHDL analog extensions: process, issues and status.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Daniel C. Liebisch, Adidev Jain	JESSI COMMON FRAMEWORK Design Management: the means to configuration and execution of the design process.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Wolfgang Ecker	Towards a common RT-level subset of VHDL.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Ching Ping Wu, Chung Len Lee 0001, Wen-Zen Shen	SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau	Harmonic scheduling of linear recurrences for digital filter design.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Nadine Azémard, V. Bonzom, Daniel Auvergne	P.SIZE: a sizing aid for optimized designs.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Sundarar Mohan, Pinaki Mazumder	Wolverines: standard cell placement on a network of workstations.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson	An exact analytic technique for simulating uniform RC lines.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Christoph Hübel, Detlev Ruland, Ernst Siepmann	On modeling integrated design environments.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Jacques Rouillard	Analysis of user requirements.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Edgar Bolender, Hans Martin Lipp	The exact solution of timing verification.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Djamel Boussebha, Norbert Giambiasi, Janine Magnier	Temporal verification of behavioral descriptions in VHDL.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Michael Pabst, Tiziano Villa, A. Richard Newton	Experiments on the synthesis and testability of non-scan finite state machines.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer	Minimal area merger of finite state machine controllers.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Frank Buijs	ALU synthesis from HDL descriptions to optimized multi-level logic.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Thomas Pförtner, Stefan Kiefl, Reimund Dachauer	Embedded pin assignment for top down system design.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Wei Wan, Marek A. Perkowski	A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Lars W. Hagen, Fadi J. Kurdahi, Champaka Ramachandran, Andrew B. Kahng	On the intrinsic rent parameter and spectra-based partitioning methodologies.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Rafael Peset Llopis, Hans G. Kerkhoff	A fast and accurate characterization method for full-CMOS circuits.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Mehrdad Nourani, Christos A. Papachristou, Yoshiyasu Takefuji	A neural network based algorithm for the scheduling problem in high-level synthesis.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Paul L. Harper, Ken Scott	Towards a standard VHDL synthesis package.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Haidar Harmanani, Christos A. Papachristou, Scott Chiu, Mehrdad Nourani	SYNTEST: an environment for system-level design for test.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	S. Amadori, P. Coerezza	Design of complex systems with a VHDL based methodology.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Uwe Hunzelmann, Wolfgang Wilkes, Gunter Schlageter	Design of a tool interface for integrated CAD-environments.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Juan Carlos López 0001, Margarida F. Jacome, Stephen W. Director	Design assistance for CAD frameworks.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	David B. Bernstein, Rodney Farrow, David Charness	Challenges in the analysis of VHDL.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Sridhar Narayanan, Charles Njinda, Rajesh Gupta 0003, Melvin A. Breuer	SIESTA: a multi-facet scan design system.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Norbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner	High-level synthesis in a rapid-prototype environment for mechatronic systems.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Andrew Guyler	VHDL 1076-1992 languages changes.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Christel Oczko, Michael W. Nitsche	Multi-kernel simulation description within VHDL.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Didier Crestani, A. Aguila, M.-H. Gentil, P. Chardon, Christian Durante	Automatic partitioning for deterministic test.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Wolfgang Ecker, Sabine März	Subtype concept of VHDL for synthesis constraints.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Hugo De Man	Design technology research for the nineties: more of the same?	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Alain Debreil, Philippe Oddo	Synchronous design in VHDL.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich	Design verification considering manufacturing tolerances by using worst-caste distances.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	O. Pulkkinen, Klaus Kronlöf	Integration of SDL and VHDL for high-level digital design.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Loganath Ramachandran, Frank Vahid, Sanjiv Narayan, Daniel D. Gajski	Semantics and synthesis of signals in behavioral VHDL.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Wolf-Dieter Tiedemann	An approach to multi-paradigm controller synthesis from timing diagram specifications.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Sy-Yen Kuo	Locating logic design errors via test generation and don't-care propagation.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Sanjiv Narayan, Daniel D. Gajski	System clock estimation based on clock slack minimization.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	B. Lutter, Wolfgang Glunz, Franz-Josef Rammig	Using VHDL for simulation of SDL specifications.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Gerhard Scholz, Wolfgang Wilkes	Information modelling of folded and unfolded design.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Jens Lienig, Krishnaiyan Thulasiraman, M. N. S. Swamy	Routing algorithms for multi-chip modules.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Mark Brown	VHDL intermediate form standardization: process, issues and status.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Farhad Aghadasi	Asynchronous state machine synthesis using data driven clocks.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Klaus D. Müller-Glaser, Jürgen Bortolazzi, Yankin Tanurhan	Towards a requirements definition, specification and system design environment.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Champaka Ramachandran, Fadi J. Kurdahi	Combined topological and functionality based delay estimation using a layout-driven approach for high level applications.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Hideo Tamamoto, Hiroshi Yokoyama, Yuichi Narita	Random current testing for CMOS logic circuits by monitoring a dynamic power supply current.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Bernd Becker 0001, Paul Molitor	A performance driven generator for efficient testable conditional-sum-adders.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Eric Felt, Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli	An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Tadeusz Luba, K. Górski, Leszek B. Wronski	ROM-based finite state machines with PLA address modifiers.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Adam Pawlak	Selected aspects of component modeling.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Kuang-Chien Chen, Jason Cong	Maximal reduction of lookup-table based FPGAs.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	C.-J. Richard Shi, Janusz A. Brzozowski	Efficient constrained encoding for VLSI sequential logic synthesis.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Weiwei Mao, Michael D. Ciletti	A quantitative measure of robustness for delay fault testing.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Min Huang, M. A. Styblinski	A generic software system for drift reliability optimization of VLSI circuits.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Ayman I. Kayssi, Karem A. Sakallah	Delay macromodels for the timing analysis of GaAs DCFL.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Clay S. Gloster Jr., Franc Brglez	Cellular scan test generation for sequential circuits.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Arno Kunzmann	Generation of deterministic test patterns by minimal basic test sets.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Bernd Becker 0001, Ralf Hahn, Rolf Krieger	Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth	DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Stephen E. Lim, David C. Hendry, Ping F. Yeung	Experiences and issues in VHDL-based synthesis.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Michael Jacobsen, Wolfgang Nebel	VHDL for high speed desktop video ICs: experience with replacement of other simulator.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Christian Berthet, Jérôme Rampon, L. Sponga	Synthesis of VHDL arrays on RAM cells.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Hamid Savoj, Mário J. Silva, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Boolean matching in logic synthesis.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Uwe Gläser, Heinrich Theodor Vierhaus	MILEF: an efficient approach to mixed level automatic test pattern generation.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Henrik Esbensen	A genetic algorithm for macro cell placement.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Sungho Kang, Stephen A. Szygenda	New design error modeling and metrics for design validation.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Marius Minea	Compiling VHDL into a high-level synthesis design representation.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Maria Brielmann, Elisabeth Kupitz	Representing the hardware design process by a common data schema.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Ronald B. Stewart, Véronique Anjubault, Philippe Garcin, Jacques Benkoski	Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulation.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Leszek J. Opalski, M. A. Styblinski	GOSSIP: a generic system for statistical circuit design.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Cross-fertilizing FSM verification techniques and sequential diagnosis.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Deborah C. Wang, C. Bernard Shung	Crossing distribution.	EURO-DAC	1992	DBLP DOI BibTeX RDF
1	Nand Kumar, Ranga Vemuri	Finite state machine verification on MIMD machines.	EURO-DAC	1992	DBLP DOI BibTeX RDF

Publications at "EURO-DAC"( http://dblp.L3S.de/Venues/EURO-DAC )