Search results for "FCCM"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima	CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing.	FCCM	2017	DBLP DOI BibTeX RDF
1	Reza Nakhjavani, Jianwen Zhu	A Case for Common-Case: On FPGA Acceleration of Erasure Coding.	FCCM	2017	DBLP DOI BibTeX RDF
1	Andrew G. Schmidt, Gabriel Weisz, Matthew French	Evaluating Rapid Application Development with Python for Heterogeneous Processor-Based FPGAs.	FCCM	2017	DBLP DOI BibTeX RDF
1	Emmanouil Kousanakis, Apostolos Dollas, Euripides Sotiriades, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Athanasia Papoutsi, Panagiotis C. Petrantonakis, Panayiota Poirazi, Spyridon Chavlis, George Kastellakis	An Architecture for the Acceleration of a Hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based Processor.	FCCM	2017	DBLP DOI BibTeX RDF
1	Nachiket Kapre	Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory Cascades.	FCCM	2017	DBLP DOI BibTeX RDF
1	Sicheng Li, Wei Wen, Yu Wang 0002, Song Han 0003, Yiran Chen 0001, Hai Li 0001	An FPGA Design Framework for CNN Sparsification and Acceleration.	FCCM	2017	DBLP DOI BibTeX RDF
1	Chin Hau Hoo, Akash Kumar 0001	ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding.	FCCM	2017	DBLP DOI BibTeX RDF
1	Le Tu, Yuelai Yuan, Kan Huang, Xiaoqiang Zhang, Zixin Wang, Dihu Chen	Improved Synthesis of Compressor Trees on FPGAs in High-Level Synthesis.	FCCM	2017	DBLP DOI BibTeX RDF
1	Yohann Uguen, Florent de Dinechin, Steven Derrien	A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators.	FCCM	2017	DBLP DOI BibTeX RDF
1	Mohammad Samragh, Mohammad Ghasemzadeh 0002, Farinaz Koushanfar	Customizing Neural Networks for Efficient FPGA Implementation.	FCCM	2017	DBLP DOI BibTeX RDF
1	Lana Josipovic, Philip Brisk, Paolo Ienne	An Out-of-Order Load-Store Queue for Spatial Computing.	FCCM	2017	DBLP DOI BibTeX RDF
1	Philip Colangelo, Randy Huang, Enno Lübbers, Martin Margala, Kevin Nealis	Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA.	FCCM	2017	DBLP DOI BibTeX RDF
1	Sang Woo Jun, Shuotao Xu, Arvind	Terabyte Sort on FPGA-Accelerated Flash Storage.	FCCM	2017	DBLP DOI BibTeX RDF
1	Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet	A Configurable FPGA Implementation of the Tanh Function Using DCT Interpolation.	FCCM	2017	DBLP DOI BibTeX RDF
1	Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao 0001, Russell Tessier	Scalable Network Function Virtualization for Heterogeneous Middleboxes.	FCCM	2017	DBLP DOI BibTeX RDF
1	Nachiket Kapre	On Bit-Serial NoCs for FPGAs.	FCCM	2017	DBLP DOI BibTeX RDF
1	Nachiket Kapre, Siddhartha 0001	Communication Optimization for the 16-Core Epiphany Floating-Point Processor Array.	FCCM	2016	DBLP DOI BibTeX RDF
1	Stylianos I. Venieris, Christos-Savvas Bouganis	fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs.	FCCM	2016	DBLP DOI BibTeX RDF
1	Zhiyuan Yang 0001, Caleb Serafy, Ankur Srivastava 0001	ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling.	FCCM	2016	DBLP DOI BibTeX RDF
1	Henry Wong, Vaughn Betz, Jonathan Rose	High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors.	FCCM	2016	DBLP DOI BibTeX RDF
1	Tianqi Wang, Xi Jin 0002, Bo Peng, Chuanjun Wang, Linlin Zheng	RP-Ring: A Heterogeneous Multi-FPGA Accelerating Solution for N-Body Simulations.	FCCM	2016	DBLP DOI BibTeX RDF
1	Chuyu Shen, Zili Lin, Ping Fan, Xianglong Meng, Weikang Qian	Parallelizing FPGA Technology Mapping through Partitioning.	FCCM	2016	DBLP DOI BibTeX RDF
1	Shijie Zhou 0001, Charalampos Chelmis, Viktor K. Prasanna	High-Throughput and Energy-Efficient Graph Processing on FPGA.	FCCM	2016	DBLP DOI BibTeX RDF
1	Bajaj Ronak, Suhaib A. Fahmy	Initiation Interval Aware Resource Sharing for FPGA DSP Blocks.	FCCM	2016	DBLP DOI BibTeX RDF
1	Ahmed Sanaullah, Arash Khoshparvar, Martin C. Herbordt	FPGA-Accelerated Particle-Grid Mapping.	FCCM	2016	DBLP DOI BibTeX RDF
1	Seyyed Mahdi Najmabadi, Zhe Wang 0008, Yousef Baroud, Sven Simon 0001	Online Bandwidth Reduction Using Dynamic Partial Reconfiguration.	FCCM	2016	DBLP DOI BibTeX RDF
1	Dustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, Ryan Kastner	Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler.	FCCM	2016	DBLP DOI BibTeX RDF
1	Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo, Cody Hao Yu	The SMEM Seeding Acceleration for DNA Sequence Alignment.	FCCM	2016	DBLP DOI BibTeX RDF
1	Que Yanghua, Nachiket Kapre, Harnhua Ng, Kirvy Teo	Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing Closure.	FCCM	2016	DBLP DOI BibTeX RDF
1	Tao Li, Qiang Liu 0011	Cost Effective Partial Scan for Hardware Emulation.	FCCM	2016	DBLP DOI BibTeX RDF
1	Zsolt István, David Sidler, Gustavo Alonso	Runtime Parameterizable Regular Expression Operators for Databases.	FCCM	2016	DBLP DOI BibTeX RDF
1	Amine Ait Si Ali, Abbes Amira, Faycal Bensaali, Mohieddine Benammar, Muhammad Hassan, Amine Bermak	High Level Synthesis Based E-Nose System for Gas Applications.	FCCM	2016	DBLP DOI BibTeX RDF
1	Junyi Liu, John Wickerson, George A. Constantinides	Loop Splitting for Efficient Pipelining in High-Level Synthesis.	FCCM	2016	DBLP DOI BibTeX RDF
1	Jiang Su, David B. Thomas, Peter Y. K. Cheung	Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout.	FCCM	2016	DBLP DOI BibTeX RDF
1	Jordan A. Bradshaw, Rasha Karakchi, Jason D. Bakos	Two-Hit Filter Synthesis for Genomic Database Search.	FCCM	2016	DBLP DOI BibTeX RDF
1	Tanja Harbaum, Mahmoud Seboui, Matthias Norbert Balzer, Jürgen Becker 0001, Marc Weber	A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment.	FCCM	2016	DBLP DOI BibTeX RDF
1	Dana L. How, Sean Atsatt	Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGA.	FCCM	2016	DBLP DOI BibTeX RDF
1	Nachiket Kapre	Marathon: Statically-Scheduled Conflict-Free Routing on FPGA Overlay NoCs.	FCCM	2016	DBLP DOI BibTeX RDF
1	Gowthami Jayashri Manikandan, Sitao Huang, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen	Acceleration of the Pair-HMM Algorithm for DNA Variant Calling.	FCCM	2016	DBLP DOI BibTeX RDF
1	Peipei Zhou 0001, Hyunseok Park, Zhenman Fang, Jason Cong, André DeHon	Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication.	FCCM	2016	DBLP DOI BibTeX RDF
1	Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon	Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP).	FCCM	2016	DBLP DOI BibTeX RDF
1	Nina Engelhardt, Hayden Kwok-Hay So	Vertex-Centric Graph Processing on FPGA.	FCCM	2016	DBLP DOI BibTeX RDF
1	Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich	A LUT-Based Approximate Adder.	FCCM	2016	DBLP DOI BibTeX RDF
1	Ameer M. S. Abdelhadi, Guy G. F. Lemieux	A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs.	FCCM	2016	DBLP DOI BibTeX RDF
1	Kohei Nagasu, Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav G. Sedukhin	Parallelism for High-Performance Tsunami Simulation with FPGA: Spatial or Temporal?	FCCM	2016	DBLP DOI BibTeX RDF
1	Eddie Hung, James J. Davis 0001, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides	KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs.	FCCM	2016	DBLP DOI BibTeX RDF
1	Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi, Marco Lattuada 0001	A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries.	FCCM	2016	DBLP DOI BibTeX RDF
1	Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei 0001, Peng Wei 0004	When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration.	FCCM	2016	DBLP DOI BibTeX RDF
1	Dajung Lee, Roger Moussalli, Sameh W. Asaad, Mudhakar Srivatsa	Spatial Predicates Evaluation in the Geohash Domain Using Reconfigurable Hardware.	FCCM	2016	DBLP DOI BibTeX RDF
1	Konstantinos Krommydas, Ahmed E. Helal, Anshuman Verma, Wu-chun Feng	Bridging the Performance-Programmability Gap for FPGAs via OpenCL: A Case Study with OpenDwarfs.	FCCM	2016	DBLP DOI BibTeX RDF
1	Farheen Fatima Khan, Andy Ye	An Empirical Analysis of the Fidelity of VPR Area Models.	FCCM	2016	DBLP DOI BibTeX RDF
1	Adam Page, Tinoosh Mohsenin	FPGA-Based Reduction Techniques for Efficient Deep Neural Network Deployment.	FCCM	2016	DBLP DOI BibTeX RDF
1	Thaddeus Koehn, Peter M. Athanas	Finding Space-Time Stream Permutations for Minimum Memory and Latency.	FCCM	2016	DBLP DOI BibTeX RDF
1	Amine Ait Si Ali, Xiaojun Zhai, Abbes Amira, Faycal Bensaali, Naeem Ramzan	Heterogeneous Implementation of ECG Encryption and Identification on the Zynq SoC.	FCCM	2016	DBLP DOI BibTeX RDF
1	Ren Chen, Viktor K. Prasanna	Accelerating Equi-Join on a CPU-FPGA Heterogeneous Platform.	FCCM	2016	DBLP DOI BibTeX RDF
1	Wei Song 0002, Dirk Koch, Mikel Luján, Jim D. Garside	Parallel Hardware Merge Sorter.	FCCM	2016	DBLP DOI BibTeX RDF
1	Gopalakrishna Hegde, Siddhartha 0001, Nachiappan Ramasamy, Vamsi Buddha, Nachiket Kapre	Evaluating Embedded FPGA Accelerators for Deep Learning Applications.	FCCM	2016	DBLP DOI BibTeX RDF
1	Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow	AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS.	FCCM	2016	DBLP DOI BibTeX RDF
1	Jan Gray	GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator.	FCCM	2016	DBLP DOI BibTeX RDF
1	William Diehl, Kris Gaj	High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two.	FCCM	2016	DBLP DOI BibTeX RDF
1	Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Zhuoran Zhao, Tong Wu 0007, Ediz Cetin, Oliver Diessel, Lingkan Gong	Reconfiguration Control Networks for TMR Systems with Module-Based Recovery.	FCCM	2016	DBLP DOI BibTeX RDF
1	Pavel Benácek, Viktor Pus, Hana Kubátová	P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers.	FCCM	2016	DBLP DOI BibTeX RDF
1	Zeping Xue, David B. Thomas	SynADT: Dynamic Data Structures in High Level Synthesis.	FCCM	2016	DBLP DOI BibTeX RDF
1	Ernst Joachim Houtgast, Vlad Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars	Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms.	FCCM	2016	DBLP DOI BibTeX RDF
1	Jiayi Sheng, Qingqing Xiong, Chen Yang 0010, Martin C. Herbordt	Application-Aware Collective Communication (Extended Abstract).	FCCM	2016	DBLP DOI BibTeX RDF
1	Maciej Kurek, Marc Peter Deisenroth, Wayne Luk, Timothy John Todman	Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs.	FCCM	2016	DBLP DOI BibTeX RDF
1	Ehsan Ghasemi, Paul Chow	Accelerating Apache Spark Big Data Analysis with FPGAs.	FCCM	2016	DBLP DOI BibTeX RDF
1	Amey M. Kulkarni, Ali Jafari, Colin Shea, Tinoosh Mohsenin	CS-Based Secured Big Data Processing on FPGA.	FCCM	2016	DBLP DOI BibTeX RDF
1		24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, Washington, DC, USA, May 1-3, 2016	FCCM	2016	DBLP BibTeX RDF
1	Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy	DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect.	FCCM	2016	DBLP DOI BibTeX RDF
1	Farheen Fatima Khan, Andy Ye	Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area.	FCCM	2015	DBLP DOI BibTeX RDF
1	Nachiket Kapre, Bibin Chandrashekaran, Harnhua Ng, Kirvy Teo	Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing.	FCCM	2015	DBLP DOI BibTeX RDF
1	Yuliang Pu, Jun Peng, Letian Huang, John Chen	An Efficient KNN Algorithm Implemented on FPGA Based Heterogeneous Computing System Using OpenCL.	FCCM	2015	DBLP DOI BibTeX RDF
1	Yun Rock Qu, Viktor K. Prasanna	Enabling High Throughput and Virtualization for Traffic Classification on FPGA.	FCCM	2015	DBLP DOI BibTeX RDF
1	Nathan A. Harward, Michael R. Gardiner, Luke W. Hsiao, Michael J. Wirthlin	Estimating Soft Processor Soft Error Sensitivity through Fault Injection.	FCCM	2015	DBLP DOI BibTeX RDF
1	Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra	Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions.	FCCM	2015	DBLP DOI BibTeX RDF
1	James Coole, Greg Stitt	Adjustable-Cost Overlays for Runtime Compilation.	FCCM	2015	DBLP DOI BibTeX RDF
1	Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser	Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System.	FCCM	2015	DBLP DOI BibTeX RDF
1	Junyi Liu, Samuel Bayliss, George A. Constantinides	Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS.	FCCM	2015	DBLP DOI BibTeX RDF
1	Jeffrey B. Goeders, Steven J. E. Wilton	Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Francis P. Russell, Peter D. Düben, Xinyu Niu, Wayne Luk, Tim N. Palmer	Architectures and Precision Analysis for Modelling Atmospheric Variables with Chaotic Behaviour.	FCCM	2015	DBLP DOI BibTeX RDF
1	Michael Xi Yue, Dirk Koch, Guy G. F. Lemieux	Rapid Overlay Builder for Xilinx FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Jens Korinth, David de la Chevallerie, Andreas Koch 0001	An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures.	FCCM	2015	DBLP DOI BibTeX RDF
1	Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono	Virtual Channel and Switch Allocation for Low Latency Network-on-Chip Routers.	FCCM	2015	DBLP DOI BibTeX RDF
1	Matthias Göbel 0001, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink	High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis.	FCCM	2015	DBLP DOI BibTeX RDF
1	Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján	Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.	FCCM	2015	DBLP DOI BibTeX RDF
1	João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes	Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders.	FCCM	2015	DBLP DOI BibTeX RDF
1	Bangtian Liu, Haohuan Fu, Lin Gan, Wenlai Zhao, Guangwen Yang	Optimizing Residue Number Reverse Converters through Bitwise Arithmetic on FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Katayoun Neshatpour, Maria Malik, Mohammad Ali Ghodrat, Houman Homayoun	Accelerating Big Data Analytics Using FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Sicheng Li, Chunpeng Wu, Hai Li 0001, Boxun Li, Yu Wang 0002, Qinru Qiu	FPGA Acceleration of Recurrent Neural Network Based Language Model.	FCCM	2015	DBLP DOI BibTeX RDF
1	Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi	Function Proxies for Improved Resource Sharing in High Level Synthesis.	FCCM	2015	DBLP DOI BibTeX RDF
1	Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell	Efficient Overlay Architecture Based on DSP Blocks.	FCCM	2015	DBLP DOI BibTeX RDF
1	Gopalakrishna Hegde, Nachiket Kapre	Energy-Efficient Acceleration of OpenCV Saliency Computation Using Soft Vector Processors.	FCCM	2015	DBLP DOI BibTeX RDF
1	Aaron Landy, Greg Stitt	Revisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Nachiket Kapre	Sparse Graph Processing with Soft-Processors.	FCCM	2015	DBLP DOI BibTeX RDF
1	David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees A. Vissers, Raymond Carley	Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware.	FCCM	2015	DBLP DOI BibTeX RDF
1	Pradeep Moorthy, Nachiket Kapre	Zedwulf: Power-Performance Tradeoffs of a 32-Node Zynq SoC Cluster.	FCCM	2015	DBLP DOI BibTeX RDF
1	Ameer M. S. Abdelhadi, Guy G. F. Lemieux	Modular SRAM-Based Binary Content-Addressable Memories.	FCCM	2015	DBLP DOI BibTeX RDF
1	Hongyuan Ding, Miaoqing Huang	Performance and Energy Optimization on MPSoCs by Enabling STT-MRAM LUTs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Christopher W. Fletcher, Ling Ren 0001, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios N. Serpanos, Srinivas Devadas	A Low-Latency, Low-Area Hardware Oblivious RAM Controller.	FCCM	2015	DBLP DOI BibTeX RDF

Publications at "FCCM"( http://dblp.L3S.de/Venues/FCCM )