Search results for "FPL"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Di Wu, Jin Chen, Wei Cao 0002, Lingli Wang	A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration Architecture.	FPL	2018	DBLP DOI BibTeX RDF
1	Anuj Vaishnav, Khoa Dang Pham, Dirk Koch	A Survey on FPGA Virtualization.	FPL	2018	DBLP DOI BibTeX RDF
1	Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, Nandeesha Veeranna	CIDPro: Custom Instructions for Dynamic Program Diversification.	FPL	2018	DBLP DOI BibTeX RDF
1	François Serre, Markus Püschel	A DSL-Based FFT Hardware Generator in Scala.	FPL	2018	DBLP DOI BibTeX RDF
1	Shenghsun Cho, Michael Ferdman, Peter A. Milder	FPGASwarm: High Throughput Model Checking on FPGAs.	FPL	2018	DBLP DOI BibTeX RDF
1	Athanasios Stratikopoulos, Christos Kotselidis, John Goodacre, Mikel Luján	FastPath: Towards Wire-Speed NVMe SSDs.	FPL	2018	DBLP DOI BibTeX RDF
1	Debdeep Mukhopadhyay, Debapriya Basu Roy	Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECC Application in GF(p).	FPL	2018	DBLP DOI BibTeX RDF
1	Marie Nguyen, James C. Hoe	Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration.	FPL	2018	DBLP DOI BibTeX RDF
1	Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu	DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.	FPL	2018	DBLP DOI BibTeX RDF
1	Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Oliver Sinnen, Andreas Koch 0001	Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis.	FPL	2018	DBLP DOI BibTeX RDF
1	Alex Rodionov, Jonathan Rose	Automatic Topology Optimization for FPGA Interconnect Synthesis.	FPL	2018	DBLP DOI BibTeX RDF
1	Junsong Wang, Qiuwen Lou, Xiaofan Zhang 0001, Chao Zhu, Yonghua Lin, Deming Chen	Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA.	FPL	2018	DBLP DOI BibTeX RDF
1	Philippos Papaphilippou, Wayne Luk	Accelerating Database Systems Using FPGAs: A Survey.	FPL	2018	DBLP DOI BibTeX RDF
1	Muhsen Owaida, Gustavo Alonso	Application Partitioning on FPGA Clusters: Inference over Decision Tree Ensembles.	FPL	2018	DBLP DOI BibTeX RDF
1		28th International Conference on Field Programmable Logic and Applications, FPL 2018, Dublin, Ireland, August 27-31, 2018	FPL	2018	DBLP BibTeX RDF
1	Habib ul Hasan Khan, Diana Göhringer	Cycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs Using Artificial Intelligence.	FPL	2018	DBLP DOI BibTeX RDF
1	Jiandong Mu, Wei Zhang 0012, Hao Liang 0003, Sharad Sinha	A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization.	FPL	2018	DBLP DOI BibTeX RDF
1	Zhenhao He, David Sidler, Zsolt István, Gustavo Alonso	A Flexible K-Means Operator for Hybrid Databases.	FPL	2018	DBLP DOI BibTeX RDF
1	Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek	Accelerated Wire-Speed Packet Capture at 200 Gbps.	FPL	2018	DBLP DOI BibTeX RDF
1	Luís Fiolhais, Horácio C. Neto	An Efficient Exact Fused Dot Product Processor in FPGA.	FPL	2018	DBLP DOI BibTeX RDF
1	Nikolaos Alachiotis 0001, Charalampos Vatsolakis, Grigorios Chrysos 0001, Dionisios N. Pnevmatikatos	Accelerated Inference of Positive Selection on Whole Genomes.	FPL	2018	DBLP DOI BibTeX RDF
1	Yongming Shen 0001, Tianchu Ji, Michael Ferdman, Peter A. Milder	Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces.	FPL	2018	DBLP DOI BibTeX RDF
1	Nina Engelhardt, C.-H. Dominic Hung, Hayden Kwok-Hay So	Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems.	FPL	2018	DBLP DOI BibTeX RDF
1	Michael Barrow, Steven M. Burns, Ryan Kastner	A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation.	FPL	2018	DBLP DOI BibTeX RDF
1	Bogdan Pasca 0001, Martin Langhammer	Activation Function Architectures for FPGAs.	FPL	2018	DBLP DOI BibTeX RDF
1	Declan Byrne, Ronan Farrell, Sidath Madhuwantha, Miriam Leeser, John Dooley	Digital Pre-distortion Implemented Using FPGA.	FPL	2018	DBLP DOI BibTeX RDF
1	Tyrone Sherwin, Kevin I-Kai Wang, Prabu Thiagaraj, Oliver Sinnen	Median Filtering with Very Large Windows: SKA Algorithms for FPGAs.	FPL	2018	DBLP DOI BibTeX RDF
1	Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk, Xinyu Niu	Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA.	FPL	2018	DBLP DOI BibTeX RDF
1	Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei 0004, Tianhe Yu	SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing.	FPL	2018	DBLP DOI BibTeX RDF
1	Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt	Hierarchical Force-Based Block Spreading for Analytical FPGA Placement.	FPL	2018	DBLP DOI BibTeX RDF
1	Lake Bu, Michel A. Kinsy	Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions.	FPL	2018	DBLP DOI BibTeX RDF
1	Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, André DeHon	Case for Fast FPGA Compilation Using Partial Reconfiguration.	FPL	2018	DBLP DOI BibTeX RDF
1	Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf	FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet.	FPL	2018	DBLP DOI BibTeX RDF
1	Yaman Umuroglu, Lahiru Rasnayake, Magnus Själander	BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing.	FPL	2018	DBLP DOI BibTeX RDF
1	Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis	Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems.	FPL	2018	DBLP DOI BibTeX RDF
1	Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk	Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model.	FPL	2018	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato	A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2).	FPL	2018	DBLP DOI BibTeX RDF
1	Ahmet Can Mert, Hasan Azgin, Ercan Kalali, Ilker Hamzaoglu	Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA.	FPL	2018	DBLP DOI BibTeX RDF
1	Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto	Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs.	FPL	2018	DBLP DOI BibTeX RDF
1	Alexandros Kouris, Stylianos I. Venieris, Christos-Savvas Bouganis	Cascade^CNN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks.	FPL	2018	DBLP DOI BibTeX RDF
1	Mustafa Abbas, Vaughn Betz	Latency Insensitive Design Styles for FPGAs.	FPL	2018	DBLP DOI BibTeX RDF
1	Simone Casale Brunet, Thierry Schüpbach, Nicolas Guex, Christian Iseli, Alan J. Bridge, Dmitry Kuznetsov, Christian J. A. Sigrist, Phillippe Lemercier, Ioannis Xenarios, Endri Bezati	Towards in the Field Fast Pathogens Detection Using FPGAs.	FPL	2018	DBLP DOI BibTeX RDF
1	Behzad Salami 0001, Osman S. Ünsal, Adrián Cristal	A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs.	FPL	2018	DBLP DOI BibTeX RDF
1	Mihailo Isakov, Alan Ehret, Michel A. Kinsy	ClosNets: Batchless DNN Training with On-Chip a Priori Sparse Neural Topologies.	FPL	2018	DBLP DOI BibTeX RDF
1	Robert Hale, Brad L. Hutchings	Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs.	FPL	2018	DBLP DOI BibTeX RDF
1	Jiayi Sheng, Chen Yang 0010, Martin C. Herbordt	High Performance Communication on Reconfigurable Clusters.	FPL	2018	DBLP DOI BibTeX RDF
1	Charles Lo, Paul Chow	Multi-fidelity Optimization for High-Level Synthesis Directives.	FPL	2018	DBLP DOI BibTeX RDF
1	Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton	An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug.	FPL	2018	DBLP DOI BibTeX RDF
1	Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones	A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors.	FPL	2018	DBLP DOI BibTeX RDF
1	João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias	K-means clustering on CGRA.	FPL	2017	DBLP DOI BibTeX RDF
1	Simon Joel Schmidt, David Boland	Dynamic bitwidth assignment for efficient dot products.	FPL	2017	DBLP DOI BibTeX RDF
1	Nikolaos Alachiotis 0001, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos	Versatile deployment of FPGA accelerators in disaggregated data centers: A bioinformatics case study.	FPL	2017	DBLP DOI BibTeX RDF
1	William Diehl, Farnoud Farahmand, Panasayya Yalla, Jens-Peter Kaps, Kris Gaj	Comparison of hardware and software implementations of selected lightweight block ciphers.	FPL	2017	DBLP DOI BibTeX RDF
1	Kizheppatt Vipin, Jan Gray, Nachiket Kapre	Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs.	FPL	2017	DBLP DOI BibTeX RDF
1	Stelios Mavridis, Emmanouil Pavlidakis, Ioannis Stamoulias, Christos Kozanitis, Nikolaos Chrysos, Christoforos Kachris, Dimitrios Soudris, Angelos Bilas	VineTalk: Simplifying software access and sharing of FPGAs in datacenters.	FPL	2017	DBLP DOI BibTeX RDF
1	Benedikt Janßen, Pascal Zimprich, Michael Hübner 0001	A dynamic partial reconfigurable overlay concept for PYNQ.	FPL	2017	DBLP DOI BibTeX RDF
1	Brad L. Hutchings, Michael J. Wirthlin	Rapid implementation of a partially reconfigurable video system with PYNQ.	FPL	2017	DBLP DOI BibTeX RDF
1	Ephrem Wu, Xiaoqian Zhang, David Berman, Inkeun Cho	A high-throughput reconfigurable processing array for neural networks.	FPL	2017	DBLP DOI BibTeX RDF
1	Brice Colombier, Ugo Mureddu, Marek Laban, Oto Petura, Lilian Bossuet, Viktor Fischer	Complete activation scheme for FPGA-oriented IP cores design protection.	FPL	2017	DBLP DOI BibTeX RDF
1	Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano	Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA.	FPL	2017	DBLP DOI BibTeX RDF
1	Grace Zgheib, Paolo Ienne	Evaluating FPGA clusters under wide ranges of design parameters.	FPL	2017	DBLP DOI BibTeX RDF
1	Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton	Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques.	FPL	2017	DBLP DOI BibTeX RDF
1	Adewale Adetomi, Godwin Enemali, Tughrul Arslan	Relocation-aware communication network for circuits on Xilinx FPGAs.	FPL	2017	DBLP DOI BibTeX RDF
1	Henry Block, Tsutomu Maruyama	An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimization.	FPL	2017	DBLP DOI BibTeX RDF
1	Ryan A. Cooke, Suhaib A. Fahmy	In-network online data analytics with FPGAs.	FPL	2017	DBLP DOI BibTeX RDF
1	Conghui He, Haohuan Fu, Wayne Luk, Weijia Li, Guangen Yang	Exploring the potential of reconfigurable platforms for order book update.	FPL	2017	DBLP DOI BibTeX RDF
1	Pedro Maat C. Massolino, Lejla Batina, Ricardo Chaves, Nele Mentens	Area-optimized montgomery multiplication on IGLOO 2 FPGAs.	FPL	2017	DBLP DOI BibTeX RDF
1	Ryouhei Maeda, Tsutomu Maruyama	An implementation method of poisson image editing on FPGA.	FPL	2017	DBLP DOI BibTeX RDF
1	Yingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci Memik, Gokhan Memik, Hal Finkel, Franck Cappello	Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench.	FPL	2017	DBLP DOI BibTeX RDF
1	Lester Kalms, Diana Göhringer	Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs.	FPL	2017	DBLP DOI BibTeX RDF
1	Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka	Evaluating high-level design strategies on FPGAs for high-performance computing.	FPL	2017	DBLP DOI BibTeX RDF
1	Ted Xie, Vinh Dang, Jack Wadden, Kevin Skadron, Mircea Stan	REAPR: Reconfigurable engine for automata processing.	FPL	2017	DBLP DOI BibTeX RDF
1	Subho S. Banerjee, Mohamed El-Hadedy 0001, Ching Y. Tan, Zbigniew T. Kalbarczyk, Steven S. Lumetta, Ravishankar K. Iyer	On accelerating pair-HMM computations in programmable hardware.	FPL	2017	DBLP DOI BibTeX RDF
1	Jinnan Ding, Shuguo Li	Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition.	FPL	2017	DBLP DOI BibTeX RDF
1	Lingkan Gong, Alexander Kroh, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel	Reliable SEU monitoring and recovery using a programmable configuration controller.	FPL	2017	DBLP DOI BibTeX RDF
1	Tobias Kenter, Jens Förstner, Christian Plessl	Flexible FPGA design for FDTD using OpenCL.	FPL	2017	DBLP DOI BibTeX RDF
1	Yifeng Mo, Shuguo Li	Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs.	FPL	2017	DBLP DOI BibTeX RDF
1	Lijuan Li 0002, Shuguo Li	High throughput AES encryption/decryption with efficient reordering and merging techniques.	FPL	2017	DBLP DOI BibTeX RDF
1	Konstantinos Boikos, Christos-Savvas Bouganis	A high-performance system-on-chip architecture for direct tracking for SLAM.	FPL	2017	DBLP DOI BibTeX RDF
1	Stephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Payá Vayá	Application-specific soft-core vector processor for advanced driver assistance systems.	FPL	2017	DBLP DOI BibTeX RDF
1	Sadegh Yazdanshenas, Vaughn Betz	Quantifying and mitigating the costs of FPGA virtualization.	FPL	2017	DBLP DOI BibTeX RDF
1	Oron Port, Yoav Etsion	DFiant: A dataflow hardware description language.	FPL	2017	DBLP DOI BibTeX RDF
1	Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat	ARMHEx: A hardware extension for DIFT on ARM-based SoCs.	FPL	2017	DBLP DOI BibTeX RDF
1	Ioannis Parnassos, Nikolaos Bellas, Nikolaos Katsaros, Nikolaos Patsiatzis, Athanasios Gkaras, Konstantinos Kanellis, Christos D. Antonopoulos, Michalis Spyrou, Manolis Maroudas	A programming model and runtime system for approximation-aware heterogeneous computing.	FPL	2017	DBLP DOI BibTeX RDF
1	Bruno da Silva 0001, Federico Domínguez, An Braeken, Abdellah Touhafi	A partial reconfiguration based microphone array network emulator.	FPL	2017	DBLP DOI BibTeX RDF
1	Kevin Nam, Blair Fort, Stephen Dean Brown	FISH: Linux system calls for FPGA accelerators.	FPL	2017	DBLP DOI BibTeX RDF
1	Muhsen Owaida, Hantian Zhang, Ce Zhang 0001, Gustavo Alonso	Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms.	FPL	2017	DBLP DOI BibTeX RDF
1	Hongxiang Fan, Xinyu Niu, Qiang Liu 0011, Wayne Luk	F-C3D: FPGA-based 3-dimensional convolutional neural network.	FPL	2017	DBLP DOI BibTeX RDF
1	Tianqi Gao, Jungwook Choi, Shang-nien Tsai, Rob A. Rutenbar	Toward a pixel-parallel architecture for graph cuts inference on FPGA.	FPL	2017	DBLP DOI BibTeX RDF
1	Weina Lu, Wenyan Lu, Jing Ye 0001, Yu Hu 0001, Xiaowei Li 0001	Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators.	FPL	2017	DBLP DOI BibTeX RDF
1	Tingyuan Liang, Liang Feng 0001, Sharad Sinha, Wei Zhang 0012	PAAS: A system level simulator for heterogeneous computing architectures.	FPL	2017	DBLP DOI BibTeX RDF
1	James Stanley Targett, Peter D. Düben, Wayne Luk	Validating optimisations for chaotic simulations.	FPL	2017	DBLP DOI BibTeX RDF
1	Farzad Fatollahi-Fard, David Donofrio, John Shalf, John D. Leidel, Xi Wang 0009, Yong Chen 0001	OpenSoC system architect: An open toolkit for building soft-cores on FPGAs.	FPL	2017	DBLP DOI BibTeX RDF
1	Thomas Townsend, Brent E. Nelson	Vivado design interface: An export/import capability for Vivado FPGA designs.	FPL	2017	DBLP DOI BibTeX RDF
1	Jiayi Sheng, Chen Yang 0010, Ahmed Sanaullah, Michael Papamichael, Adrian M. Caulfield, Martin C. Herbordt	HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics.	FPL	2017	DBLP DOI BibTeX RDF
1	Thomas B. Preußer	Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs.	FPL	2017	DBLP DOI BibTeX RDF
1	Jose Raul Garcia Ordaz, Dirk Koch	Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit.	FPL	2017	DBLP DOI BibTeX RDF
1	Junyi Liu, John Wickerson, George A. Constantinides	Tile size selection for optimized memory reuse in high-level synthesis.	FPL	2017	DBLP DOI BibTeX RDF
1	Bruno da Silva 0001, Federico Domínguez, An Braeken, Abdellah Touhafi	Demonstration of a partial reconfiguration based microphone array network emulator.	FPL	2017	DBLP DOI BibTeX RDF
1	Mitra Purandare, Raphael Polig, Christoph Hagleitner	Accelerated analysis of Boolean gene regulatory networks.	FPL	2017	DBLP DOI BibTeX RDF

Publications at "FPL"( http://dblp.L3S.de/Venues/FPL )