Search results for "GALS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Octavian Petre, Hans G. Kerkhoff	Scan Test Strategy for Asynchronous-Synchronous Interfaces.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (GALS), asynchronous synchronous interface, synchronizers, scan test
19	Erland Nilsson, Johnny Öberg	Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	hot-potato, pseudochronous, network on chip, mesh, clocking, GALS, GPLS
19	Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli	Heterogeneous reactive systems modeling: capturing causality and the correctness of loosely time-triggered architectures (LTTA).	EMSOFT	2004	DBLP DOI BibTeX RDF	distributed deployment, heterogeneous reactive systems, GALS
19	Manuel Salim Maza, Mónico Linares Aranda	Analysis and verification of interconnected rings as clock distribution networks.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	GALS, ring oscillators, clock distribution networks
19	Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli	On-chip communication design: roadblocks and avenues.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	GALS, on-chip networks, latency-insensitive design
19	Manuel Salim Maza, Mónico Linares Aranda	Interconnected rings and oscillators as gigahertz clock distribution nets.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	GALS, ring oscillators, clock distribution networks
13	Mohammad Reza Kakoee, Igor Loi, Luca Benini	A new physical routing approach for robust bundled signaling on NoC links.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	NoC global link routing, bundled routing, delay matching, pin placement, robust signaling, wire length variability, bus routing
13	Thomas Polzer, Thomas Handl, Andreas Steininger	A Metastability-Free Multi-synchronous Communication Scheme for SoCs.	SSS	2009	DBLP DOI BibTeX RDF
13	Yue Ma 0004, Jean-Pierre Talpin, Thierry Gautier	Virtual prototyping AADL architectures in a polychronous model of computation.	MEMOCODE	2008	DBLP DOI BibTeX RDF
13	Nicolas Coste, Hubert Garavel, Holger Hermanns, Richard Hersemeule, Yvain Thonnart, Meriem Zidouni	Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures.	DATE	2008	DBLP DOI BibTeX RDF
13	Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach	Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip.	NOCS	2007	DBLP DOI BibTeX RDF
13	Nikolaos Minas, David Kinniment, Keith Heron, Gordon Russell 0002	A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability.	ASYNC	2007	DBLP DOI BibTeX RDF
13	Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley	Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus.	ASYNC	2007	DBLP DOI BibTeX RDF
13	Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope	High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids.	AICCSA	2007	DBLP DOI BibTeX RDF
13	José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes	Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.	ISVLSI	2006	DBLP DOI BibTeX RDF
13	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.	ISVLSI	2006	DBLP DOI BibTeX RDF
13	Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen	A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.	DSD	2006	DBLP DOI BibTeX RDF
13	Tobias Bjerregaard, Jens Sparsø	Packetizing OCP Transactions in the MANGO Network-on-Chip.	DSD	2006	DBLP DOI BibTeX RDF
13	Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach	A DFT Architecture for Asynchronous Networks-on-Chip.	ETS	2006	DBLP DOI BibTeX RDF
13	Nicolas Halbwachs, Louis Mandel	Simulation and Verification of Asynchronous Systems by means of a Synchronous Model.	ACSD	2006	DBLP DOI BibTeX RDF
13	Yongkang Zhu, David H. Albonesi	Localized microarchitecture-level voltage management.	ISCAS	2006	DBLP DOI BibTeX RDF
13	Xin Jia, Ranga Vemuri	CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture.	VLSI Design	2006	DBLP DOI BibTeX RDF
13	Atanu Chattopadhyay, Zeljko Zilic	GALDS: a complete framework for designing multiclock ASICs and SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
13	Tobias Bjerregaard, Jens Sparsø	A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip.	DATE	2005	DBLP DOI BibTeX RDF
13	Sohini Dasgupta, Alexandre Yakovlev	Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures.	DATE	2005	DBLP DOI BibTeX RDF
13	Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin	An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.	ASYNC	2005	DBLP DOI BibTeX RDF
13	Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar	An Asynchronous Router for Multiple Service Levels Networks on Chip.	ASYNC	2005	DBLP DOI BibTeX RDF
13	Dumitru Potop-Butucaru, Benoît Caillaud	Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications.	ACSD	2005	DBLP DOI BibTeX RDF
13	Peggy B. McGee, Steven M. Nowick, Edward G. Coffman Jr.	Efficient performance analysis of asynchronous systems based on periodicity.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	performance, asynchronous, periodic, marked graphs, petrinets
13	Jean-Pierre Talpin, Dumitru Potop-Butucaru, Julien Ouy, Benoît Caillaud	From multi-clocked synchronous processes to latency-insensitive modules.	EMSOFT	2005	DBLP DOI BibTeX RDF	compositional mapping, separate compilation
13	Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez	Glitch-free discretely programmable clock generation on chip.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
13	Eun-Gu Jung, Eonpyo Hong, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har	Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs.	PCM (1)	2005	DBLP DOI BibTeX RDF
13	Mohammad Reza Mousavi 0001, Paul Le Guernic, Jean-Pierre Talpin, Sandeep K. Shukla, Twan Basten	Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks.	DATE	2004	DBLP DOI BibTeX RDF
13	Venkata Syam P. Rapaka, Emil Talpes, Diana Marculescu	Mixed-clock issue queue design for energy aware, high-performance cores.	ASP-DAC	2004	DBLP DOI BibTeX RDF
13	Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri	A Dynamically Reconfigurable Asynchronous FPGA Architecture.	FPL	2004	DBLP DOI BibTeX RDF
13	Dumitru Potop-Butucaru, Benoît Caillaud, Albert Benveniste	Concurrency in Synchronous Systems.	ACSD	2004	DBLP DOI BibTeX RDF
13	Diana Marculescu	Application adaptive energy efficient clustered architectures.	ISLPED	2004	DBLP DOI BibTeX RDF	dynamic voltage scaling, clustered architectures
13	Grigorios Magklis, José González 0002, Antonio González 0001	Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2.	ICCD	2004	DBLP DOI BibTeX RDF
13	Matthew W. Heath, Ian G. Harris	A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture.	MTV	2003	DBLP DOI BibTeX RDF
13	Joep L. W. Kessels, Ad M. G. Peeters, Suk-Jin Kim	Bridging Clock Domains by Synchronizing the Mice in the Mousetrap.	PATMOS	2003	DBLP DOI BibTeX RDF
13	E. Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi	Power Comparison of Throughput Optimized IC Busses.	ISVLSI	2003	DBLP DOI BibTeX RDF
13	Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta 0001, Frederic Doucet	Polychrony for Refinement-Based Design.	DATE	2003	DBLP DOI BibTeX RDF
13	Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner	Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems.	ASYNC	2003	DBLP DOI BibTeX RDF
13	Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta 0001, Frederic Doucet	Polychrony for Formal Refinement-Checking in a System-Level Design Methodology.	ACSD	2003	DBLP DOI BibTeX RDF
13	Albert Benveniste, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli	Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment.	EMSOFT	2003	DBLP DOI BibTeX RDF
13	Albert Benveniste, Benoît Caillaud, Luca P. Carloni, Paul Caspi, Alberto L. Sangiovanni-Vincentelli	Causality and Scheduling Constraints in Heterogeneous Reactive Systems Modeling.	FMCO	2003	DBLP DOI BibTeX RDF
13	Atanu Chattopadhyay, Zeljko Zilic	A globally asynchronous locally dynamic system for ASICs and SoCs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	all-digital clock generation, dynamic clock manager, globally asynchronous locally synchronous system, asynchronous design
13	Ranadhir Ghosh	Finding Optimal Architectures and Weights for ANN: A Combined Hierarchical Approach.	Australian Conference on Artificial Intelligence	2003	DBLP DOI BibTeX RDF
13	Gérard Berry	Synchronous Programming Techniques for Embedded Systems: Present and Future.	EMSOFT	2001	DBLP DOI BibTeX RDF
13	Mogens Nielsen, Vladimiro Sassone, Jirí Srba	Properties of Distributed Timed-Arc Petri Nets.	FSTTCS	2001	DBLP DOI BibTeX RDF