Search results for "Hardware"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Adrian Stoica, Ricardo Salem Zebulum, Xin Guo 0002, Didier Keymeulen, Michael I. Ferguson, Vu Duong	Silicon Validation of Evolution-Designed Circuits.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
22	Alexander H. Jackson, Richard Canham, Andrew M. Tyrrell	Robot Fault-Tolerance Using an Embryonic Array.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
22	Richard Canham, Alexander H. Jackson, Andrew M. Tyrrell	Robot Error Detection Using an Artificial Immune System.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
22	Hugo de Garis, Jonathan Dinerstein, Ravichandra Sriram	Reversible Evolvable Networks: A Reversible Evolvable Boolean Network Architecture and Methodology to Overcome the Heat Generation Problem in Molecular Scale Brain Building.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
22	Jiangning Xu, Tughrul Arslan	An EHW Architecture for Real-Time GPS Attitude Determination Based on Parallel Genetic Algorithm.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
22	Hajime Shibata, Soji Mori, Nobuo Fujii	Automated Design of Analog Circuits Using Cell-Based Structure .	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
22	Morten Hartmann, Pauline C. Haddow, Frode Eskelund	Evolving Robust Digital Designs.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
22	Jörg Langeheine, Karlheinz Meier, Johannes Schemmel	Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
22	Jennifer Golbeck	Evolving Optimal Parameters for Swarm Control.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
22	Miron Abramovici, John Marty Emmert, Charles E. Stroud	Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
22	Andrew M. Tyrrell, Gordon Hollingworth, Stephen L. Smith 0002	Evolutionary Strategies And Intrinsic Fault Tolerance.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
22	André Stauffer, Daniel Mange, Gianluca Tempesti, Christof Teuscher	Biowatch: A Giant Electronic Bio-Inspired Watch.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
22	John C. Gallagher	A Neuromorphic Paradigm For Extrinsically Evolved Hybrid Analog/digital Device Controllers: Initial Explorations.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
22	Sanza T. Kazadi, Yan Qi, Isaac Park, Nancy Huang, Paul Hwu, Brian Kwan, Waynn Lue, Hubert Li	Insufficiency Of Piecewise Evolution.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
22	Cristina Costa Santini, Marco Aurélio Cavalcanti Pacheco, Marley M. B. R. Vellasco, Moisés H. Szwarcman, Ricardo Salem Zebulum	Pama - Programmable Analog Multiplexer Array.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
22	Ricardo Salem Zebulum, Cristina Costa Santini, Helio Takahiro Sinohara, Marco Aurélio Cavalcanti Pacheco, Marley M. B. R. Vellasco, Moisés H. Szwarcman	A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
22	Stuart J. Flockton, Kevin Sheehan	Behavior of a Building Block for Intrinsic Evolution of Analogue Signal Shaping and Filtering Circuits.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
22	Delon Levi	HereBoy: A Fast Evolutionary Algorithm.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
22	Kosuke Imamura, James A. Foster, Axel W. Krings	The Test Vector Problem and Limitations to Evolving Digital Circuits.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
22	Ron Levy, Stefano Lepri, Eduardo Sanchez, Gilles Ritter, Moshe Sipper	Slate of the Art: An Evolving FPGA-Based Board for Handwritten-Digit Recognition.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
22	Jason Masner, John Cavalieri, James F. Frenzel, James A. Foster	Representation and Robustness for Evolved Sorting Networks.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
22	Piet van Remortel	The Evolution of ROBDDs: Preliminary Results and a First Analysis.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
22	Nicholas J. Macias	The PIG Paradigm: The Design and Use of a Massively Parallel Fine Grained Self-Reconfigurable Infinitely Scalable Architecture.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
22	Paul Loewenstein	Reasoning about State Machines in Higher-Order Logic.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
22	Mark Bickford, Mandayam K. Srivas	Verification of a Pipelined Microprocessor Using Clio.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
22	George J. Milne	Design for Verifiability.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
22	Andreas Raabe, Philipp A. Hartmann, Joachim K. Anlauf	ReChannel: Describing and simulating reconfigurable hardware in systemC.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hardware description, simulation, refinement, dynamic reconfiguration, SystemC, Reconfigurable hardware
22	Túlio Cicero Salvaro de Souza, Jean Everson Martina, Ricardo Felipe Custódio	Audit and backup procedures for hardware security modules.	IDtrust	2008	DBLP DOI BibTeX RDF	PKI ceremony, embedded cryptographic hardware, hardware security module, key life-cycle, key management, public key infrastructure
22	Zoltán Ádám Mann, András Orbán, Péter Arató	Finding optimal hardware/software partitions.	Formal Methods Syst. Des.	2007	DBLP DOI BibTeX RDF	Branch-and-bound, Integer linear programming, Hardware/software partitioning, Hardware/software co-design
22	Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham	Improved verification of hardware designs through antecedent conditioned slicing.	Int. J. Softw. Tools Technol. Transf.	2007	DBLP DOI BibTeX RDF	LTL property, Antecedent conditioned slicing, Verilog RTL, Model checking, Program slicing, Hardware description languages, Hardware verification
22	Masaru Hase, Kazushi Akie, Masaki Nobori, Keisuke Matsumoto	Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware.	ASP-DAC	2007	DBLP DOI BibTeX RDF	54 MHz, real-time VC-1/H.264/MPEG-4 video processing hardware, multifunctional hardware intellectual property, digital moving pictures, mobile products, VC-1 functionality, Internet content, AVC functionality, digital television broadcasting, MPEG-4 functionality, TV telephony, encoding, decoding
22	Robert Strzodka, Marc Droske, Martin Rumpf	Image Registration by a Regularized Gradient Flow. A Streaming Implementation in DX9 Graphics Hardware.	Computing	2004	DBLP DOI BibTeX RDF	graphics hardware computing, DX9 graphics hardware, Image registration, stream processing, multi-scale, gradient flow, multi-grid
22	Tsuyoshi Yamamoto, Munehiro Doi	Design and Implementation of Panoramic Movie System by Using Commodity 3D Graphics Hardware.	Computer Graphics International	2003	DBLP DOI BibTeX RDF	Panorama movie, Image Mosaicking, Commodity Hardware, Texture Mapping, 3D Graphics Hardware
22	Sheu-Chih Cheng, Hsueh-Ming Hang	The Impact of Rate Control Algorithms on Video Codec Hardware Design.	ICIP (2)	1997	DBLP DOI BibTeX RDF	rate control algorithms, video codec hardware design, system-level VLSI design, optimal rate-distortion performance, internal buffer size, performance, video coding, image quality, VLSI implementation, video codecs, DCT coefficients, picture quality, hardware cost
22	David R. Smith	Hardware Synthesis From Encapsulated Verilog Modules.	ASAP	1996	DBLP DOI BibTeX RDF	encapsulated Verilog modules, Verilog writing style, code complexity, automatic inference of control, low level simulation, computational complexity, logic design, inference mechanisms, hardware description languages, hardware synthesis, control points, clock cycle
22	Pai H. Chou, Ross B. Ortega, Gaetano Borriello	The Chinook hardware/software co-synthesis system.	ISSS	1995	DBLP DOI BibTeX RDF	Chinook hardware/software co-synthesis system, custom logic, design co-simulation, design time constraints, embedded controller design, error-prone tasks, function migration, interface hardware, interface software, system components integration, real-time systems, software tools, logic design, microprocessors, logic CAD, microcontrollers, computer-aided design tools
22	Jörg Henkel, Rolf Ernst	A path-based technique for estimating hardware runtime in HW/SW-cosynthesis.	ISSS	1995	DBLP DOI BibTeX RDF	hardware runtime, hardware software cosynthesis, local estimation techniques, local list scheduling, path-based technique, scheduling, computational complexity, computer architecture, quality, systems analysis, circuit CAD, computation time, optimising compilers, synthesis tools
22	Kurt Akeley, Simon J. Watt, Ahna Reza Girshick, Martin S. Banks	A stereo display prototype with multiple focal distances.	ACM Trans. Graph.	2004	DBLP DOI BibTeX RDF	virtual reality, graphics hardware, optics, hardware systems, user-interface hardware
22	Hanspeter Pfister, Jan Hardenbergh, Jim Knittel, Hugh C. Lauer, Larry Seiler	The VolumePro Real-Time Ray-Casting System.	SIGGRAPH	1999	DBLP DOI BibTeX RDF	volume rendering, graphics hardware, rendering systems, rendering hardware, hardware systems
21	Rakesh Kumar	Computing with stochastic processors: revisiting the correctness contract between software and hardware.	ISLPED	2010	DBLP DOI BibTeX RDF	stochastic processor, reliability, error resilience, error tolerance
21	Pablo Montesinos, Matthew Hicks, Samuel T. King, Josep Torrellas	Capo: a software-hardware interface for practical deterministic multiprocessor replay.	ASPLOS	2009	DBLP DOI BibTeX RDF	capo, capoone, replay sphere, deterministic replay
21	Elias Teodoro Silva Jr., David Andrews 0001, Carlos Eduardo Pereira, Flávio Rech Wagner	An Infrastructure for Hardware-Software Co-Design of Embedded Real-Time Java Applications.	ISORC	2008	DBLP DOI BibTeX RDF	Java, Real-time systems, Co-design, Embedded applications
21	Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke	Modulo scheduling for highly customized datapaths to increase hardware reusability.	CGO	2008	DBLP DOI BibTeX RDF	programmable asic, modulo scheduling, loop accelerator
21	Ioannis Mavroidis, Ioannis Papaefstathiou	Efficient testbench code synthesis for a hardware emulator system.	DATE	2007	DBLP DOI BibTeX RDF
21	Elhadj Benkhelifa, Anthony G. Pipe, Mokhtar Nibouche, Gabriel Dragffy	Steps Forward to Evolve Bio-inspired Embryonic Cell-Based Electronic Systems.	ICES	2007	DBLP DOI BibTeX RDF
21	Pao-Ann Hsiung, Pin-Hsien Lu, Chih-Wen Liu	Energy efficient co-scheduling in dynamically reconfigurable systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	energy efficient, reconfigurable systems
21	Fei Xie, Guowu Yang, Xiaoyu Song	Compositional Reasoning for Hardware/Software Co-verification.	ATVA	2006	DBLP DOI BibTeX RDF
21	Stephen A. Edwards	The Challenges of Hardware Synthesis from C-Like Languages.	DATE	2005	DBLP DOI BibTeX RDF
21	Martin Simka, Jan Pelzl, Thorsten Kleinjung, Jens Franke, Christine Priplata, Colin Stahlke, Milos Drutarovský, Viktor Fischer	Hardware Factorization Based on Elliptic Curve Method.	FCCM	2005	DBLP DOI BibTeX RDF
21	Masahide Abe, Hiroki Arai, Masayuki Kawamata	Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
21	Christian Haubelt	Design Space Exploration for Distributed Hardware Reconfigurable Systems.	FPL	2004	DBLP DOI BibTeX RDF
21	Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West	ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers.	FCCM	2004	DBLP DOI BibTeX RDF
21	Tetsuya Higchi	Industrial Applications of Evolvable Hardware.	KES	2004	DBLP DOI BibTeX RDF
21	Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Kathryn S. McKinley, Charles C. Weems	Guided Region Prefetching: A Cooperative Hardware/Software Approach.	ISCA	2003	DBLP DOI BibTeX RDF
21	Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man	Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications.	FPL	2002	DBLP DOI BibTeX RDF
21	Byoungro So, Mary W. Hall, Pedro C. Diniz	A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems.	PLDI	2002	DBLP DOI BibTeX RDF	reuse analysis, design space exploration, loop transformations, data dependence analysis
21	Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
21	George J. Grevera, Jayaram K. Udupa, Dewey Odhner	An Order of Magnitude Faster Isosurface Rendering in Software on a PC than Using Dedicated, General Purpose Rendering Hardware.	IEEE Trans. Vis. Comput. Graph.	2000	DBLP DOI BibTeX RDF	rendering, Volume visualization, isosurfaces, 3D imaging
21	Markus Weinhardt, Wayne Luk	Evaluating Hardware Compilation Techniques.	FCCM	2000	DBLP DOI BibTeX RDF
21	Kari Kostiainen, Jan-Erik Ekberg, N. Asokan, Aarne Rantala	On-board credentials with open provisioning.	AsiaCCS	2009	DBLP DOI BibTeX RDF	provisioning protocols, trusted computing, credentials, secure hardware
21	Gaurav Singh 0006, Sandeep K. Shukla	Verifying Compiler Based Refinement of BluespecTM.	SPIN	2008	DBLP DOI BibTeX RDF	Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker
21	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Towards Nanoelectronics Processor Architectures.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	fault tolerance, reliability, computational model, processor architecture, nanoelectronics, time redundancy, hardware redundancy
21	Sumit Ghosh	P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics
21	Akashi Satoh, Takeshi Sugawara 0001, Naofumi Homma, Takafumi Aoki	High-Performance Concurrent Error Detection Scheme for AES Hardware.	CHES	2008	DBLP DOI BibTeX RDF
21	Pim Tuyls, Geert Jan Schrijen, Boris Skoric, Jan van Geloven, Nynke Verhaegh, Rob Wolters	Read-Proof Hardware from Protective Coatings.	CHES	2006	DBLP DOI BibTeX RDF
21	Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne	Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	virtual machine, synthesis, accelerator
21	Sharad Malik	A Case for Runtime Validation of Hardware.	Haifa Verification Conference	2005	DBLP DOI BibTeX RDF
21	Eunjong Hong, Jai-Hoon Chung, Chae Hoon Lim	Hardware Design and Performance Estimation of the 128-bit Block Cipher Crypton.	CHES	1999	DBLP DOI BibTeX RDF
21	Adrian Stoica, Alex S. Fukunaga, Ken Hayworth, Carlos Salazar-Lazaro	Evolvable Hardware for Space Applications.	ICES	1998	DBLP DOI BibTeX RDF
21	Frank Vahid	Modifying Min-Cut for Hardware and Software Functional Partitioning.	CODES	1997	DBLP DOI BibTeX RDF	Kernighan/Lin, min-cut, Functional partitioning
21	Petru Eles, Zebo Peng, Alexa Doboli	VHDL system-level specification and partitioning in a hardware/software co-synthesis environment.	CODES	1994	DBLP DOI BibTeX RDF
21	Serdar Ates, Ismail Bayezit, Gökhan Inalhan	Design and Hardware-in-the-Loop Integration of a UAV Microavionics System in a Manned-Unmanned Joint Airspace Flight Network Simulator.	J. Intell. Robotic Syst.	2009	DBLP DOI BibTeX RDF	Microavionics, Hardware-in-the-loop testing, Flight network simulator
21	Brian Butka, Janusz Zalewski, Andrew J. Kornecki	Issues in Tool Qualification for Safety-Critical Hardware: What Formal Approaches Can and Cannot Do.	SAFECOMP	2009	DBLP DOI BibTeX RDF	Tool Qualification, Formal Methods, Safety-Critical Systems, Hardware Design, HDL, PLD
21	Antonio Hernández Zavala, Ildar Z. Batyrshin, Imre J. Rudas, Luis A. Villa Vargas, Oscar Camacho Nieto	Parametric Operations for Digital Hardware Implementation of Fuzzy Systems.	MICAI	2009	DBLP DOI BibTeX RDF	digital fuzzy hardware, parametric conjunction, Fuzzy logic, generator, conjunction, disjunction
21	Jewgenij Botaschanjan, Benjamin Hummel	Specifying the worst case: orthogonal modeling of hardware errors.	ISSTA	2009	DBLP DOI BibTeX RDF	af/stem case tool, error filters, error mode specification, modelling hardware errors, error models
21	Tayeb Bouhadiba, Florence Maraninchi	Contract-Based Coordination of Hardware Components for the Development of Embedded Software.	COORDINATION	2009	DBLP DOI BibTeX RDF	Executable Contracts, Embedded Systems, Components, Simulation Models, Hardware/Software Interface
21	Ghiath Al-Kadi, Andrei Sergeevich Terechko	A Hardware Task Scheduler for Embedded Video Processing.	HiPEAC	2009	DBLP DOI BibTeX RDF	Hardware task scheduler, task dependency patterns, H.264 video compression, embedded video processing
21	Daniel Y. Deng, Andrew H. Chan, G. Edward Suh	Hardware authentication leveraging performance limits in detailed simulations and emulations.	DAC	2009	DBLP DOI BibTeX RDF	hardware authentication, secure processors
21	Jigang Wu, Thambipillai Srikanthan, Guang-Wei Zou	New Model and Algorithm for Hardware/Software Partitioning.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	algorithm, complexity, dynamic programming, hardware/software partitioning
21	Ioannis Sourdis, João Bispo, João M. P. Cardoso, Stamatis Vassiliadis	Regular Expression Matching in Reconfigurable Hardware.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	network security, pattern matching, regular expression, reconfigurable hardware
21	Anastasia N. Kastania, Stelios Zimeras, Sophia Kossida	A Biosignal Classification Neural Modeling Methodology for Intelligent Hardware Construction.	New Directions in Intelligent Interactive Multimedia	2008	DBLP DOI BibTeX RDF	intelligent hardware construction, neural networks, classification
21	Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari 0002, Brad Calder, Josep Torrellas	Patching Processor Design Errors with Programmable Hardware.	IEEE Micro	2007	DBLP DOI BibTeX RDF	hardware errors, microarchitecture for fault-tolerance, design defects in real processors, processor errata analysis
21	José M. González, Vern Paxson, Nicholas Weaver	Shunting: a hardware/software architecture for flexible, high-performance network intrusion prevention.	CCS	2007	DBLP DOI BibTeX RDF	nips, fpga, intrusion detection, hardware acceleration, intrusion prevention, nids
21	Patrice Gerin, Hao Shen, A. Chureau, Aimen Bouchhima, Ahmed Amine Jerraya	Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC.	ASP-DAC	2007	DBLP DOI BibTeX RDF	transaction accurate level, hardware/software interface modeling, multiprocessor SoC design, automatic generation tools, system-on-chip, SystemC, abstraction level, architecture exploration
21	Michael R. Hansen, Jan Madsen, Aske Wiid Brekling	Semantics and Verification of a Language for Modelling Hardware Architectures.	Formal Methods and Hybrid Real-Time Systems	2007	DBLP DOI BibTeX RDF	Hardware descriptions, model- checking, verification, semantics
21	Mohammad Mehdi Hassani, Reza Berangi	Improving the COWLS algorithm for hardware software co-synthesis of wireless client-server systems using preference vectors and peak power information.	CompSysTech	2007	DBLP DOI BibTeX RDF	embedded systems, client server systems, wireless systems, low power consumption, hardware-software co-synthesis
21	Abraham Gutiérrez, Luis Fernández, Fernando Arroyo, Santiago Alonso	Hardware and Software Architecture for Implementing Membrane Systems: A Case of Study to Transition P Systems.	DNA	2007	DBLP DOI BibTeX RDF	Transition P System, Software architecture, Hardware implementations, Natural Computing
21	I-Hsuan Huang, Chih-Chun Wang, Shih-Min Chu, Cheng-Zen Yang	Function-Level Multitasking Interface Design in an Embedded Operating System with Reconfigurable Hardware.	EUC	2007	DBLP DOI BibTeX RDF	hardware function, FPGA-based computer, ?C/OS, Reconfigurable computing, multitasking
21	Wu Jigang, Thambipillai Srikanthan, Chengbin Yan	Minimizing Power in Hardware/Software Partitioning.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF	algorithm, complexity, dynamic programming, hardware/software partitioning
21	Saranyan A. Vigraham, John C. Gallagher, Sanjay K. Boddhu	Evolving analog controllers for correcting thermoacoustic instability in real hardware.	GECCO	2005	DBLP DOI BibTeX RDF	evolvable hardware
21	Malay Kumar Pakhira, Rajat K. De	A hardware pipeline for function optimization using genetic algorithms.	GECCO	2005	DBLP DOI BibTeX RDF	hardware pipeline, pipelined GA, stochastic selection, genetic algorithms, function optimization
21	Austin Armbruster, Matt Ryan, Xiaoqing Frank Liu, Ying Cheng, Bruce M. McMillin	Hardware/software co-design for power system test development.	WISER	2004	DBLP DOI BibTeX RDF	HOOMT, test development, hardware/software co-design, system test
21	François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat	ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware.	FSE	2004	DBLP DOI BibTeX RDF	block cipher design, side-channel resistance, reconfigurable hardware, efficient implementations
21	Manfred Weiler, Martin Kraus 0001, Markus Merz, Thomas Ertl	Hardware-Based View-Independent Cell Projection.	IEEE Trans. Vis. Comput. Graph.	2003	DBLP DOI BibTeX RDF	pixel shading, volume rendering, ray tracing, volume visualization, programmable graphics hardware, tetrahedral meshes, unstructured meshes, Cell projection
21	Manfred Weiler, Martin Kraus 0001, Thomas Ertl	Hardware-based view-independent cell projection.	VolVis	2002	DBLP DOI BibTeX RDF	pixel shading, volume rendering, ray tracing, volume visualization, programmable graphics hardware, tetrahedral meshes, unstructured meshes, cell projection
21	JoAnn M. Paul, Arne J. Suppé, Henele I. Adams, Donald E. Thomas	Multi-Level Modeling of Software on Hardware in Concurrent Computation.	IPDPS	2002	DBLP DOI BibTeX RDF	Computer System Performance Modeling, Simulation, Hardware-Software Codesign, Concurrent Computation, Design Hierarchy
21	Robert Siegmund, Dietmar Müller 0001	A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications.	DAC	2002	DBLP DOI BibTeX RDF	controller hardware synthesis, interface-based design, protocol specification
21	Stefan Brabec, Hans-Peter Seidel	Hardware-Accelerated Rendering of Antialiased Shadows with Shadow Maps.	Computer Graphics International	2001	DBLP DOI BibTeX RDF	Frame Buffer Tricks, Image Processing, Rendering, Graphics Hardware, Shadow Algorithms
21	Sung-Ming Yen, Seungjoo Kim, Seongan Lim, Sang-Jae Moon	RSA Speedup with Residue Number System Immune against Hardware Fault Cryptanalysis.	ICISC	2001	DBLP DOI BibTeX RDF	Fault infective CRT, Fault tolerance, Cryptography, Fault detection, Side channel attack, Factorization, Chinese remainder theorem (CRT), Residue number system, Physical cryptanalysis, Hardware fault cryptanalysis
21	Alessandro Marongiu, Paolo Palazzari, Vittorio Rosato	Parallel dedicated hardware devices for heterogeneous computations.	SC	2001	DBLP DOI BibTeX RDF	dedicated hardware device, low-autocorrelation binary sequences, systems of affine recurrence equations