Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Osman Allam, Stijn Eyerman, Lieven Eeckhout |
An efficient CPI stack counter architecture for superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake City, UT, USA, May 3-4, 2012, pp. 55-58, 2012, ACM, 978-1-4503-1244-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Michael Andersch, Chi Ching Chi, Ben H. H. Juurlink |
Programming parallel embedded and consumer applications in OpenMP superscalar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2012, New Orleans, LA, USA, February 25-29, 2012, pp. 281-282, 2012, ACM, 978-1-4503-1160-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Wen-mei W. Hwu |
Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Parallel Computing ![In: Encyclopedia of Parallel Computing, pp. 1962-1966, 2011, Springer, 978-0-387-09765-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Jiongyao Ye, Yu Wan 0002, Takahiro Watanabe |
A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12), pp. 2639-2648, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Jongmyon Kim, Linda M. Wills, D. Scott Wills |
Color-Aware Instructions for Embedded Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 64(3), pp. 335-350, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Bijan Alizadeh, Masahiro Fujita |
Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011, pp. 297-302, 2011, IEEE, 978-1-61284-914-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg |
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA, pp. 11-22, 2011, ACM, 978-1-4503-0472-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(3), pp. 365-377, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Enric Tejedor, Rosa M. Badia, Romina Royo, Josep Lluis Gelpí |
Enabling HMMER for the Grid with COMP Superscalar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS ![In: Conceptual Structures: From Information to Intelligence, 18th International Conference on Conceptual Structures, ICCS 2010, Kuching, Sarawak, Malaysia, July 26-30, 2010. Proceedings, pp. 2629-2638, 2010, Springer, 978-3-642-14196-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Huiba Li, Shengyun Liu, Yuxing Peng 0001, Dongsheng Li 0001, Hangjun Zhou, Xicheng Lu |
Superscalar communication: A runtime optimization for distributed applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 53(10), pp. 1931-1946, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Sebastián Reyes, Camelia Muñoz-Caro, Alfonso Niño, Raül Sirvent, Rosa M. Badia |
Monitoring and steering Grid applications with GRID superscalar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Future Gener. Comput. Syst. ![In: Future Gener. Comput. Syst. 26(4), pp. 645-653, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Gyu Sang Choi, Chita R. Das |
A Superscalar software architecture model for Multi-Core Processors (MCPs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Softw. ![In: J. Syst. Softw. 83(10), pp. 1823-1837, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Mario Schölzel |
Software-based self-repair of statically scheduled superscalar data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, pp. 66-71, 2010, IEEE Computer Society, 978-1-4244-6612-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Sandeep Navada, Niket Kumar Choudhary, Eric Rotenberg |
Criticality-driven superscalar design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, Vienna, Austria, September 11-15, 2010, pp. 261-272, 2010, ACM, 978-1-4503-0178-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero |
Task Superscalar: An Out-of-Order Task Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA, pp. 89-100, 2010, IEEE Computer Society, 978-0-7695-4299-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Jörg Mische, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer |
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2010, 23rd International Conference, Hannover, Germany, February 22-25, 2010. Proceedings, pp. 2-14, 2010, Springer, 978-3-642-11949-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Jongbok Lee |
A Superscalar Processor Model for Limited Functional Units Using Instruction Dependencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATA ![In: Proceedings of the ISCA 25th International Conference on Computers and Their Applications, CATA 2010, March 24-26, 2010, Sheraton Waikiki Hotel, Honolulu, Hawaii, USA, pp. 294-299, 2010, ISCA, 978-1-880843-75-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
17 | Ritu Baniwal, Kumar Sambhav Pandey |
Recent Trends in Superscalar Architecture to Exploit More Instruction Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICT ![In: Information and Communication Technologies - International Conference, ICT 2010, Kochi, Kerala, India, September 7-9, 2010. Proceedings, pp. 660-665, 2010, Springer, 978-3-642-15765-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Meltem Ozsoy, Yusuf Onur Koçberber, Mehmet Kayaalp 0001, Oguz Ergin |
Dynamic register file partitioning in superscalar microprocessors for energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 28th International Conference on Computer Design, ICCD 2010, 3-6 October 2010, Amsterdam, The Netherlands, Proceedings, pp. 515-520, 2010, IEEE Computer Society, 978-1-4244-8936-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Faheem Sheikh, Shahid Masud, Rehan Ahmed |
Superscalar architecture design for high performance DSP operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 33(2), pp. 154-160, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Arpad Gellert, Adrian Florea, Lucian N. Vintan |
Exploiting selective instruction reuse and value prediction in a superscalar architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 55(3), pp. 188-195, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2009), Samos, Greece, July 20-23, 2009, pp. 41-48, 2009, IEEE, 978-1-4244-4501-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Jorge Ortiz 0002 |
A Reconfigurable Superscalar Processor Architecture for FPGA-based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2009 International Conference on Computer Design, CDES 2009, July 13-16, 2009, Las Vegas Nevada, USA, pp. 211-217, 2009, CSREA Press, 1-60132-096-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
17 | Nasir Mohyuddin, Kimish Patel, Massoud Pedram |
Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 27th International Conference on Computer Design, ICCD 2009, Lake Tahoe, CA, USA, October 4-7, 2009, pp. 166-172, 2009, IEEE Computer Society, 978-1-4244-5029-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Raül Sirvent Pardell |
GRID superscalar: a programming model for the Grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2009 |
RDF |
|
17 | Jorge Ortiz 0002 |
Synthesis Techniques for Semi-Custom Dynamically Reconfigurable Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2009 |
RDF |
|
17 | Christopher B. Smith, David R. Mandel, Eugene John |
A superscalar simulation employing poisson distributed stalls. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 34(3), pp. 192-201, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Wlodzimierz Funika, Piotr Machner, Marian Bubak, Rosa M. Badia, Raül Sirvent |
Performance Monitoring of GRID superscalar: Summing up. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoreGRID Workshop on Grid Middleware ![In: Grid and Services Evolution, Proceedings of the 3rd CoreGRID Workshop on Grid Middleware, June 5-6, 2008, Barcelona, Spain, pp. 1-13, 2008, 978-0-387-85966-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Xianfeng Zhao |
Structural Optimization on Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (3) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 3: Grid Computing / Distributed and Parallel Computing / Information Security, December 12-14, 2008, Wuhan, China, pp. 427-430, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Tameesh Suri |
Improving instruction level parallelism through reconfigurable units in superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 35(3), pp. 20-27, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz |
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SoC: Advanced Topics on Systems on a Chip - A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007), October 15-17, 2007, Atlanta, USA, pp. 1-22, 2007, Springer, 978-0-387-93845-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Virginia Escuder, Raúl Durán, Rafael Rico |
Analysis of x86 ISA Condition Codes Influence on Superscalar Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2007, 14th International Conference, Goa, India, December 18-21, 2007, Proceedings, pp. 119-132, 2007, Springer, 978-3-540-77219-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Condition codes, Graph theory, Instruction level parallelism, Instruction set architecture |
17 | Shijian Zhang, Weiwu Hu |
CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 16th Asian Test Symposium, ATS 2007, Beijing, China, October 8-11, 2007, pp. 313-318, 2007, IEEE, 0-7695-2890-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Jonathan Evans, Kyle Rupnow, Katherine Compton |
Reconfigurable Functional Units for Scientific Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007, pp. 73-80, 2007, IEEE, 1-4244-1472-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Ani Anciaux-Sedrakian, Rosa M. Badia, Raül Sirvent, Josep M. Pérez, Thilo Kielmann, André Merzky |
GRID superscalar and job mapping on the reliable grid resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoreGRID Workshop - Making Grids Work ![In: Making Grids Work: Proceedings of the CoreGRID Workshop on Programming Models Grid and P2P System Architecture Grid Systems, Tools and Environments, 12-13 June 2007, Heraklion, Crete, Greece, pp. 77-88, 2007, Springer, 978-0-387-78447-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Rosa M. Badia, Raül Sirvent, Marian Bubak, Wlodzimierz Funika, Piotr Machner |
Performance monitoring of GRID superscalar with OCM-G/G-PM: improvements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoreGRID Workshop - Making Grids Work ![In: Making Grids Work: Proceedings of the CoreGRID Workshop on Programming Models Grid and P2P System Architecture Grid Systems, Tools and Environments, 12-13 June 2007, Heraklion, Crete, Greece, pp. 273-283, 2007, Springer, 978-0-387-78447-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Ian Michael Caulfield |
Complexity-effective superscalar embedded processors using instruction-level distributed processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2007 |
RDF |
|
17 | Yasuo Sugure, Seiji Takeuchi, Yuichi Abe, Hiromichi Yamada, Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka, Takanori Shimura |
Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 89-C(6), pp. 844-850, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Juan L. Aragón, José M. González, Antonio González 0001 |
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(3), pp. 281-291, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low-power design, processor architecture, energy-aware systems, Control speculation |
17 | Tsai Chi Huang, Linda M. Wills, Roy W. Melton, Cecil O. Alford |
Predicting communication protocol performance on superscalar architectures using instruction dependency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Perform. Evaluation ![In: Perform. Evaluation 63(9-10), pp. 939-955, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Stephen Hill |
Design of a reusable 1GHz, superscalar ARM processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2006 IEEE Hot Chips 18 Symposium (HCS), Stanford, CA, USA, August 20-22, 2006, pp. 1-18, 2006, IEEE, 978-1-4673-8867-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Oguz Ergin |
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 477-485, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil |
A Predictive Performance Model for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 161-170, 2006, IEEE Computer Society, 0-7695-2732-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Raül Sirvent, Rosa M. Badia, Natalia Currle-Linde, Michael M. Resch |
GRID Superscalar and GriCoL: Integrating Different Programming Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoreGRID Integration Workshop ![In: Achievements in European Research on Grid Systems: CoreGRID Integration Workshop 2006, Krakow, Poland, October 19-20, Selected Papers, pp. 139-150, 2006, Springer, 978-0-387-72811-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Rosa M. Badia, Raül Sirvent, Marian Bubak, Wlodzimierz Funika, Piotr Machner |
Performance monitoring of GRID superscalar with OCM-G/G-PM: integration issues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoreGRID Integration Workshop ![In: Achievements in European Research on Grid Systems: CoreGRID Integration Workshop 2006, Krakow, Poland, October 19-20, Selected Papers, pp. 193-205, 2006, Springer, 978-0-387-72811-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Yongxin Zhu 0001, Weng-Fai Wong, Stefan Andrei |
Co-optimization of Performance and Power in a Superscalar Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC Workshops ![In: Emerging Directions in Embedded and Ubiquitous Computing, EUC 2006 Workshops: NCUS, SecUbiq, USN, TRUST, ESO, and MSA, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 868-878, 2006, Springer, 3-540-36850-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Toshinori Sato, Akihiro Chiyonobu |
Evaluating the Impact of Fault Recovery on Superscalar Processor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 18-20 December, 2006, University of California, Riverside, USA, pp. 369-370, 2006, IEEE Computer Society, 0-7695-2724-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Jessica H. Tseng |
Banked microarchitectures for complexity-effective superscalar microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
RDF |
|
17 | Timothy M. Jones 0001 |
Compiler-directed energy savings in superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
RDF |
|
17 | Jean-Luc Gaudiot, Jung-Yup Kang, Won Woo Ro |
Techniques to Improve Performance Beyond Pipelining: Superpipelining, Superscalar, and VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Comput. ![In: Adv. Comput. 63, pp. 2-35, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Douglas A. Lyon |
Java Optimization for Superscalar and Vector Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Object Technol. ![In: J. Object Technol. 4(2), pp. 27-40, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Toshinori Sato, Akihiro Chiyonobu |
An Energy-Efficient Clustered Superscalar Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 88-C(4), pp. 544-551, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Oleg Bessonov, Dominique Fougère, Bernard Roux |
Development of efficient computational kernels and linear algebra routines for out-of-order superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Future Gener. Comput. Syst. ![In: Future Gener. Comput. Syst. 21(4), pp. 743-748, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Julio Sahuquillo, Salvador Petit, Ana Pont, Veljko M. Milutinovic |
Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 51(8), pp. 451-469, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Rafael Rico, Juan Ignacio Pérez, José Antonio de Frutos |
The impact of x86 instruction set architecture on superscalar processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 51(1), pp. 63-77, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Pierre Salverda, Craig B. Zilles |
A Criticality Analysis of Clustering in Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 55-66, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Testing Superscalar Processors in Functional Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 747-750, 2005, IEEE, 0-7803-9362-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Mihai Budiu, Pedro V. Artigas, Seth Copen Goldstein |
Dataflow: A Complement to Superscalar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2005, March 20-22, 2005, Austin, Texas, USA, Proceedings, pp. 177-186, 2005, IEEE Computer Society, 0-7803-8965-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Peng Zhou, Soner Önder, Steve Carr 0001 |
Fast branch misprediction recovery in out-of-order superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, Massachusetts, USA, June 20-22, 2005, pp. 41-50, 2005, ACM, 1-59593-167-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
processor state, checkpoint, recovery, branch misprediction |
17 | Manuel A. (Manuel Alejandro) Pajuelo González |
Speculative Vectorization for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2005 |
RDF |
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17 | Dean G. Bair, Steven M. German, William D. Wollyung, Edward J. Kaminski Jr., James Schafer, Michael P. Mullen, William J. Lewis, Rebecca Wisniewski, Joerg Walter, Steven Mittermaier, Visda Vokhshoori, Robert J. Adkins, Michael Halas, Thomas Ruane, Ursel Hahn |
Functional verification of the z990 superscalar, multibook microprocessor complex. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 48(3-4), pp. 347-366, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose |
Complexity-Effective Reorder Buffer Designs for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(6), pp. 653-665, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Chao-Chin Wu |
Embedding a superscalar processor onto a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 28(4), pp. 147-156, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Vladimir Lazarov, Maria Marinova |
Dependencies evaluation in superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CompSysTech ![In: Proceedings of the 5th International Conference on Computer Systems and Technologies, CompSysTech 2004, Rousse, Bulgaria, June 17-18, 2004, pp. 1-4, 2004, ACM, 978-954-9641-38-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Mars Lan, Morteza Biglari-Abhari |
An Adaptive Superscalar Architecture for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA/VLSI ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA, pp. 151-156, 2004, CSREA Press, 1-932415-41-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
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17 | Shahzad Nazar, Behrooz A. Shirazi, Sungyong Jung |
Performance/Energy Efficiency Analysis of Register Files in Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA/VLSI ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA, pp. 325-331, 2004, CSREA Press, 1-932415-41-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
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17 | Axel Böttcher |
Visualizing the MMIX superscalar pipeline: not only for teaching purposes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2004 workshop on Computer architecture education - Held in conjunction with the 31st International Symposium on Computer Architecture, WCAE@ISCA 2004, Munich, Germany, June 19, 2004, pp. 11, 2004, ACM, 978-1-4503-4733-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Joan-Manuel Parcerisa |
Design of Clustered Superscalar Microarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2004 |
RDF |
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17 | Miroslav N. Velev, Randal E. Bryant |
Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Symb. Comput. ![In: J. Symb. Comput. 35(2), pp. 73-106, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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17 | Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera |
Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 49(12-15), pp. 543-555, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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17 | Parimal Patel, Venkataramana Reddipalli |
Design Considerations of Implementing a Superscalar CPU in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATA ![In: Proceedings of the ISCA 18th International Conference Computers and Their Applications, Honolulu, Hawaii, USA, March 26-28, 2003, pp. 296-299, 2003, ISCA, 1-880843-46-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
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17 | Elena Zaharieva-Stoyanova, Lorentz Jäntschi |
Application of software data dependency detection algorithm in superscalar computer architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CompSysTech ![In: Proceedings of the 4th International Conference on Computer Systems and Technologies: e-Learning, CompSysTech 2003, Rousse, Bulgaria, June 19-20, 2003, pp. 107-112, 2003, ACM, 978-954-9641-33-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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17 | Hee-Jun Yoo, Jin-Young Choi |
Process Algebraic Model of Superscalar Processor Programs for Instruction Level Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 7th International Conference, PaCT 2003, Novosibirsk, Russia, September 15-19, 2003, Proceedings, pp. 180-184, 2003, Springer, 3-540-40673-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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17 | Oleg Bessonov, Dominique Fougère, Bernard Roux |
Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 7th International Conference, PaCT 2003, Novosibirsk, Russia, September 15-19, 2003, Proceedings, pp. 345-353, 2003, Springer, 3-540-40673-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors |
17 | Feng-Jiann Shiao, Jong-Jiann Shieh |
An Issue Logic for Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAINE ![In: Proceedings of the 16th International Conference on Computer Applications in Industry and Engineering, November 11-13, 2003, Imperial Palace Hotel, Las Vegas, Nevada, USA, pp. 268-271, 2003, ISCA, 1-880843-49-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
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17 | James C. Hoe |
Superscalar out-of-order demystified in four instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2003 workshop on Computer architecture education - Held in conjunction with the 30th International Symposium on Computer Architecture, WCAE@ISCA 2003, San Diego, California, USA, June 8, 2003, pp. 5, 2003, ACM, 978-1-4503-4732-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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17 | Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung |
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 18(3), pp. 393-409, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
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17 | Toshinori Sato, Itsujiro Arita |
Simplifying Instruction Issue Logic in Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 341-346, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Sascha Wennekers, Christian Siemers |
Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Trends in Network and Pervasive Computing - ARCS 2002, International Conference on Architecture of Computing Systems, Karlsruhe, Germany, April 8-12, 2002, Proceedings, pp. 165-178, 2002, Springer, 3-540-43409-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Siddharth Rele, Santosh Pande, Soner Önder, Rajiv Gupta 0001 |
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 11th International Conference, CC 2002, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2002, Grenoble, France, April 8-12, 2002, Proceedings, pp. 261-275, 2002, Springer, 3-540-43369-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | Zheng-Kuo Wu, Jong-Jiann Shieh |
Block Based Fetch Engine for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAINE ![In: Proceedings of the 15th International Conference on Computer Applications in Industry and Engineering, November 7-9, 2002, Clarion Hotel Bay View, San Diego, California, USA, pp. 201-204, 2002, ISCA, 1-880843-45-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
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17 | R.-Ming Shiu, Hui-Yue Hwang, Jean Jyh-Jiun Shann |
Aggressive Schduling for Memory Accesses of CISC Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 17(5), pp. 787-803, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
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17 | Pierre Michaud, André Seznec, Stéphan Jourdan |
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 29(1), pp. 35-58, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Bernard Goossens |
Handling 16 instructions per cycle in a superscalar processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Future Gener. Comput. Syst. ![In: Future Gener. Comput. Syst. 17(6), pp. 699-709, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Yasunori Kimura, Kouya Shimura, Haruko Nishimoto, Motoyuki Kawaba, Takeshi Eguchi |
Building a design support tool for superscalar processors and its case studies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 32(12), pp. 67-79, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori |
A high-speed dynamic instruction scheduling scheme for superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 225-236, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Ioannis Vakalis |
A Comparison Study of the Behavior of Equivalent Algorithms in Fault Injection Experiments in Parallel Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAFECOMP ![In: Computer Safety, Reliability and Security, 20th International Conference, SAFECOMP 2001, Budapest, Hungary, September 26-28, 2001, Proceedings, pp. 145-155, 2001, Springer, 3-540-42607-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
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17 | Sid Ahmed Ali Touati |
Register Saturation in Superscalar and VLIW Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 213-228, 2001, Springer, 3-540-41861-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Julien Sébot, Nathalie Drach-Temam |
Memory Bandwidth: The True Bottleneck of SIMD Multimedia Performance on a Superscalar Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2001: Parallel Processing, 7th International Euro-Par Conference Manchester, UK August 28-31, 2001, Proceedings, pp. 439-447, 2001, Springer, 3-540-42495-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Gabriel H. Loh |
A time-stamping algorithm for efficient performance estimation of superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS/Performance ![In: Proceedings of the Joint International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS/Performance 2001, June 16-20, 2001, Cambridge, MA, USA, pp. 72-81, 2001, ACM, 1-58113-334-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Yung-Chung Wu, Jong-Jiann Shieh |
A Multiple Blocks Fetch Engine for High Performance Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCS ![In: Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, August 8-10, 2001, Richardson, Texas, USA, pp. 339-344, 2001, ISCA, 1-880843-39-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
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17 | Matt Postiff, David A. Greene, Steven E. Raasch, Trevor N. Mudge |
Integrating superscalar processor components to implement register caching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 15th international conference on Supercomputing, ICS 2001, Sorrento, Napoli, Italy, June 16-21, 2001, pp. 348-357, 2001, ACM, 1-58113-410-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Miroslav N. Velev, Randal E. Bryant |
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 226-231, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Frank P. Burns, Albert Koelmans, Alexandre Yakovlev |
WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 18(2/3), pp. 275-288, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Andrew Wolfe, Derek B. Noonburg |
A Superscalar 3D Graphics Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Instr. Level Parallelism ![In: J. Instr. Level Parallelism 2, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
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17 | S. J. Davis, C. J. Elston, Paul A. Findlay |
Register bypassing in an asynchronous superscalar processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 46(9), pp. 749-764, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | K. S. Loh, Weng-Fai Wong |
Multiple context multithreaded superscalar processor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 46(3), pp. 243-258, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Amirali Baniasadi, Andreas Moshovos |
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000, pp. 337-347, 2000, ACM/IEEE Computer Society, 0-7695-0924-x. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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17 | Andreas Moshovos, Gurindar S. Sohi |
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 301-312, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Scheduling, Cache, Memory, Instruction Level Parallelism |
17 | Fujio Ishihara, Christian Klinger, Ken-ichi Agawa |
Clock design of 300MHz 128-bit 2-way superscalar microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, pp. 647-652, 2000, ACM, 0-7803-5974-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|