Search results for "chip-multiprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Stefanos Kaxiras, Girija J. Narlikar, Alan D. Berenbaum, Zhigang Hu	Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads.	CASES	2001	DBLP DOI BibTeX RDF
11	Jörg Hilgenstock, Klaus Herrmann 0002, Peter Pirsch	Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
8	Chen Tian 0002, Min Feng 0001, Rajiv Gupta 0001	Speculative parallelization using state separation and multiple value prediction.	ISMM	2010	DBLP DOI BibTeX RDF	multicore processors, speculative parallelization
8	Gaurav Dhiman, Vasileios Kontorinis, Dean M. Tullsen, Tajana Rosing, Eric Saxe, Jonathan Chew	Dynamic workload characterization for power efficient scheduling on CMP systems.	ISLPED	2010	DBLP DOI BibTeX RDF	power, multi-cores, workload characterization
8	Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su	A hyperscalar multi-core architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors
8	Li Zhao 0002, Ravi R. Iyer 0001, Srihari Makineni, Don Newell, Liqun Cheng	NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cache, directory
8	Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt	Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems.	ASPLOS	2010	DBLP DOI BibTeX RDF	fairness, shared memory systems, system performance, multi-core systems
8	Kshitij Sudan, Niladrish Chatterjee, David W. Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis	Micro-pages: increasing DRAM efficiency with locality-aware data placement.	ASPLOS	2010	DBLP DOI BibTeX RDF	dram row-buffer management, data placement
8	Fernando Castro, Regana Noor, Alok Garg, Daniel Chaver, Michael C. Huang 0001, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado	Replacing Associative Load Queues: A Timing-Centric Approach.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
8	Jaejin Lee, Changhee Jung, Daeseob Lim, Yan Solihin	Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
8	Takeshi Ogasawara, Ken Sakamura	How lock contention affects energy use in a CMP server.	OOPSLA Companion	2009	DBLP DOI BibTeX RDF	Java, energy efficiency, CMP, DVFS, lock contention
8	Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt	Coordinated control of multiple prefetchers in multi-core systems.	MICRO	2009	DBLP DOI BibTeX RDF	prefetching, multi-core, feedback control, memory systems
8	Harold Ishebabi, Philipp Mahr, Christophe Bobda, Martin Gebser, Torsten Schaub	Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs.	LPNMR	2009	DBLP DOI BibTeX RDF
8	Alyssa Bonnoit, Sebastian Herbert, Diana Marculescu, Lawrence T. Pileggi	Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic voltage / frequency scaling, body biasing
8	Noriko Takagi, Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura	Cooperative shared resource access control for low-power chip multiprocessors.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, chip multiprocessors, cache partitioning, dvfs, resource conflict
8	Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir	A case for integrated processor-cache partitioning in chip multiprocessors.	SC	2009	DBLP DOI BibTeX RDF
8	Yang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Padma Raghavan	Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
8	Wei Hu 0001, Tianzhou Chen, Qingsong Shi	Exploring multicore computing education in China by model curriculum construction.	Summit on Computing Education in China	2008	DBLP DOI BibTeX RDF	model curriculum, programming, multicore
8	Jonathan A. Winter, David H. Albonesi	Scheduling algorithms for unpredictably heterogeneous CMP architectures.	DSN	2008	DBLP DOI BibTeX RDF
8	José L. Abellán, Juan Fernández 0001, Manuel E. Acacio	CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE.	PDP	2008	DBLP DOI BibTeX RDF
8	Luke Yen, Stark C. Draper, Mark D. Hill	Notary: Hardware techniques to enhance signatures.	MICRO	2008	DBLP DOI BibTeX RDF
8	Kaiyu Chen, Sharad Malik, Priyadarsan Patra	Runtime validation of memory ordering using constraint graph checking.	HPCA	2008	DBLP DOI BibTeX RDF
8	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs.	HiPC	2008	DBLP DOI BibTeX RDF
8	Qi Zhang, Yurong Chen 0001, Yimin Zhang 0002, Yinlong Xu	SIFT implementation and optimization for multi-core systems.	IPDPS	2008	DBLP DOI BibTeX RDF
8	Michel Dubois 0001, Hyunyoung Lee	STAMP: A universal algorithmic model for next-generation multithreaded machines and systems.	IPDPS	2008	DBLP DOI BibTeX RDF
8	Kevin Brownell, Gu-Yeon Wei, David M. Brooks	Evaluation of voltage interpolation to address process variations.	ICCAD	2008	DBLP DOI BibTeX RDF
8	Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala	Parameterized transient thermal behavioral modeling for chip multiprocessors.	ICCAD	2008	DBLP DOI BibTeX RDF
8	Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba	Clustered Decoupled Software Pipelining on Commodity CMP.	ICPADS	2008	DBLP DOI BibTeX RDF
8	José L. Abellán, Juan Fernández 0001, Manuel E. Acacio	Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades.	ICCS (1)	2008	DBLP DOI BibTeX RDF
8	Jason Zebchuk, Srihari Makineni, Donald Newell	Re-examining cache replacement policies.	ICCD	2008	DBLP DOI BibTeX RDF
8	Khalid Latif 0002, Moazzam Fareed Niazi, Hannu Tenhunen, Tiberiu Seceleanu, Sakir Sezer	Application development flow for on-chip distributed architectures.	SoCC	2008	DBLP DOI BibTeX RDF
8	Jisheng Zhao, Matthew Horsnell, Mikel Luján, Ian Rogers, Chris C. Kirkham, Ian Watson	Adaptive Loop Tiling for a Multi-cluster CMP.	ICA3PP	2008	DBLP DOI BibTeX RDF	Multi-Cluster CMP, Automatic Parallelization, Loop Tiling, Feedback-Directed Optimization
8	Wangyuan Zhang, Tao Li 0006	Managing multi-core soft-error reliability through utility-driven cross domain optimization.	ASAP	2008	DBLP DOI BibTeX RDF
8	Antonio Flores, Manuel E. Acacio, Juan L. Aragón	Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs.	ICPP	2008	DBLP DOI BibTeX RDF
8	Xiaoye Sherry Li	Evaluation of Sparse LU Factorization and Triangular Solution on Multicore Platforms.	VECPAR	2008	DBLP DOI BibTeX RDF
8	Sean Rul, Hans Vandierendonck, Koen De Bosschere	Extracting coarse-grain parallelism in general-purpose programs.	PPoPP	2008	DBLP DOI BibTeX RDF	do-across, thread-level parallelism, coarse-grain parallelism
8	Rezaul Alam Chowdhury, Vijaya Ramachandran	Cache-efficient dynamic programming algorithms for multicores.	SPAA	2008	DBLP DOI BibTeX RDF	parallelism, multicore, shared cache, distributed cache, cache-efficiency
8	Olatunji Ruwase, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Shimin Chen, Michael Kozuch, Michael P. Ryan	Parallelizing dynamic information flow tracking.	SPAA	2008	DBLP DOI BibTeX RDF	dynamic information flow tracking (dift), log-based monitoring, parallel algorithm, taint analysis, program monitoring
8	Guilherme Ottoni, David I. August	Communication optimizations for global multi-threaded instruction scheduling.	ASPLOS	2008	DBLP DOI BibTeX RDF	graph min-cut, communication, synchronization, data-flow analysis, multi-threading, instruction scheduling
8	Alexander D. Rast, Xin Jin 0003, Muhammad Mukaram Khan, Steve B. Furber	The Deferred Event Model for Hardware-Oriented Spiking Neural Networks.	ICONIP (2)	2008	DBLP DOI BibTeX RDF
8	Michael Gschwind, David Erb, Sid Manning, Mark Nutter	An Open Source Environment for Cell Broadband Engine System Software.	Computer	2007	DBLP DOI BibTeX RDF	chip multiprocessors, open source software, multicore processors, Cell Broadband Engine
8	Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry	CMP Support for Large and Dependent Speculative Threads.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	databases, Multiprocessor Systems, cache coherence, thread-level speculation
8	Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang 0011, Michael Orshansky	Architecting a reliable CMP switch architecture.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	CMP switch, reliability, defect-tolerance
8	Salman Khan 0002, Polychronis Xekalakis, John Cavazos, Marcelo Cintra	Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems.	PACT	2007	DBLP DOI BibTeX RDF
8	Neil Vachharajani, Ram Rangan, Easwaran Raman, Matthew J. Bridges, Guilherme Ottoni, David I. August	Speculative Decoupled Software Pipelining.	PACT	2007	DBLP DOI BibTeX RDF
8	Thuy Duong Vu, Chris R. Jesshope	Formalizing SANE Virtual Processor in Thread Algebra.	ICFEM	2007	DBLP DOI BibTeX RDF	SANE Virtual Processor, microthreading, thread algebra
8	Jun Sung Park, Jung-Gyu Park, Hyo-Jung Song	Implementation of OpenMP Work-Sharing on the Cell Broadband Engine Architecture.	IWOMP	2007	DBLP DOI BibTeX RDF
8	Jie Tao 0001, Kim D. Hoàng, Wolfgang Karl	CMP Cache Architecture and the OpenMP Performance.	IWOMP	2007	DBLP DOI BibTeX RDF
8	Karin Strauss, Xiaowei Shen, Josep Torrellas	Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors.	MICRO	2007	DBLP DOI BibTeX RDF
8	Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe	Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding.	MICRO	2007	DBLP DOI BibTeX RDF
8	Guilherme Ottoni, David I. August	Global Multi-Threaded Instruction Scheduling.	MICRO	2007	DBLP DOI BibTeX RDF
8	Lu Peng 0001, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-Kuang Chen, David M. Koppelman	Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study.	IPCCC	2007	DBLP DOI BibTeX RDF
8	Lei Miao 0002, Yong Qi, Di Hou, Chang-li Wu, Yue-hua Dai	Dynamic Power Management and Dynamic Voltage Scaling in Real-time CMP Systems.	IEEE NAS	2007	DBLP DOI BibTeX RDF
8	Michel Dubois 0001, Hyunyoung Lee, Lan Lin	STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems.	IPDPS	2007	DBLP DOI BibTeX RDF
8	Feiqi Su, Xudong Shi 0003, Gang Liu, Ye Xia 0001, Jih-Kwon Peir	Comparative evaluation of multi-core cache occupancy strategies.	ICPADS	2007	DBLP DOI BibTeX RDF
8	James Tuck 0001, Wei Liu 0014, Josep Torrellas	CAP: Criticality analysis for power-efficient speculative multithreading.	ICCD	2007	DBLP DOI BibTeX RDF
8	Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim 0001, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen	Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	parallelization, CMP, characterization, physical simulation
8	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	Core fusion: accommodating software diversity in chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, reconfigurable architectures, software diversity
8	Arindam Mallik, Yu Zhang, Gokhan Memik	Automated task distribution in multicore network processors using statistical analysis.	ANCS	2007	DBLP DOI BibTeX RDF
8	Tomer Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé	Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
8	Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu	Memory-Conscious Reliable Execution on Embedded Chip Multiprocessors.	DSN	2006	DBLP DOI BibTeX RDF
8	Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe	Reunion: Complexity-Effective Multicore Redundancy.	MICRO	2006	DBLP DOI BibTeX RDF
8	Aamer Jaleel, Matthew Mattina, Bruce L. Jacob	Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads.	HPCA	2006	DBLP DOI BibTeX RDF
8	Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang 0011, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky	BulletProof: a defect-tolerant CMP switch architecture.	HPCA	2006	DBLP DOI BibTeX RDF
8	JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun	The common case transactional behavior of multithreaded programs.	HPCA	2006	DBLP DOI BibTeX RDF
8	Guilin Chen, Mahmut T. Kandemir, Feihui Li	Energy-aware computation duplication for improving reliability in embedded chip multiprocessors.	ASP-DAC	2006	DBLP DOI BibTeX RDF
8	Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin	Helper thread prefetching for loosely-coupled multiprocessor systems.	IPDPS	2006	DBLP DOI BibTeX RDF
8	Jeffrey Namkung, Dohyung Kim, Rajesh K. Gupta 0001, Igor Kozintsev, Jean-Yves Bouguet, Carole Dulong	Phase guided sampling for efficient parallel application simulation.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	phase analysis, simulation, sampling, chip multiprocessors, multithreading
8	Jie Tao 0001, Siegfried Schloissnig, Wolfgang Karl	Analysis of the Spatial and Temporal Locality in Data Accesses.	International Conference on Computational Science (2)	2006	DBLP DOI BibTeX RDF
8	Mahmut T. Kandemir, Seung Woo Son 0001	Reducing power through compiler-directed barrier synchronization elimination.	ISLPED	2006	DBLP DOI BibTeX RDF	barrier elimination, low power, compiler
8	Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven	Static cache partitioning robustness analysis for embedded on-chip multi-processors.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	robustness, cache partitioning, multi-processors
8	Daewook Kim, Manho Kim, Gerald E. Sobelman	DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Stephen B. Furber, Steve Temple, Andrew D. Brown	On-chip and inter-chip networks for modeling large-scale neural systems.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Ravi R. Iyer 0001, Mahesh Bhat, Li Zhao 0002, Ramesh Illikkal, Srihari Makineni, Michael Jones, Kumar Shiv, Donald Newell	Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers.	IISWC	2006	DBLP DOI BibTeX RDF
8	Ozcan Ozturk 0001, Mahmut T. Kandemir, Seung Woo Son 0001, Mustafa Karaköy	Selective code/data migration for reducing communication energy in embedded MpSoC architectures.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	energy, migration, MPSoC
8	Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk 0001	Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs.	ISQED	2006	DBLP DOI BibTeX RDF
8	Wenbin Yao, Nianmin Yao, Shaobin Cai, Jun Ni	Verification Environment for a SCMP Architecture.	IMSCCS (2)	2006	DBLP DOI BibTeX RDF
8	Wei Liu 0014, James Tuck 0001, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas	POSH: a TLS compiler that exploits program structure.	PPoPP	2006	DBLP DOI BibTeX RDF	TLS compiler, profiling, prefetching, thread-level speculation, multi-core architecture
8	Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry	Tolerating Dependences Between Large Speculative Threads Via Sub-Threads.	ISCA	2006	DBLP DOI BibTeX RDF
8	Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck	A defect tolerant self-organizing nanoscale SIMD architecture.	ASPLOS	2006	DBLP DOI BibTeX RDF	self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
8	Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi	Computation spreading: employing hardware migration to specialize CMP cores on-the-fly.	ASPLOS	2006	DBLP DOI BibTeX RDF	dynamic specialization, cache locality
8	Engin Ipek, Sally A. McKee, Rich Caruana, Bronis R. de Supinski, Martin Schulz 0001	Efficiently exploring architectural design spaces via predictive modeling.	ASPLOS	2006	DBLP DOI BibTeX RDF	sensitivity studies, artificial neural networks, performance prediction, design space exploration
8	James Laudon	Performance/Watt: the new server focus.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
8	Norman P. Jouppi, Rakesh Kumar 0002, Dean M. Tullsen	Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05).	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
8	M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang 0001, David H. Albonesi	Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance.	IEEE PACT	2005	DBLP DOI BibTeX RDF
8	James A. Kahle	The Cell Processor Architecture.	MICRO	2005	DBLP DOI BibTeX RDF
8	Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou	ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing.	MICRO	2005	DBLP DOI BibTeX RDF
8	Meyrem Kirman, Nevin Kirman, José F. Martínez	Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors.	MICRO	2005	DBLP DOI BibTeX RDF
8	Ayodele Thomas, Kunle Olukotun	An Application Analysis Framework For Polymorphic Chip Multiprocessors.	IPDPS	2005	DBLP DOI BibTeX RDF
8	Valentina Salapura, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, Dong Chen 0005, Paul Coteus, Alan Gara, Mark Giampapa, Michael Gschwind, Manish Gupta 0002, Shawn Hall, Ruud A. Haring, Philip Heidelberger, Dirk Hoenicke, Gerard V. Kopcsay, Martin Ohmacht, Rick A. Rand, Todd Takken, Pavlos Vranas	Power and performance optimization at the system level.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	BlueGene/L, application performance analysis, application scaling in multiprocessor systems, power/performance efficient systems, power/performance tradeos in systems, chip multiprocessors, supercomputers
8	Ethan Schuchman, T. N. Vijaykumar	Rescue: A Microarchitecture for Testability and Defect Tolerance.	ISCA	2005	DBLP DOI BibTeX RDF
8	Mladen Nikitovic, Mats Brorsson	A Low Power Strategy for Future Mobile Terminals.	DATE	2004	DBLP DOI BibTeX RDF
8	Michael K. Chen, Kunle Olukotun	TEST: A Tracer for Extracting Speculative Thread.	CGO	2003	DBLP DOI BibTeX RDF
8	Peter Rundberg, Per Stenström	Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections.	IPDPS	2003	DBLP DOI BibTeX RDF
8	Chris R. Jesshope	Multi-threaded Microprocessors - Evolution or Revolution.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
8	Michael K. Chen, Kunle Olukotun	The Jrpm System for Dynamically Parallelizing Java Programs.	ISCA	2003	DBLP DOI BibTeX RDF
8	Gokhan Memik, William H. Mangione-Smith	Increasing power efficiency of multi-core network processors through data filtering.	CASES	2002	DBLP DOI BibTeX RDF	chip multiprocessors, network processors, data locality, remote procedure call, power reduction
8	Fredrik Warg, Per Stenström	Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms.	IEEE PACT	2001	DBLP DOI BibTeX RDF
8	José E. Moreira	Blue Gene: A Massively Parallel System.	International Conference on Computational Science (1)	2001	DBLP DOI BibTeX RDF
8	Lisa Wu 0001, Christopher T. Weaver, Todd M. Austin	CryptoManiac: a fast flexible architecture for secure communication.	ISCA	2001	DBLP DOI BibTeX RDF