Search results for "gate-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Chunhong Chen, Ran Xiao	A fast model for analysis and improvement of gate-level circuit reliability.	Integr.	2015	DBLP DOI BibTeX RDF
13	Sandip Ghosal, Debasis Mitra 0002, Subhasis Bhattacharjee	Certificate-based encoding of gate level description for secure transmission.	Int. J. Electron. Secur. Digit. Forensics	2015	DBLP DOI BibTeX RDF
13	Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa	A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2015	DBLP DOI BibTeX RDF
13	Zhao Wang, Xiao He, Carl Sechen	A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic.	Circuits Syst. Signal Process.	2015	DBLP DOI BibTeX RDF
13	Domenico Albano, Marco Lanuzza, Ramiro Taco, Felice Crupi	Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines.	Int. J. Circuit Theory Appl.	2015	DBLP DOI BibTeX RDF
13	Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas 0001, Letícia Maria Bolzani Pöhls	SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic.	DDECS	2015	DBLP DOI BibTeX RDF
13	Dongfang Li, Wenchao Liu 0003, Xuecheng Zou, Zhenglin Liu	Hardware IP Protection through Gate-Level Obfuscation.	CAD/Graphics	2015	DBLP DOI BibTeX RDF
13	Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Cyril Chevalier	An efficient hybrid power modeling approach for accurate gate-level power estimation.	ICM	2015	DBLP DOI BibTeX RDF
13	Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa	A score-based classification method for identifying hardware-trojans at gate-level netlists.	DATE	2015	DBLP BibTeX RDF
13	Burçin Çakir, Sharad Malik	Hardware Trojan detection for gate-level ICs using signal correlation based clustering.	DATE	2015	DBLP BibTeX RDF
13	Elsa J. Gonsiorowski, Justin M. LaPre, Christopher D. Carothers	Improving Accuracy and Performance Through Automatic Model Generation for Gate-Level Circuit PDES with Reverse Computation.	SIGSIM-PADS	2015	DBLP DOI BibTeX RDF
13	Jeremy Schlachter, Vincent Camus, Christian C. Enz, Krishna V. Palem	Automatic generation of inexact digital circuits by gate-level pruning.	ISCAS	2015	DBLP DOI BibTeX RDF
13	Xin Fang 0001, Pei Luo, Yunsi Fei, Miriam Leeser	Balance power leakage to fight against side-channel analysis at gate level in FPGAs.	ASAP	2015	DBLP DOI BibTeX RDF
13	Makoto Ikeda	Design and optimization of asynchronous circuits with gate-level pipelining.	ASICON	2015	DBLP DOI BibTeX RDF
13	Masato Tamura, Atsushi Ito, Makoto Ikeda	Optimal design on asynchronous system with gate-level pipelining.	ASICON	2015	DBLP DOI BibTeX RDF
13	Kai Chen, Young Hwan Kim	Current source model of combinational logic gates for accurate gate-level circuit analysis and timing analysis.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
13	Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi	Verification of gate-level arithmetic circuits by function extraction.	DAC	2015	DBLP DOI BibTeX RDF
13	Ran Xiao, Chunhong Chen	Gate-Level Circuit Reliability Analysis: A Survey.	VLSI Design	2014	DBLP DOI BibTeX RDF
13	Jinwook Kim, Young Hwan Kim	Hybrid Gate-Level Leakage Model for Monte Carlo Analysis on Multiple GPUs.	IEEE Access	2014	DBLP DOI BibTeX RDF
13	Jason Oberg, Sarah Meiklejohn, Timothy Sherwood, Ryan Kastner	Leveraging Gate-Level Properties to Identify Hardware Timing Channels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
13	Pasquale Corsonello, Marco Lanuzza, Stefania Perri	Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates.	Int. J. Circuit Theory Appl.	2014	DBLP DOI BibTeX RDF
13	Wei Hu 0008, Dejun Mu, Jason Oberg, Baolei Mao, Mohit Tiwari, Timothy Sherwood, Ryan Kastner	Gate-Level Information Flow Tracking for Security Lattices.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
13	Palkesh Jain, Bapana Pudi, Meghna Sreenivasan	Design-in-reliability: From library modeling and optimization to gate-level verification.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
13	Shlomo Greenberg, Joseph Rabinowicz, Ron Tsechanski, Eugene Paperno	Selective State Retention Power Gating Based on Gate-Level Analysis.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
13	Soongyu Kwon, Jong Kang Park, Jong Tae Kim	An approximated soft error analysis technique for gate-level designs.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
13	Juan Núñez 0002, Maria J. Avedillo, Hector J. Quintero	DOE based high-performance gate-level pipelines.	PATMOS	2014	DBLP DOI BibTeX RDF
13	Ghaith Bany Hamad, Syed Rafay Hasan, Otmane Aït Mohamed, Yvon Savaria	Modeling, analyzing, and abstracting single event transient propagation at gate level.	MWSCAS	2014	DBLP DOI BibTeX RDF
13	Tariq B. Ahmad, Maciej J. Ciesielski	Fast STA prediction-based gate-level timing simulation.	DATE	2014	DBLP DOI BibTeX RDF
13	Alexandru Amaricai, Sergiu Nimara, Oana Boncalo, Jiaoyan Chen, Emanuel M. Popovici	Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits.	DSD	2014	DBLP DOI BibTeX RDF
13	Raghuraman Balasubramanian, Karthikeyan Sankaralingam	Understanding the impact of gate-level physical reliability effects on whole program execution.	HPCA	2014	DBLP DOI BibTeX RDF
13	Marco Lanuzza, Ramiro Taco, Domenico Albano	Dynamic gate-level body biasing for subthreshold digital design.	LASCAS	2014	DBLP DOI BibTeX RDF
13	Shreepad A. Panth, Kambiz Samadi, Yang Du 0001, Sung Kyu Lim	Design and CAD methodologies for low power gate-level monolithic 3D ICs.	ISLPED	2014	DBLP DOI BibTeX RDF
13	Franck Courbon, Philippe Loubet-Moundi, Jacques J. A. Fournier, Assia Tria	Increasing the efficiency of laser fault injections using fast gate level reverse engineering.	HOST	2014	DBLP DOI BibTeX RDF
13	Michael Meixner, Tobias G. Noll	Limits of gate-level power estimation considering real delay effects and glitches.	ISSoC	2014	DBLP DOI BibTeX RDF
13	Andrew J. Leiserson, Mark E. Marson, Megan A. Wachs	Gate-Level Masking under a Path-Based Leakage Metric.	CHES	2014	DBLP DOI BibTeX RDF
13	Li Zhang, Chip-Hong Chang	Hardware Trojan detection with linear regression based gate-level characterization.	APCCAS	2014	DBLP DOI BibTeX RDF
13	Dean Sullivan, Jeff Biggers, Guidong Zhu, Shaojie Zhang, Yier Jin	FIGHT-Metric: Functional Identification of Gate-Level Hardware Trustworthiness.	DAC	2014	DBLP DOI BibTeX RDF
13	Ching-Lung Su, Tse-Min Chen, Kuo-Hsuan Wu	A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation.	VLSI Design	2013	DBLP DOI BibTeX RDF
13	Wei Hu 0008, Jason Oberg, Janet Barrientos, Dejun Mu, Ryan Kastner	Expanding Gate Level Information Flow Tracking for Multilevel Security.	IEEE Embed. Syst. Lett.	2013	DBLP DOI BibTeX RDF
13	Yu Jin, Zhe Du, Shinji Kimura	Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2013	DBLP DOI BibTeX RDF
13	Angshuman Chakraborty, Sambhu Nath Pradhan	Gate level leakage minimisation at 90 nm technology.	Int. J. Comput. Aided Eng. Technol.	2013	DBLP DOI BibTeX RDF
13	Albert Kwon, Udit Dhawan, Jonathan M. Smith, Thomas F. Knight Jr., André DeHon	Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security.	CCS	2013	DBLP DOI BibTeX RDF
13	Tariq Bashir Ahmad, Maciej J. Ciesielski	An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads.	MTV	2013	DBLP DOI BibTeX RDF
13	Kosuke Oshima, Takeshi Matsumoto, Masahiro Fujita	A debugging method for gate level circuit designs by introducing programmability.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
13	Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla	GLA: gate-level abstraction revisited.	DATE	2013	DBLP DOI BibTeX RDF
13	Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard	A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits.	DATE	2013	DBLP DOI BibTeX RDF
13	Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada	Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
13	Yu Jin, Shinji Kimura	On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
13	Wei Hu 0008, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, Ryan Kastner	On the Complexity of Generating Gate Level Information Flow Tracking Logic.	IEEE Trans. Inf. Forensics Secur.	2012	DBLP DOI BibTeX RDF
13	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu	Simulated fault injection methodology for gate-level quantum circuit reliability assessment.	Simul. Model. Pract. Theory	2012	DBLP DOI BibTeX RDF
13	Andrea Pellegrini, Robert Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita V. Adve, Todd M. Austin, Valeria Bertacco	CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions.	DATE	2012	DBLP DOI BibTeX RDF
13	Sandip Ghosal, Debasis Mitra 0002	Secure transmission of gate level description.	RAIT	2012	DBLP DOI BibTeX RDF
13	Nicolas Chevillon, Morgan Madec, Christophe Lallement	Gate-level modeling for CMOS circuit simulation with ultimate FinFETs.	NANOARCH	2012	DBLP DOI BibTeX RDF
13	Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada	Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation.	COOL Chips	2012	DBLP DOI BibTeX RDF
13	Shohei Ono, Takeshi Matsumoto, Masahiro Fujita	Automatic assertion extraction in gate-level simulation using GPGPUs.	ICCD	2012	DBLP DOI BibTeX RDF
13	Yiqiong Shi, Bah-Hwee Gwee, Ye Ren, Thet Khaing Phone, Chan Wai Ting	Extracting functional modules from flattened gate-level netlist.	ISCIT	2012	DBLP DOI BibTeX RDF
13	Mu-Shun Matt Lee, Yi-Chu Liu, Wan-Rong Wu, Chien-Nan Jimmy Liu	Peak wake-up current estimation at gate-level with standard library information.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
13	Kai-Hui Chang, Chris Browy	Improving gate-level simulation accuracy when unknowns exist.	DAC	2012	DBLP DOI BibTeX RDF
13	Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada	A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
13	Wei Hu 0008, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, Ryan Kastner	Theoretical Fundamentals of Gate Level Information Flow Tracking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
13	Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco	Gate-Level Simulation with GPU Computing.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
13	Dusung Kim, Maciej J. Ciesielski, Seiyang Yang	A new distributed event-driven gate-level HDL simulation by accurate prediction.	DATE	2011	DBLP DOI BibTeX RDF
13	Michal Rumplík, Josef Strnadel	On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits.	DSD	2011	DBLP DOI BibTeX RDF
13	Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada	A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS.	ASP-DAC	2011	DBLP DOI BibTeX RDF
13	Moslem Didehban, Ario Sadafi, Sajjad Salehi, Mohammad Bagher Chami	A Gate Level Analysis of Transient Faults Effects on Dual-Core Chip-Multi Processors.	ARES	2011	DBLP DOI BibTeX RDF
13	Levent Aksoy, Eduardo Costa 0001, Paulo F. Flores, José Monteiro 0001	Optimization of gate-level area in high throughput Multiple Constant Multiplications.	ECCTD	2011	DBLP DOI BibTeX RDF
13	Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada	Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system.	ICECS	2011	DBLP DOI BibTeX RDF
13	Sidinei Ghissoni, Eduardo Costa 0001, José Monteiro 0001, Ricardo Reis 0001	Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization.	ICECS	2011	DBLP DOI BibTeX RDF
13	Ghaith Bany Hamad, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria	SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level.	ICECS	2011	DBLP DOI BibTeX RDF
13	Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada	Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA.	ISLPED	2011	DBLP BibTeX RDF
13	Levent Aksoy, Cristiano Lazzari, Eduardo Costa 0001, Paulo F. Flores, José Monteiro 0001	Optimization of area in digit-serial Multiple Constant Multiplications at gate-level.	ISCAS	2011	DBLP DOI BibTeX RDF
13	Miroslav N. Velev, Ping Gao 0002	CNF encodings of cardinality in formal methods for robustness checking of gate-level circuits.	ISCAS	2011	DBLP DOI BibTeX RDF
13	Massoud Mokhtarpour Ghahroodi, Mark Zwolinski, Emre Özer 0001	Radiation hardening by design: A novel gate level approach.	AHS	2011	DBLP DOI BibTeX RDF
13	Tao Lin, Sheqin Dong, Song Chen 0001, Yuchun Ma, Ou He, Satoshi Goto	Novel and efficient min cut based voltage assignment in gate level.	ISQED	2011	DBLP DOI BibTeX RDF
13	Jie Xiao, Jianhui Jiang, Xuguang Zhu, Chengtian Ouyang	A Method of Gate-Level Circuit Reliability Estimation Based on Iterative PTM Model.	PRDC	2011	DBLP DOI BibTeX RDF
13	Mohit Tiwari, Xun Li 0001, Hassan M. G. Wassel, Bita Mazloom, Shashidhar Mysore, Frederic T. Chong, Timothy Sherwood	Gate-Level Information-Flow Tracking for Secure Architectures.	IEEE Micro	2010	DBLP DOI BibTeX RDF	covert channels, noninterference, high-assurance systems, timing channels, information-flow tracking
13	Ali Namazi, Mehrdad Nourani	Gate-Level Redundancy: A New Design-for-Reliability Paradigm for Nanotechnologies.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
13	Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara	A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification.	IEICE Trans. Inf. Syst.	2010	DBLP DOI BibTeX RDF
13	Sina Meraji, Wei Zhang 0034, Carl Tropper	On the Scalability and Dynamic Load-Balancing of Optimistic Gate Level Simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
13	Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann	Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene).	it Inf. Technol.	2010	DBLP DOI BibTeX RDF
13	Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara	A synthesis method to propagate false path information from RTL to gate level.	DDECS	2010	DBLP DOI BibTeX RDF
13	Levent Aksoy, Eduardo Costa 0001, Paulo F. Flores, José Monteiro 0001	Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications.	DSD	2010	DBLP DOI BibTeX RDF
13	Mu-Shun Matt Lee, Kuo-Sheng Lai, Chia-Ling Hsu, Chien-Nan Jimmy Liu	Dynamic IR drop estimation at gate level with standard library information.	ISCAS	2010	DBLP DOI BibTeX RDF
13	Yiqiong Shi, Chan Wai Ting, Bah-Hwee Gwee, Ye Ren	A highly efficient method for extracting FSMs from flattened gate-level netlist.	ISCAS	2010	DBLP DOI BibTeX RDF
13	Amirali Ghofrani, Fatemeh Javaheri, Saeed Safari, Zainalabedin Navabi	Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization.	SoC	2010	DBLP DOI BibTeX RDF
13	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu	An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.	IPSJ Trans. Syst. LSI Des. Methodol.	2009	DBLP DOI BibTeX RDF
13	Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco	GCS: High-performance gate-level simulation with GPGPUs.	DATE	2009	DBLP DOI BibTeX RDF
13	Michal Bidlo, Zdenek Vasícek	Investigating gate-level evolutionary development of combinational multipliers using enhanced cellular automata-based model.	IEEE Congress on Evolutionary Computation	2009	DBLP DOI BibTeX RDF
13	Zbysek Gajda, Lukás Sekanina	Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming.	IEEE Congress on Evolutionary Computation	2009	DBLP DOI BibTeX RDF
13	Xin Wang, Alireza Kasnavi, Harold Levy	A general piece-wise nonlinear library modeling format and size reduction technique for gate-level timing, SI, power, and variation analysis.	ISQED	2009	DBLP DOI BibTeX RDF
13	B. Chung, J. B. Kuo	Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application.	Integr.	2008	DBLP DOI BibTeX RDF
13	Yukihide Kohira, Atsushi Takahashi 0001	A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
13	Jong Kang Park, Jong Tae Kim	A soft error mitigation technique for constrained gate-level designs.	IEICE Electron. Express	2008	DBLP DOI BibTeX RDF
13	Lukás Starecek, Lukás Sekanina, Zdenek Kotásek	Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration.	DDECS	2008	DBLP DOI BibTeX RDF
13	Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang	Temporal parallel gate-level timing simulation.	HLDVT	2008	DBLP DOI BibTeX RDF
13	Michal Bidlo, Zdenek Vasícek	Gate-Level Evolutionary Development Using Cellular Automata.	AHS	2008	DBLP DOI BibTeX RDF
13	Igor Keller, King Ho Tam, Vinod Kariat	Challenges in gate level modeling for delay and SI at 65nm and below.	DAC	2008	DBLP DOI BibTeX RDF	delay calculation, gate characterization, gate modeling
13	Jun Cheng Chi, Hung Hsie Lee, Sung Han Tsai, Mely Chen Chi	Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
13	Yukihide Kohira, Atsushi Takahashi 0001	Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
13	Mark B. Josephs	Gate-level modelling and verification of asynchronous circuits using CSPM and FDR.	ASYNC	2007	DBLP DOI BibTeX RDF