Search results for "loop"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Marianne De Michiel, Armelle Bonenfant, Hugues Cassé, Pascal Sainrat	Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation.	RTCSA	2008	DBLP DOI BibTeX RDF
22	Russell Meyers, Zhiyuan Li 0001	ASYNC Loop Constructs for Relaxed Synchronization.	LCPC	2008	DBLP DOI BibTeX RDF
22	Nima Maghari, Un-Ku Moon	Multi-loop efficient sturdy MASH delta-sigma modulators.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Tara Julia Hamilton, Craig T. Jin, André van Schaik, Jonathan Tapson	A 2-D silicon cochlea with an improved automatic quality factor control-loop.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Xiaolong Yuan, Nianxiong Tan, Svante Signell	On low power design of feedforward continuous-time sigma delta modulators with excess loop delay.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Agostino Martinelli, Roland Siegwart	Exploiting the Information at the Loop Closure in SLAM.	ICRA	2007	DBLP DOI BibTeX RDF
22	Srikanth Kurra, Neeraj Kumar Singh 0004, Preeti Ranjan Panda	The impact of loop unrolling on controller delay in high level synthesis.	DATE	2007	DBLP DOI BibTeX RDF
22	Sofiane Naci	Optimizing Inter-Nest Data Locality Using Loop Splitting and Reordering.	IPDPS	2007	DBLP DOI BibTeX RDF
22	Yong Dou, Jinhui Xu 0002, Guiming Wu	The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.	ARC	2007	DBLP DOI BibTeX RDF
22	Ali Mili 0001	A Refinement Based Framework for Computing Loop Behavior.	SEW	2007	DBLP DOI BibTeX RDF
22	Hovhannes A. Harutyunyan, Edward Maraachlian	Broadcasting in Optimal Bipartite Double Loop Graphs.	IV	2006	DBLP DOI BibTeX RDF
22	Betul Buyukkurt, Zhi Guo, Walid A. Najjar	Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
22	Jinhui Xu 0002, Guiming Wu, Yong Dou, Yazhuo Dong	Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
22	Yong Shim, Youngkwon Jo, Soo Hwan Kim, Suki Kim, Kwanjun Cho	A register controlled delay locked loop using a TDC and a new fine delay line scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Lei Shen, Fangni Chen, Shiju Li	Performance of Coherent Delay Lock Loop in the Presence of CW Interference and Additive Noise.	IMSCCS (1)	2006	DBLP DOI BibTeX RDF
22	Yuhua Cheng, Xiaobo Wu, Xiaolang Yan	Translinear Loop Principle and Identification of the Translinear Loops.	APCCAS	2006	DBLP DOI BibTeX RDF
22	Hari Rangarajan, J. J. Garcia-Luna-Aceves	Efficient Use of Route Requests for Loop-Free On-demand Routing in Ad Hoc Networks.	NETWORKING	2005	DBLP DOI BibTeX RDF
22	Gary B. Parker, Ramona Georgescu	Evolution of multi-loop controllers for fixed morphology with a cyclic genetic algorithm.	GECCO	2005	DBLP DOI BibTeX RDF	learning, control, code generation, evolutionary robotics
22	Alban Douillet, Guang R. Gao	Register Pressure in Software-Pipelined Loop Nests: Fast Computation and Impact on Architecture Design.	LCPC	2005	DBLP DOI BibTeX RDF
22	You Zheng, Carlos E. Saavedra	A BPSK demodulator circuit using an anti-parallel synchronization loop.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
22	Jidong Long, Daniel G. Schwartz, Sara Stoecklin, Mahesh K. Patel	Application of Loop Reduction to Learning Program Behaviors for Anomaly Detection.	ITCC (1)	2005	DBLP DOI BibTeX RDF
22	Sungho Jo, Steve G. Massaquoi	A model of cerebellum stabilized and scheduled hybrid long-loop control of upright balance.	Biol. Cybern.	2004	DBLP DOI BibTeX RDF
22	Luca Faes, Alberto Porta, R. Cucino, Sergio Cerutti, Renzo Antolini, Giandomenico Nollo	Causal transfer function analysis to describe closed loop interactions between cardiovascular and cardiorespiratory variability signals.	Biol. Cybern.	2004	DBLP DOI BibTeX RDF	Linear transfer function, Cardiovascular control, Coherence
22	Wei Zhang 0002, Bramha Allu	Loop-based leakage control for branch predictors.	CASES	2004	DBLP DOI BibTeX RDF	compiler, branch prediction, leakage energy
22	Hassan Aboushady, Marie-Minerve Louërat	Loop delay compensation in bandpass continuous-time Sigma Delta modulators without additional feedback coefficients.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
22	Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo	A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
22	Shigeo Doi, Masayuki Yamamura	An Experimental Analysis of Loop-Free Algorithms for Scale-Free Networks.	ANTS Workshop	2004	DBLP DOI BibTeX RDF
22	José Ignacio Gómez, Paul Marchal, Sven Verdoolaege, Luis Piñuel, Francky Catthoor	Optimizing the Memory Bandwidth with Loop Morphing.	ASAP	2004	DBLP DOI BibTeX RDF
22	Gang-Ryung Uh	Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer.	SCOPES	2003	DBLP DOI BibTeX RDF
22	Vasu Jolly, Shahram Latifi	On Loop Control In Multiprotocol Label Switching.	ITCC	2003	DBLP DOI BibTeX RDF	Label space, Label switched path and LSR, IP, MPLS
22	Taewoong Jeon, Sunghwan Roh, Hyonwoo Seung, Sungyoung Lee	The Design and Implementation of an Object-Oriented Process Control Loop Framework.	AISA	2002	DBLP DOI BibTeX RDF
22	Arun Rao, William McIntyre, J. Parry, Un-Ku Moon, Gabor C. Temes	Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
22	Frank Hannig, Jürgen Teich	Energy estimation of nested loop programs.	SPAA	2002	DBLP DOI BibTeX RDF	hardware mapping, low power, processor arrays
22	Christo Frank, B. S. Manoj 0001, C. Siva Ram Murthy	Throughput Enhanced Wireless in Local Loop (TWiLL) - The Architecture, Protocols and Pricing Schemes.	LCN	2002	DBLP DOI BibTeX RDF
22	Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karaköy	An energy saving strategy based on adaptive loop parallelization.	DAC	2002	DBLP DOI BibTeX RDF	energy consumption, multiprocessing, adaptive parallelization
22	Hosam Khalil, Kenneth Rose, Shankar L. Regunathan	The asymptotic closed-loop approach to predictive vector quantizer design with application in video coding.	IEEE Trans. Image Process.	2001	DBLP DOI BibTeX RDF
22	Daniel Cociorva, J. W. Wilkins, Chi-Chung Lam, Gerald Baumgartner, J. Ramanujam, P. Sadayappan	Loop optimization for a class of memory-constrained computations.	ICS	2001	DBLP DOI BibTeX RDF
22	Ching-Chi Chang, Chien-Chih Lin, Muh-Tian Shiue, Chorng-Kuang Wang	A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
22	Alan L. Yuille	A Double-Loop Algorithm to Minimize the Bethe Free Energy.	EMMCVPR	2001	DBLP DOI BibTeX RDF
22	Kiran Bondalapati, Viktor K. Prasanna	Loop Pipelining and Optimization for Run Time Reconfiguration.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
22	Michael F. P. O'Boyle, Peter M. W. Knijnenburg	Efficient Parallelization Using Combined Loop and Data Transformations.	IEEE PACT	1999	DBLP DOI BibTeX RDF
22	Kainam Thomas Wong	A novel closed-form azimuth/elevation angle and polarization estimation technique using only electric dipole triads or only magnetic loop triads with arbitrary unknown spacings.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
22	Sven-Bodo Scholz	A Case Study: Effects of WITH-Loop-Folding on the NAS Benchmark MG in SAC.	IFL	1998	DBLP DOI BibTeX RDF
22	J. Mark Bull	Feedback Guided Dynamic Loop Scheduling: Algorithms and Experiments.	Euro-Par	1998	DBLP DOI BibTeX RDF
22	Maurice Herlihy, Sergio Rajsbaum	A Wait-Free Classification of Loop Agreement Tasks.	DISC	1998	DBLP DOI BibTeX RDF
22	Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee	A Loop Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality.	LCPC	1998	DBLP DOI BibTeX RDF
22	Zbigniew Chamski, Michael F. P. O'Boyle	Practical Loop Generation.	HICSS (1)	1996	DBLP DOI BibTeX RDF
22	Madalene Spezialetti, Rajiv Gupta 0001	Loop Monotonic Statements.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	Access anomalies (data races), run-time dependence checking, static analysis, array bound checking, induction variables
22	Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski	A transformation-based method for loop folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
22	Qi Ning, Guang R. Gao	Minimizing Loop Storage Allocation for An Argument-Fetching Dataflow Architecture Model.	PARLE	1992	DBLP DOI BibTeX RDF
22	Guang R. Gao, Yue-Bong Wong, Qi Ning	A timed Petri-net model for fine-grain loop scheduling.	CASCON	1991	DBLP BibTeX RDF
22	François Bodin, François Charot	Loop optimization for horizontal microcoded machines.	ICS	1990	DBLP DOI BibTeX RDF
22	Diantong Liu, Wolfgang K. Giloi	A loop optimization technique based on scheduling table.	MICRO	1989	DBLP DOI BibTeX RDF
22	James C. Dehnert, Peter Y.-T. Hsu, Joseph P. Bratt	Overlapped Loop Support in the Cydra 5.	ASPLOS	1989	DBLP DOI BibTeX RDF	Cydra 5
22	Tao Liu, Haibo Lin, Tong Chen 0001, Kevin O'Brien, Ling Shao 0002	DBDB: optimizing DMATransfer for the cell be architecture.	ICS	2009	DBLP DOI BibTeX RDF	loop blocking, local memory, multi-core system
22	Long-Sheng Li, Gwo-Chuan Lee, Jhu-Shyuan Mei, Cing-Long Chen	The Hierarchical Path-Selection Scheme Based on Multihoming NEMO.	ICA3PP	2009	DBLP DOI BibTeX RDF	Loop prevention, Load balance, Network Mobility, Multihoming
22	Keith D. Cooper, Jason Eckhardt, Ken Kennedy	Redundancy elimination revisited.	PACT	2008	DBLP DOI BibTeX RDF	expression optimization, reassociation, scalar replacement, loop optimization, redundancy elimination
22	Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke	Modulo scheduling for highly customized datapaths to increase hardware reusability.	CGO	2008	DBLP DOI BibTeX RDF	programmable asic, modulo scheduling, loop accelerator
22	Louis-Noël Pouchet, Cédric Bastoul, Albert Cohen 0001, John Cavazos	Iterative optimization in the polyhedral model: part ii, multidimensional time.	PLDI	2008	DBLP DOI BibTeX RDF	genetic algorithm, loop transformation, iterative compilation, affine scheduling
22	Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras	Low power microarchitecture with instruction reuse.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	loop reusing technique, reorder buffer optimization, superscalar processor, power reduction
22	Ward Douglas Maurer	Using mathematics to improve ada compiled code, part 2: the proof.	SIGAda	2007	DBLP DOI BibTeX RDF	ada compilers, base registers, code improvement, display method, loop trees, nested procedures
22	Johnnie Birch, Robert A. van Engelen, Kyle A. Gallivan, Yixin Shou	An empirical evaluation of chains of recurrences for array dependence testing.	PACT	2006	DBLP DOI BibTeX RDF	chains of recurrences, dependence testing, loop optimization
22	Jun Xia, Li Luo, Xuejun Yang	A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	compiler optimizations, integer linear programming, loop transformations, data transformations, Cache locality, memory layouts
22	Bruno Harbulot, John R. Gurd	A join point for loops in AspectJ.	AOSD	2006	DBLP DOI BibTeX RDF	loop join point, AspectJ
22	Khaled F. Hussain, Ghada S. Moussa	Laser intensity vehicle classification system based on random neural network.	ACM Southeast Regional Conference (1)	2005	DBLP DOI BibTeX RDF	loop detectors, image processing, range sensor, vehicle classification
22	Dongkeun Kim, Donald Yeung	A study of source-level compiler algorithms for automatic construction of pre-execution code.	ACM Trans. Comput. Syst.	2004	DBLP DOI BibTeX RDF	pre-execution, prefetch conversion, speculative loop parallelization, multithreading, program slicing, Data prefetching, memory-level parallelism
22	Weng-Long Chang, Jih-Woei Huang, Chih-Ping Chu	Using Elementary Linear Algebra to Solve Data Alignment for Arrays with Linear or Quadratic References.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	communication-free alignment, load balancing, parallel computing, Parallel compiler, loop optimization, data dependence analysis
22	Zhiyuan Li 0001, Yonghong Song	Automatic tiling of iterative stencil loops.	ACM Trans. Program. Lang. Syst.	2004	DBLP DOI BibTeX RDF	Caches, optimizing compilers, loop transformations
22	Mahmut T. Kandemir	LODS: locality-oriented dynamic scheduling for on-chip multiprocessors.	DAC	2004	DBLP DOI BibTeX RDF	embedded system, parallelization, data locality, loop scheduling
22	Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno	Reducing instruction fetch energy with backwards branch control information and buffering.	ISLPED	2003	DBLP DOI BibTeX RDF	loop buffer, low-power, instruction fetch
22	Volodymyr Beletskyy, R. Drazkowski, Marcin Liersz	An Approach to Parallelizing Non-Uniform Loops with the Omega Calculator.	PARELEC	2002	DBLP DOI BibTeX RDF	non-uniform dependences, Presburger formulas, loop parallelization
22	Smita Bakshi, Daniel Gajski	Performance-constrained hierarchical pipelining for behaviors, loops, and operations.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	DSP (digital signal processing) systems, hierarchical pipelining, pipelined systems, scheduling, component selection, loop pipelining
22	Dean Batten, Sanjay Jinturkar, C. John Glossner, Michael J. Schulte, Paul D'Arcy	A New Approach to DSP Intrinsic Functions.	HICSS	2000	DBLP DOI BibTeX RDF	Speech coders, intrinsic functions, profile-directed function inlining, performance analysis, instruction-level parallelism, software pipelining, speedup, modulo scheduling, loop optimization, code growth
22	Yijun Yu, Erik H. D'Hollander	Partitioning Loops with Variable Dependence Distances.	ICPP	2000	DBLP DOI BibTeX RDF	dependence equation, pseudo distance matrix, uni-modular transformation, iteration space partitioning 1, loop parallelization, distance vector
22	Val Donaldson, Jeanne Ferrante	Determining Asynchronous Acyclic Pipeline Execution Times.	IPPS	1996	DBLP DOI BibTeX RDF	asynchronous pipelining, parallel execution time, loop parallelism, task graph scheduling, pipeline scheduling
22	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor	A comparative evaluation of software techniques to hide memory latency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
22	Zbigniew Chamski	Beyond convexity: scanning 'non-convex polyhedra'.	HICSS (2)	1995	DBLP DOI BibTeX RDF	nonconvex polyhedra, point enumeration, algebraically-specified domain, algorithmic problem, scientific program transformation, scanning algorithms, runtime overhead, regularly nonconvex domains, arbitrary unions, nested loop sequences, parallel algorithms, parallel programming, computational geometry, convexity, program interpreters, program control structures, convex polyhedra
22	Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja	Incorporating testability considerations in high-level synthesis.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability
21	Vincent Lagareste, Franck Badets, Pierre Melchior, Jean-Baptiste Bégueret, Yann Deval, Alain Oustaloup, Didier Belot	Phase locked loop robustness improvement using non integer order loop filter.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Didier Keymeulen, Michael I. Ferguson, Wolfgang Fink, Boris Oks, Chris Peay, Richard Terrile, Yen Cheng, Dennis Kim, Eric W. MacDonald, David Foor	Hardware Platforms for MEMS Gyroscope Tuning Based on Evolutionary Computation Using Open-Loop and Closed-Loop Frequency Response.	ICES	2005	DBLP DOI BibTeX RDF
21	Huabin Chen, Fenglin Lv 0001, Tao Lin 0011, Shanben Chen	Closed-Loop Control of Robotic Arc Welding System with Full-penetration Monitoring.	J. Intell. Robotic Syst.	2009	DBLP DOI BibTeX RDF	Feed forward compensation, Robotic arc welding, Penetration control, Closed-loop
21	Dongwon Jung, Jayant Ratti, Panagiotis Tsiotras	Real-time Implementation and Validation of a New Hierarchical Path Planning Scheme of UAVs via Hardware-in-the-Loop Simulation.	J. Intell. Robotic Syst.	2009	DBLP DOI BibTeX RDF	Path planning and control, Hardware-in-the-loop simulation (HILS), UAV
21	Meikang Qiu, Meiqin Liu, Hao Li, Hung-Chung Huang, Wenyuan Li 0006, Jiande Wu	Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Optimization, Real-time, Multi-core, Assignment, Loop scheduling
21	José Luís Calvo-Rolle, Héctor Alaiz-Moretón, Javier Alfonso-Cendón, Ángel Alonso-Álvarez, Ramón Ferreiro García	Development of a Conceptual Model for a Knowledge-Based System for the Design of Closed-Loop PID Controllers.	IDEAL	2009	DBLP DOI BibTeX RDF	closed-loop adjustment, expert system, Knowledge engineering, ruled-based system, PID
21	Tameesh Suri, Aneesh Aggarwal	Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	data value prediction, dynamic reconfiguration, loop level parallelism
21	Marcelo Panaro de Moraes Zamith, Esteban Walter Gonzalez Clua, Aura Conci, Anselmo Antunes Montenegro, Regina Leal-Toledo, Paulo A. Pagliosa, Luis Valente, Bruno Feijó	A game loop architecture for the GPU used as a math coprocessor in real-time applications.	Comput. Entertain.	2008	DBLP DOI BibTeX RDF	Game loop, real-time physics, GPGPU
21	Calin Glitia, Pierre Boulet	High Level Loop Transformations for Systematic Signal Processing Embedded Applications.	SAMOS	2008	DBLP DOI BibTeX RDF	Multidimensional Dataflow, optimizations, loop transformations
21	Diego R. Llanos Ferraris, David Orden, Belén Palop	Just-In-Time Scheduling for Loop-based Speculative Parallelization.	PDP	2008	DBLP DOI BibTeX RDF	loop-based speculation, scheduling, speculative multithreading, Speculative parallelization
21	Kristina Höök	Affective Loop Experiences - What Are They?	PERSUASIVE	2008	DBLP DOI BibTeX RDF	affective loop, bodily interfaces, persuasion, affective interaction
21	Girish Venkataramani, Seth Copen Goldstein	Slack analysis in the system design loop.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	slack analysis, system design loop, timing update
21	Jingjin Shen, Chenggang Li, Hongtao Wu	A Research on Dynamics of a Hexapod with Closed-Loop Legs.	ICIRA (1)	2008	DBLP DOI BibTeX RDF	hexapod, AB algorithm, Newton-Euler MBDA, dynamic analysis, closed-loop
21	Rui Pereira	Loop-R: real-time video interface.	Advances in Computer Entertainment Technology	2008	DBLP DOI BibTeX RDF	NIME, live-visuals, real-time, interface, video, loop
21	Jisheng Zhao, Matthew Horsnell, Mikel Luján, Ian Rogers, Chris C. Kirkham, Ian Watson	Adaptive Loop Tiling for a Multi-cluster CMP.	ICA3PP	2008	DBLP DOI BibTeX RDF	Multi-Cluster CMP, Automatic Parallelization, Loop Tiling, Feedback-Directed Optimization
21	Jiri Haze, Radimir Vrba, Roman Prokop	Design of Phase Locked-Loop for Very Slow Sine-Wave Signals.	ICONS	2008	DBLP DOI BibTeX RDF	sine wave signal, phase locked-loop
21	Meikang Qiu, Jiande Wu	Energy saving for memory with loop scheduling and prefetching.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	multi-module memory, probability, partition, low power design, prefetching, loop scheduling
21	Carine Neus, Wim Foubert, Leo Van Biesen	Loop Identification and Capacity Estimation of Digital Subscriber Lines with Single Ended Line Testing.	AccessNets	2008	DBLP DOI BibTeX RDF	Digital Subscriber Line (DSL), Single Ended Line Testing (SELT), transfer function estimation, loop qualification, channel capacity
21	Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel	A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Automatic layout generation, Transient fault injection, Phase-locked loop
21	J. Manuel Cano Izquierdo, Julio Ibarrola, Miguel Almonacid	Performance Monitoring of Closed-Loop Controlled Systems Using dFasArt.	IWINAC (2)	2007	DBLP DOI BibTeX RDF	dFasArt, closed-loop systems, temporal analysis, neuro-fuzzy
21	Chenfeng Zhang, Vamsi K. Vijapurapu, Anurag K. Srivastava 0001, Noel N. Schulz, Jimena L. Bastos, Rudi Wierckx	Hardware-in-the-loop simulation of distance relay using RTDS.	SCSC	2007	DBLP BibTeX RDF	SEL distance relay, power system protection, real time simulation, hardware-in-the-loop, RTDS
21	Fabian M. Uriarte, Karen L. Butler-Purry	A partitioning approach for the parallel simulation of ungrounded shipboard power systems using Kron's diakoptics and loop analysis.	SCSC	2007	DBLP BibTeX RDF	Kron, diakoptics, shipboard, ungrounded, simulation, cluster, parallel, partitioning, power, systems, PC, loop, transient