Search results for "reconfigurable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Marcelo Götz, Achim Rettberg, Carlos Eduardo Pereira	A Run-Time Partitioning Algorithm for RTOS on Reconfigurable Hardware.	EUC	2005	DBLP DOI BibTeX RDF
26	Sacki Agelis, Magnus Jonsson	Reconfigurable Optical Interconnection System Supporting Concurrent Application-Specific Parallel Computing.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
26	Stéphane Chevobbe, Nicolas Ventroux, Frédéric Blanc 0001, Thierry Collette	RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems.	SAMOS	2004	DBLP DOI BibTeX RDF
26	Michael Rubenstein, Kenneth Payne, Peter M. Will, Wei-Min Shen	Docking Among Independent and Autonomous CONRO Self-reconfigurable Robots.	ICRA	2004	DBLP DOI BibTeX RDF
26	Kostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis 0001	Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.	PATMOS	2004	DBLP DOI BibTeX RDF
26	Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis	A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms.	DATE	2004	DBLP DOI BibTeX RDF
26	Sami Khawam, Sajid Baloch, Arjun Pai, Imran Ahmed 0001, Nizamettin Aydin, Tughrul Arslan, Fred Westall	Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays.	DATE	2004	DBLP DOI BibTeX RDF
26	Iván González, Javier Sanchez-Pastor, Jorge L. Hernandez-Ardieta, Francisco J. Gomez-Arribas, Javier Martínez	Using Reconfigurable Hardware Through Web Services in Distributed Applications.	FPL	2004	DBLP DOI BibTeX RDF
26	Renqiu Huang, Manish Handa, Ranga Vemuri	Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
26	Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato	FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.	FPL	2004	DBLP DOI BibTeX RDF
26	Minoru Watanabe, Fuminori Kobayashi	A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.	FPL	2004	DBLP DOI BibTeX RDF
26	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor.	FCCM	2004	DBLP DOI BibTeX RDF
26	André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda 0007, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton	Design Patterns for Reconfigurable Computing.	FCCM	2004	DBLP DOI BibTeX RDF
26	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing.	ASAP	2004	DBLP DOI BibTeX RDF
26	Jürgen Helmschmidt, Eberhard Schüler, Prashant Rao, Sergio Rossi, Serge di Matteo, Rainer Bonitz	Reconfigurable Signal Processing in Wireless Terminals.	DATE	2003	DBLP DOI BibTeX RDF
26	Kees A. Vissers	Parallel Processing Architectures for Reconfigurable Systems.	DATE	2003	DBLP DOI BibTeX RDF
26	Théodore Marescaux, Jean-Yves Mignolet, T. Andrei Bartic, W. Moffat, Diederik Verkest, Serge Vernalde, Rudy Lauwereins	Networks on Chip as Hardware Components of an OS for Reconfigurable Systems.	FPL	2003	DBLP DOI BibTeX RDF
26	Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo	Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device.	FPL	2003	DBLP DOI BibTeX RDF
26	Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic.	SBCCI	2003	DBLP DOI BibTeX RDF
26	J. L. Silva, R. M. Costa, G. H. R. Jorge	RtrASSoc - An Adaptable Superscalar Reconfigurable System-On-Chip.	IWSOC	2003	DBLP DOI BibTeX RDF
26	Katherine Compton, Zhiyuan Li 0008, James Cooley, Stephen Knol, Scott Hauck	Configuration relocation and defragmentation for run-time reconfigurable computing.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
26	Jürgen Teich, Markus Köster	(Self-)reconfigurable Finite State Machines: Theory and Implementation.	DATE	2002	DBLP DOI BibTeX RDF
26	Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek	Improving Code Efficiency for Reconfigurable VLIW Processors.	IPDPS	2002	DBLP DOI BibTeX RDF
26	Mihai Budiu, Mahim Mishra, Ashwin R. Bharambe, Seth Copen Goldstein	Peer-to-Peer Hardware-Software Interfaces for Reconfigurable Fabrics.	FCCM	2002	DBLP DOI BibTeX RDF
26	Satnam Singh	Interface specification for reconfigurable components.	ICCAD	2002	DBLP DOI BibTeX RDF
26	Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek	Prototyping Framework for Reconfigurable Processors.	FPL	2001	DBLP DOI BibTeX RDF
26	Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins	CRISP: A Template for Reconfigurable Instruction Set Processors.	FPL	2001	DBLP DOI BibTeX RDF
26	Neil W. Bergmann, Anwar S. Dawood	Adaptive Interfacing with Reconfigurable Computers.	ACSAC	2001	DBLP DOI BibTeX RDF
26	Huesung Kim, Arun K. Somani, Akhilesh Tyagi	A reconfigurable multi-function computing cache architecture.	FPGA	2000	DBLP DOI BibTeX RDF
26	Martyn Edwards, Peter Green 0001	An Object Oriented Design Method for Reconfigurable Computing Systems.	DATE	2000	DBLP DOI BibTeX RDF
26	John Jing-Fu Jenq, Dajin Wang	Parallel Computation of Configuration Space on Reconfigurable Mesh with Faults.	ICPP Workshops	2000	DBLP DOI BibTeX RDF
26	Masaru Fukushi, Susumu Horiguchi	Self-Reconfigurable Mesh Array System on FPGA.	DFT	2000	DBLP DOI BibTeX RDF
26	Jeffrey Hammes, Bruce A. Draper, A. P. Wim Böhm	Sassy: A Language and Optimizing Compiler for Image Processing on Reconfigurable Computing Systems.	ICVS	1999	DBLP DOI BibTeX RDF
26	Lizy Kurian John, E. John	A dynamically reconfigurable interconnect for array processors.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
26	Scott Hauck	Configuration Prefetch for Single Context Reconfigurable Coprocessors.	FPGA	1998	DBLP DOI BibTeX RDF
26	Gordon Charles McGregor, David Robinson, Patrick Lysaght	A Hardwar/Software Co-design Environment for Reconfigurable Logic Systems.	FPL	1998	DBLP DOI BibTeX RDF
26	Kiran Bondalapati, Viktor K. Prasanna	Mapping Loops onto Reconfigurable Architectures.	FPL	1998	DBLP DOI BibTeX RDF
26	Timothy J. Callahan, John Wawrzynek	Instruction-Level Parallelism for Reconfigurable Computing.	FPL	1998	DBLP DOI BibTeX RDF
26	Takashi Miyamori, Kunle Olukotun	A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications.	FCCM	1998	DBLP DOI BibTeX RDF
26	Manfred Kunde, Kay Guertzig	Efficient Sorting and Routing on Reconfigurable Meshes Using Restricted Bus Length.	IPPS	1997	DBLP DOI BibTeX RDF
25	Dirk Koch, Christian Beckhoff, Jürgen Teich	Hardware Decompression Techniques for FPGA-Based Embedded Systems.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	reconfigurable computing, configuration, Bitstream
24	Maurice Keller, Andrew Byrne, William P. Marnane	Elliptic Curve Cryptography on FPGA for Low-Power Applications.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, low-power, Cryptography, elliptic curves
24	Manish Handa, Ranga Vemuri	An efficient algorithm for finding empty space for online FPGA placement.	DAC	2004	DBLP DOI BibTeX RDF	online placement, partially reconfigurable FPGAs, reconfigurable computing
24	Johann Großschädl	The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip.	ACSAC	2000	DBLP DOI BibTeX RDF	RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency
24	Shung-Shing Lee, Shi-Jinn Horng, Horng-Ren Tsai, Yu-Hua Lee	Some Image Processing Algorithms on a RAP with Wider Bus Networks.	IPPS	1996	DBLP DOI BibTeX RDF	wider bus networks, reconfigurable array of processors, base-m number system, parallel algorithms, parallel algorithms, image processing, image segmentation, image segmentation, parallel architectures, multiprocessor interconnection networks, reconfigurable architectures, histogram, system buses, computation power, image processing algorithms, image labeling, constant time, RAP
24	Paul M. Wexelblat	An alternative addressing scheme for conventional CDMA fiber-optic networks allows interesting parallel processing capabilities.	ICPADS	1996	DBLP DOI BibTeX RDF	alternative addressing scheme, CDMA fiber-optic networks, fiber based LAN, sensor type nodes, dynamically reconfigurable parallel multiprocessor, real-time systems, parallel processing, parallel processing, local area network, code division multiple access, code division multiple access, reconfigurable architectures, optical fibre LAN
24	S. Q. Zheng 0001, Balaji Calidas, Yanjun Zhang	Efficient in-place sorting algorithms using feasible parallel machine models.	ISPAN	1996	DBLP DOI BibTeX RDF	in-place sorting algorithms, feasible parallel machine models, parallel sorting scheme, ZZ-sort, average performance, MasPar parallel computer, distributed memory parallel computer system, standard routine, space critical situations, fixed-size reconfigurable meshes, parallel algorithms, sorting, reconfigurable architectures, distributed memory systems, safety-critical software, tight bound, worst case performance, parallel sorting algorithm
24	Michael Bolotski, Thomas Simon, Carlin Vieri, Rajeevan Amirtharajah, Thomas F. Knight Jr.	Abacus: a 1024 processor 8 ns SIMD array.	ARVLSI	1995	DBLP DOI BibTeX RDF	bit-slice computers, Abacus, SIMD array, reconfigurable bit-parallel array, system-level design issues, real-time early vision processing, bit-slice processing element, 8 ns, real-time systems, computer vision, VLSI, parallel architectures, reconfigurable architectures, microarchitecture, VLSI implementation, communication primitives
24	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	T-trees: A tree-based representation for temporal and three-dimensional floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration
24	Yu Zhang, Dan Feng 0001	An Active Storage System for High Performance Computing.	AINA	2008	DBLP DOI BibTeX RDF	High Performance Computing, Reconfigurable Computing, Active Storage
24	Rodolfo Pellizzoni, Marco Caccamo	Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Reconfigurable devices, real-time resource management, online admission control, hardware and software tasks
24	Katherine Compton, Scott Hauck	Automatic Design of Area-Efficient Configurable ASIC Cores.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	logic design and synthesis, Reconfigurable architecture
24	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Temporal floorplanning using the three-dimensional transitive closure subGraph.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration
24	Wim Heirman, Joni Dambre, Jan Van Campenhout	Synthetic traffic generation as a tool for dynamic interconnect evaluation.	SLIP	2007	DBLP DOI BibTeX RDF	dynamic interconnect requirements, reconfigurable interconnect, synthetic traffic generation
24	Kenneth L. Rice, Christopher N. Vutsinas, Tarek M. Taha	A preliminary investigation of a neocortex model implementation on the Cray XD1.	SC	2007	DBLP DOI BibTeX RDF	cognitive algorithms, FPGA, reconfigurable, application performance
24	Michael Hübner 0001, Jürgen Becker 0001	Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration.	SBCCI	2006	DBLP DOI BibTeX RDF	designflow, dynamic and partial reconfiguration, reconfigurable hardware
24	Soheil Ghiasi, Ani Nahapetian, Majid Sarrafzadeh	An optimal algorithm for minimizing run-time reconfiguration delay.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	instantiation ordering, reconfiguration delay, Reconfigurable computing
24	Andrea Lodi 0002, Mario Toma, Fabio Campi	A pipelined configurable gate array for embedded processors.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, pipeline, energy, reconfigurable processor
24	Kris Gaj, Tarek A. El-Ghazawi, Nikitas A. Alexandridis, Jacek R. Radzikowski, Mohamed Taher, Frederic Vroman	Effective Utilization and Reconfiguration of Distributed Hardware Resources Using Job Management Systems.	IPDPS	2003	DBLP DOI BibTeX RDF	distributed hardware resources, Job Management Systems, accelerator boards, FPGA, job scheduling, reconfigurable hardware
24	Ulrik Pagh Schultz	Distributed control diffusion: towards a flexible programming paradigm for modular robots.	ROBOCOMM	2007	DBLP DOI BibTeX RDF
24	Reiner W. Hartenstein	RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances.	IPDPS	2006	DBLP DOI BibTeX RDF
24	Bo-Hee Lee, Kyu-Tae Seo, Jung-Shik Kong, Jin-Geol Kim	Design of the Configurable Clothes Using Mobile Actuator-Sensor Network.	ICCSA (4)	2006	DBLP DOI BibTeX RDF
24	Tien-Fu Chen, Chia-Ming Hsu, S.-R. Wu	Flexible Heterogeneous Multicore Architectures for Versatile Media Processing Via Customized Long Instruction Words.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
23	Like Yan, Binbin Wu, Yuan Wen, Shaobin Zhang, Tianzhou Chen	A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit.	CIT	2010	DBLP DOI BibTeX RDF	reconfigurable computing, multi-core, dynamic reconfiguration, processor architecture
23	Laurent Gantel, Salah Layouni, Mohamed El Amine Benkhelifa, François Verdier, Stéphanie Chauvet	Multiprocessor Task Migration Implementation in a Reconfigurable Platform.	ReConFig	2009	DBLP DOI BibTeX RDF	RTOS for embedded platforms, Dynamic and partial reconfigurable systems, FPGA, MPSoC, Task migration
23	Sven Eisenhardt, Thomas Schweizer, Andreas Bernauer, Tommy Kuhn, Wolfgang Rosenstiel	Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures.	ReConFig	2009	DBLP DOI BibTeX RDF	temperature optimization, reliability, reconfigurable computing, hot spot, coarse-grained
23	John A. Kalomiros, John N. Lygouras	A Reconfigurable Architecture for Stereo-Assisted Detection of Point-Features for Robot Mapping.	ReConFig	2009	DBLP DOI BibTeX RDF	Real-Time systems, Machine vision, Reconfigurable hardware, Robot mapping
23	Juan Fernando Eusse Giraldo, Ricardo Pezzuol Jacobi	Signal Processing Domain Application Mapping on the Brick Reconfigurable Array.	ReConFig	2009	DBLP DOI BibTeX RDF	Expression Grain, Reconfigurable Computing, Signal Processing, Application Mapping
23	Asadollah Shahbahrami, Mahmood Ahmadi, Stephan Wong, Koen Bertels	A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements.	ReConFig	2009	DBLP DOI BibTeX RDF	Grid Computing, Reconfigurable Computing, DWT
23	Vikas Aggarwal, Rafael García, Greg Stitt, Alan D. George, Herman Lam	SCF: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems.	HPRCTA@SC	2009	DBLP DOI BibTeX RDF	communication, coordination, reconfigurable computing, productivity, portability, heterogeneous computing, accelerators
23	Paulo Sérgio Brandão do Nascimento, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Abner Corrêa Barros, Manoel Eusébio de Lima	A Temporal Partitioning Methodology for Reconfigurable High Performance Computers.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGAs, Reconfigurable Computers, Temporal Partitioning
23	Zain-ul-Abdin, Bertil Svensson	Using a CSP Based Programming Model for Reconfigurable Processor Arrays.	ReConFig	2008	DBLP DOI BibTeX RDF	CSP, Programming Models, Coarse-grained Reconfigurable Architectures
23	Francesco Redaelli, Marco D. Santambrogio, Seda Ogrenci Memik	An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures.	ReConFig	2008	DBLP DOI BibTeX RDF	2D dynamically and partially reconfigurable architecture, ILP scheduling model
23	Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoît Miramond, François Verdier, Daniel Chillet, Sébastien Pillement	A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources.	ReConFig	2008	DBLP DOI BibTeX RDF	dynamically reconfigurable architectures, RTOS, high-level modelling
23	Juan Antonio Clemente, Carlos González 0002, Javier Resano, Daniel Mozos	A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems.	ReConFig	2008	DBLP DOI BibTeX RDF	Hardware multitasking, FPGAs, Reconfigurable architectures, Task scheduling
23	Yuken Kishimoto, Shinichiro Haruyama, Hideharu Amano	Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor.	ReConFig	2008	DBLP DOI BibTeX RDF	Software-Defined Radio, Reconfigurable Processor, Viterbi Decoder
23	Manuel Saldaña, Emanuel Ramalho, Paul Chow	A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI.	ReConFig	2008	DBLP DOI BibTeX RDF	Simulation, FPGA, Parallel Programming, MPI, Message-Passing, Reconfigurable, High-Performance
23	Abdulrahman Hanoun, Friedrich Mayer-Lindenberg, Bassel Soudan	Reconfigurable Cell Architecture for Systolic and Pipelined Computing Datapaths.	ReConFig	2008	DBLP DOI BibTeX RDF	2D pipeline, Baugh-Wooley, Reconfigurable, Multiplier, distributed arithmetic, Systolic
23	Luiza M. N. Coutinho, José Leandro D. Mendes, Carlos A. P. S. Martins	Dynamically Reconfigurable Split Cache Architecture.	ReConFig	2008	DBLP DOI BibTeX RDF	Computer Architecture, Reconfigurable Computing, Cache memories
23	Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello	Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices.	ReConFig	2008	DBLP DOI BibTeX RDF	multimedia, reconfigurable, SIMD, datapath
23	Patrick Rocke, Brian McGinley, Fearghal Morgan, John Maher	Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller.	ARC	2007	DBLP DOI BibTeX RDF	Genetic Algorithm, Evolutionary Computation, Reconfigurable Hardware, Spiking Neural Networks, FPAA
23	Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy 0001, Ranjani Narayan	Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.	ARC	2009	DBLP DOI BibTeX RDF
23	Ricardo S. Ferreira 0001, Alex Damiany, Julio C. Goldner Vendramini, Tiago Teixeira, João M. P. Cardoso	On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks.	ARC	2009	DBLP DOI BibTeX RDF
23	Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek	Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study.	ARC	2008	DBLP DOI BibTeX RDF
23	Vu Manh Tuan, Hideharu Amano	A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor.	ARC	2008	DBLP DOI BibTeX RDF
23	Ozana Silvia Dragomir, Elena Moscu Panainte, Koen Bertels, Stephan Wong	Optimal Unroll Factor for Reconfigurable Architectures.	ARC	2008	DBLP DOI BibTeX RDF
23	Senthil Kumar Lakshmanan, Peter Tawdross, Andreas König 0001	Towards Generic On-the-Fly Reconfigurable Sensor Electronics for Embedded System- First Measurement Results of Reconfigurable Folded.	VLSI Design	2007	DBLP DOI BibTeX RDF
23	David B. Thomas, Wayne Luk, Michael Stumpf	Reconfigurable Hardware Acceleration of Canonical Graph Labelling.	ARC	2007	DBLP DOI BibTeX RDF
23	Wagner Rodrigo Weinert, César Manuel Vargas Benítez, Heitor S. Lopes, Carlos Raimundo Erig Lima	Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing.	ARC	2007	DBLP DOI BibTeX RDF
23	Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic	MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture.	ARC	2007	DBLP DOI BibTeX RDF
23	Yong Dou, Jinhui Xu 0002, Guiming Wu	The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.	ARC	2007	DBLP DOI BibTeX RDF
23	Yazhuo Dong, Yong Dou, Jie Zhou 0007	Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware.	ARC	2007	DBLP DOI BibTeX RDF
23	Balal Ahmad, Ahmet T. Erdogan, Sami Khawam	Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC.	AHS	2006	DBLP DOI BibTeX RDF
23	Tarek A. El-Ghazawi, Dave Bennett, Daniel S. Poznanovic, Allan Cantle, Keith D. Underwood, Rob Pennington, Duncan A. Buell, Alan D. George, Volodymyr V. Kindratenko	Reconfigurable supercomputing - Is high-performance reconfigurable computing the next supercomputing paradigm?	SC	2006	DBLP DOI BibTeX RDF
23	Sara Román Navarro, Julio Septién, Hortensia Mecha, Daniel Mozos	Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
23	Jens Braunes, Rainer G. Spallek	A Compiler-Oriented Architecture Description for Reconfigurable Systems.	ARC	2006	DBLP DOI BibTeX RDF
23	Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano	Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor.	ARC	2006	DBLP DOI BibTeX RDF
23	Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro	Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility.	ARC	2006	DBLP DOI BibTeX RDF
23	Marcelo Götz, Florian Dittmann 0001	Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server.	ARC	2006	DBLP DOI BibTeX RDF
23	Gerd Van den Branden, Geert Braeckman, Abdellah Touhafi, Erik F. Dirkx	Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform.	ARC	2006	DBLP DOI BibTeX RDF