Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Osman Allam, Stijn Eyerman, Lieven Eeckhout |
An efficient CPI stack counter architecture for superscalar processors. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Michael Andersch, Chi Ching Chi, Ben H. H. Juurlink |
Programming parallel embedded and consumer applications in OpenMP superscalar. |
PPoPP |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Wen-mei W. Hwu |
Superscalar Processors. |
Encyclopedia of Parallel Computing |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Jiongyao Ye, Yu Wan 0002, Takahiro Watanabe |
A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Jongmyon Kim, Linda M. Wills, D. Scott Wills |
Color-Aware Instructions for Embedded Superscalar Processors. |
J. Signal Process. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Bijan Alizadeh, Masahiro Fujita |
Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg |
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. |
ISCA |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. |
IEEE Trans. Very Large Scale Integr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Enric Tejedor, Rosa M. Badia, Romina Royo, Josep Lluis Gelpí |
Enabling HMMER for the Grid with COMP Superscalar. |
ICCS |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Huiba Li, Shengyun Liu, Yuxing Peng 0001, Dongsheng Li 0001, Hangjun Zhou, Xicheng Lu |
Superscalar communication: A runtime optimization for distributed applications. |
Sci. China Inf. Sci. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Sebastián Reyes, Camelia Muñoz-Caro, Alfonso Niño, Raül Sirvent, Rosa M. Badia |
Monitoring and steering Grid applications with GRID superscalar. |
Future Gener. Comput. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Gyu Sang Choi, Chita R. Das |
A Superscalar software architecture model for Multi-Core Processors (MCPs). |
J. Syst. Softw. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Mario Schölzel |
Software-based self-repair of statically scheduled superscalar data paths. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Sandeep Navada, Niket Kumar Choudhary, Eric Rotenberg |
Criticality-driven superscalar design space exploration. |
PACT |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero |
Task Superscalar: An Out-of-Order Task Pipeline. |
MICRO |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Jörg Mische, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer |
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT. |
ARCS |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Jongbok Lee |
A Superscalar Processor Model for Limited Functional Units Using Instruction Dependencies. |
CATA |
2010 |
DBLP BibTeX RDF |
|
17 | Ritu Baniwal, Kumar Sambhav Pandey |
Recent Trends in Superscalar Architecture to Exploit More Instruction Level Parallelism. |
ICT |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Meltem Ozsoy, Yusuf Onur Koçberber, Mehmet Kayaalp 0001, Oguz Ergin |
Dynamic register file partitioning in superscalar microprocessors for energy efficiency. |
ICCD |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Faheem Sheikh, Shahid Masud, Rehan Ahmed |
Superscalar architecture design for high performance DSP operations. |
Microprocess. Microsystems |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Arpad Gellert, Adrian Florea, Lucian N. Vintan |
Exploiting selective instruction reuse and value prediction in a superscalar architecture. |
J. Syst. Archit. |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. |
ICSAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Jorge Ortiz 0002 |
A Reconfigurable Superscalar Processor Architecture for FPGA-based Designs. |
CDES |
2009 |
DBLP BibTeX RDF |
|
17 | Nasir Mohyuddin, Kimish Patel, Massoud Pedram |
Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Raül Sirvent Pardell |
GRID superscalar: a programming model for the Grid. |
|
2009 |
RDF |
|
17 | Jorge Ortiz 0002 |
Synthesis Techniques for Semi-Custom Dynamically Reconfigurable Superscalar Processors. |
|
2009 |
RDF |
|
17 | Christopher B. Smith, David R. Mandel, Eugene John |
A superscalar simulation employing poisson distributed stalls. |
Comput. Electr. Eng. |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Wlodzimierz Funika, Piotr Machner, Marian Bubak, Rosa M. Badia, Raül Sirvent |
Performance Monitoring of GRID superscalar: Summing up. |
CoreGRID Workshop on Grid Middleware |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Xianfeng Zhao |
Structural Optimization on Superscalar Processors. |
CSSE (3) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Tameesh Suri |
Improving instruction level parallelism through reconfigurable units in superscalar processors. |
SIGARCH Comput. Archit. News |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz |
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. |
VLSI-SoC (Selected Papers) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Virginia Escuder, Raúl Durán, Rafael Rico |
Analysis of x86 ISA Condition Codes Influence on Superscalar Execution. |
HiPC |
2007 |
DBLP DOI BibTeX RDF |
Condition codes, Graph theory, Instruction level parallelism, Instruction set architecture |
17 | Shijian Zhang, Weiwu Hu |
CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors. |
ATS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Jonathan Evans, Kyle Rupnow, Katherine Compton |
Reconfigurable Functional Units for Scientific Superscalar Processors. |
FPT |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Ani Anciaux-Sedrakian, Rosa M. Badia, Raül Sirvent, Josep M. Pérez, Thilo Kielmann, André Merzky |
GRID superscalar and job mapping on the reliable grid resources. |
CoreGRID Workshop - Making Grids Work |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Rosa M. Badia, Raül Sirvent, Marian Bubak, Wlodzimierz Funika, Piotr Machner |
Performance monitoring of GRID superscalar with OCM-G/G-PM: improvements. |
CoreGRID Workshop - Making Grids Work |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Ian Michael Caulfield |
Complexity-effective superscalar embedded processors using instruction-level distributed processing. |
|
2007 |
RDF |
|
17 | Yasuo Sugure, Seiji Takeuchi, Yuichi Abe, Hiromichi Yamada, Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka, Takanori Shimura |
Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications. |
IEICE Trans. Electron. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Juan L. Aragón, José M. González, Antonio González 0001 |
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
low-power design, processor architecture, energy-aware systems, Control speculation |
17 | Tsai Chi Huang, Linda M. Wills, Roy W. Melton, Cecil O. Alford |
Predicting communication protocol performance on superscalar architectures using instruction dependency. |
Perform. Evaluation |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Stephen Hill |
Design of a reusable 1GHz, superscalar ARM processor. |
Hot Chips Symposium |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Oguz Ergin |
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil |
A Predictive Performance Model for Superscalar Processors. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Raül Sirvent, Rosa M. Badia, Natalia Currle-Linde, Michael M. Resch |
GRID Superscalar and GriCoL: Integrating Different Programming Approaches. |
CoreGRID Integration Workshop |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Rosa M. Badia, Raül Sirvent, Marian Bubak, Wlodzimierz Funika, Piotr Machner |
Performance monitoring of GRID superscalar with OCM-G/G-PM: integration issues. |
CoreGRID Integration Workshop |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Yongxin Zhu 0001, Weng-Fai Wong, Stefan Andrei |
Co-optimization of Performance and Power in a Superscalar Processor Design. |
EUC Workshops |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Toshinori Sato, Akihiro Chiyonobu |
Evaluating the Impact of Fault Recovery on Superscalar Processor Performance. |
PRDC |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Jessica H. Tseng |
Banked microarchitectures for complexity-effective superscalar microprocessors. |
|
2006 |
RDF |
|
17 | Timothy M. Jones 0001 |
Compiler-directed energy savings in superscalar processors. |
|
2006 |
RDF |
|
17 | Jean-Luc Gaudiot, Jung-Yup Kang, Won Woo Ro |
Techniques to Improve Performance Beyond Pipelining: Superpipelining, Superscalar, and VLIW. |
Adv. Comput. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Douglas A. Lyon |
Java Optimization for Superscalar and Vector Architectures. |
J. Object Technol. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Toshinori Sato, Akihiro Chiyonobu |
An Energy-Efficient Clustered Superscalar Processor. |
IEICE Trans. Electron. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Oleg Bessonov, Dominique Fougère, Bernard Roux |
Development of efficient computational kernels and linear algebra routines for out-of-order superscalar processors. |
Future Gener. Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Julio Sahuquillo, Salvador Petit, Ana Pont, Veljko M. Milutinovic |
Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors. |
J. Syst. Archit. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Rafael Rico, Juan Ignacio Pérez, José Antonio de Frutos |
The impact of x86 instruction set architecture on superscalar processing. |
J. Syst. Archit. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Pierre Salverda, Craig B. Zilles |
A Criticality Analysis of Clustering in Superscalar Processors. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Testing Superscalar Processors in Functional Mode. |
FPL |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Mihai Budiu, Pedro V. Artigas, Seth Copen Goldstein |
Dataflow: A Complement to Superscalar. |
ISPASS |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Peng Zhou, Soner Önder, Steve Carr 0001 |
Fast branch misprediction recovery in out-of-order superscalar processors. |
ICS |
2005 |
DBLP DOI BibTeX RDF |
processor state, checkpoint, recovery, branch misprediction |
17 | Manuel A. (Manuel Alejandro) Pajuelo González |
Speculative Vectorization for Superscalar Processors. |
|
2005 |
RDF |
|
17 | Dean G. Bair, Steven M. German, William D. Wollyung, Edward J. Kaminski Jr., James Schafer, Michael P. Mullen, William J. Lewis, Rebecca Wisniewski, Joerg Walter, Steven Mittermaier, Visda Vokhshoori, Robert J. Adkins, Michael Halas, Thomas Ruane, Ursel Hahn |
Functional verification of the z990 superscalar, multibook microprocessor complex. |
IBM J. Res. Dev. |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose |
Complexity-Effective Reorder Buffer Designs for Superscalar Processors. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Chao-Chin Wu |
Embedding a superscalar processor onto a chip multiprocessor. |
Microprocess. Microsystems |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Vladimir Lazarov, Maria Marinova |
Dependencies evaluation in superscalar processors. |
CompSysTech |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Mars Lan, Morteza Biglari-Abhari |
An Adaptive Superscalar Architecture for Embedded Systems. |
ESA/VLSI |
2004 |
DBLP BibTeX RDF |
|
17 | Shahzad Nazar, Behrooz A. Shirazi, Sungyong Jung |
Performance/Energy Efficiency Analysis of Register Files in Superscalar Processors. |
ESA/VLSI |
2004 |
DBLP BibTeX RDF |
|
17 | Axel Böttcher |
Visualizing the MMIX superscalar pipeline: not only for teaching purposes. |
WCAE |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Joan-Manuel Parcerisa |
Design of Clustered Superscalar Microarchitectures. |
|
2004 |
RDF |
|
17 | Miroslav N. Velev, Randal E. Bryant |
Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. |
J. Symb. Comput. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera |
Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. |
J. Syst. Archit. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Parimal Patel, Venkataramana Reddipalli |
Design Considerations of Implementing a Superscalar CPU in FPGA. |
CATA |
2003 |
DBLP BibTeX RDF |
|
17 | Elena Zaharieva-Stoyanova, Lorentz Jäntschi |
Application of software data dependency detection algorithm in superscalar computer architecture. |
CompSysTech |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Hee-Jun Yoo, Jin-Young Choi |
Process Algebraic Model of Superscalar Processor Programs for Instruction Level Timing Analysis. |
PaCT |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Oleg Bessonov, Dominique Fougère, Bernard Roux |
Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors. |
PaCT |
2003 |
DBLP DOI BibTeX RDF |
linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors |
17 | Feng-Jiann Shiao, Jong-Jiann Shieh |
An Issue Logic for Superscalar Microprocessors. |
CAINE |
2003 |
DBLP BibTeX RDF |
|
17 | James C. Hoe |
Superscalar out-of-order demystified in four instructions. |
WCAE |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung |
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. |
J. Inf. Sci. Eng. |
2002 |
DBLP BibTeX RDF |
|
17 | Toshinori Sato, Itsujiro Arita |
Simplifying Instruction Issue Logic in Superscalar Processors. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Sascha Wennekers, Christian Siemers |
Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture. |
ARCS |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Siddharth Rele, Santosh Pande, Soner Önder, Rajiv Gupta 0001 |
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors. |
CC |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Zheng-Kuo Wu, Jong-Jiann Shieh |
Block Based Fetch Engine for Superscalar Processors. |
CAINE |
2002 |
DBLP BibTeX RDF |
|
17 | R.-Ming Shiu, Hui-Yue Hwang, Jean Jyh-Jiun Shann |
Aggressive Schduling for Memory Accesses of CISC Superscalar Microprocessors. |
J. Inf. Sci. Eng. |
2001 |
DBLP BibTeX RDF |
|
17 | Pierre Michaud, André Seznec, Stéphan Jourdan |
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. |
Int. J. Parallel Program. |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Bernard Goossens |
Handling 16 instructions per cycle in a superscalar processor. |
Future Gener. Comput. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Yasunori Kimura, Kouya Shimura, Haruko Nishimoto, Motoyuki Kawaba, Takeshi Eguchi |
Building a design support tool for superscalar processors and its case studies. |
Syst. Comput. Jpn. |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori |
A high-speed dynamic instruction scheduling scheme for superscalar processors. |
MICRO |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Ioannis Vakalis |
A Comparison Study of the Behavior of Equivalent Algorithms in Fault Injection Experiments in Parallel Superscalar Architectures. |
SAFECOMP |
2001 |
DBLP BibTeX RDF |
|
17 | Sid Ahmed Ali Touati |
Register Saturation in Superscalar and VLIW Codes. |
CC |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Julien Sébot, Nathalie Drach-Temam |
Memory Bandwidth: The True Bottleneck of SIMD Multimedia Performance on a Superscalar Processor. |
Euro-Par |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Gabriel H. Loh |
A time-stamping algorithm for efficient performance estimation of superscalar processors. |
SIGMETRICS/Performance |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Yung-Chung Wu, Jong-Jiann Shieh |
A Multiple Blocks Fetch Engine for High Performance Superscalar Processors. |
PDCS |
2001 |
DBLP BibTeX RDF |
|
17 | Matt Postiff, David A. Greene, Steven E. Raasch, Trevor N. Mudge |
Integrating superscalar processor components to implement register caching. |
ICS |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Miroslav N. Velev, Randal E. Bryant |
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Frank P. Burns, Albert Koelmans, Alexandre Yakovlev |
WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets. |
Real Time Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Andrew Wolfe, Derek B. Noonburg |
A Superscalar 3D Graphics Engine. |
J. Instr. Level Parallelism |
2000 |
DBLP BibTeX RDF |
|
17 | S. J. Davis, C. J. Elston, Paul A. Findlay |
Register bypassing in an asynchronous superscalar processor. |
J. Syst. Archit. |
2000 |
DBLP DOI BibTeX RDF |
|
17 | K. S. Loh, Weng-Fai Wong |
Multiple context multithreaded superscalar processor architecture. |
J. Syst. Archit. |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Amirali Baniasadi, Andreas Moshovos |
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. |
MICRO |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Andreas Moshovos, Gurindar S. Sohi |
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. |
HPCA |
2000 |
DBLP DOI BibTeX RDF |
Scheduling, Cache, Memory, Instruction Level Parallelism |
17 | Fujio Ishihara, Christian Klinger, Ken-ichi Agawa |
Clock design of 300MHz 128-bit 2-way superscalar microprocessor. |
ASP-DAC |
2000 |
DBLP DOI BibTeX RDF |
|