Search results for "wirelength"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali	Multiobjective VLSI cell placement using distributed simulated evolution algorithm.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
10	Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh	3D module placement for congestion and power noise reduction.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	3D module placement, power noise reduction, congestion, system-on-package
10	Ulrich Brenner, Markus Struzyna	Faster and better global placement by a new transportation algorithm.	DAC	2005	DBLP DOI BibTeX RDF	VLSI-placement, global placement, transportation problem
10	Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar	Net weighting to reduce repeater counts during placement.	DAC	2005	DBLP DOI BibTeX RDF	interconnect, placement, scaling, buffering, repeater, force-directed placement, net weighting
10	Paul D. Kundarewich, Jonathan Rose	Synthetic circuit generation using clustering and iteration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Jai-Ming Lin, Yao-Wen Chang	TCG-S: orthogonal coupling of P*-admissible representations for general floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Chris C. N. Chu, Evangeline F. Y. Young	Nonrectangular shaping and sizing of soft modules for floorplan-design improvement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu	Nontree routing for reliability and yield improvement [IC layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, Xu Xu 0001	Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Jason Cong, Sung Kyu Lim	Retiming-based timing analysis with an application to mincut-based global placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Jacob R. Minz, Mohit Pathak, Sung Kyu Lim	Net and Pin Distribution for 3D Package Global Routing.	DATE	2004	DBLP DOI BibTeX RDF
10	Zion Cien Shen, Chris C. N. Chu	Accurate and efficient flow based congestion estimation in floorplanning.	ASP-DAC	2004	DBLP DOI BibTeX RDF
10	Ulrich Brenner, Anna Pauli, Jens Vygen	Almost optimum placement legalization by minimum cost flow and dynamic programming.	ISPD	2004	DBLP DOI BibTeX RDF	placement, legalization, minimum-cost flow, detailed placement
10	Jason Cong, Jie Wei, Yan Zhang	A thermal-driven floorplanning algorithm for 3D ICs.	ICCAD	2004	DBLP DOI BibTeX RDF
10	Chen Li 0004, Min Xie 0004, Cheng-Kok Koh, Jason Cong, Patrick H. Madden	Routability-driven placement and white space allocation.	ICCAD	2004	DBLP DOI BibTeX RDF
10	Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang	I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.	ICCD	2004	DBLP DOI BibTeX RDF
10	Meng-Chen Wu, Yao-Wen Chang	Placement with Alignment and Performance Constraints Using the B*-Tree Representation.	ICCD	2004	DBLP DOI BibTeX RDF
10	PariVallal Kannan, Dinesh Bhatia	Estimating Pre-Placement FPGA Interconnection Requirements.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar	Large-scale placement by grid-warping.	DAC	2004	DBLP DOI BibTeX RDF	algorithms, placement
10	Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout	A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Michael G. Wrighton, André DeHon	Hardware-assisted simulated annealing with application for fast FPGA placement.	FPGA	2003	DBLP DOI BibTeX RDF	field-programmable gate arrays, simulated annealing, placement, reconfigurable computing, design automation
10	Paul D. Kundarewich, Jonathan Rose	Synthetic circuit generation using clustering and iteration.	FPGA	2003	DBLP DOI BibTeX RDF
10	Bing Lu, Jiang Hu, Gary Ellis, Haihua Su	Process variation aware clock tree routing.	ISPD	2003	DBLP DOI BibTeX RDF	VLSI, interconnect, physical design, clock tree synthesis
10	Saurabh N. Adya, Igor L. Markov, Paul Villarrubia	On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis.	ICCAD	2003	DBLP DOI BibTeX RDF
10	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage.	ICCAD	2003	DBLP DOI BibTeX RDF
10	Brent Goplen, Sachin S. Sapatnekar	Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach.	ICCAD	2003	DBLP DOI BibTeX RDF
10	Joachim Pistorius, Mike Hutton	Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation.	SLIP	2003	DBLP DOI BibTeX RDF	FPGA architecture, interconnect prediction, SLIP, rent
10	Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang	Multilevel floorplanning/placement for large-scale modules using B*-trees.	DAC	2003	DBLP DOI BibTeX RDF	multilevel framework, floorplanning, lagrangian relaxation
10	Yih-Chih Chou, Youn-Long Lin	Effective enforcement of path-delay constraints inperformance-driven placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh	Congestion estimation during top-down placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, Stefanus Mantik, Igor L. Markov	Min-max placement for large-scale timing optimization.	ISPD	2002	DBLP DOI BibTeX RDF
10	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	Routability driven white space allocation for fixed-die standard-cell placement.	ISPD	2002	DBLP DOI BibTeX RDF	placement, physical design, routability
10	Saurabh N. Adya, Igor L. Markov	Consistent placement of macro-blocks using floorplanning and standard-cell placement.	ISPD	2002	DBLP DOI BibTeX RDF
10	Jingcao Hu, Yangdong Deng, Radu Marculescu	System-Level Point-to-Point Communication Synthesis using Floorplanning Information.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	System-leve design, low-power, floorplanning, Communication synthesis, point-to-point communication
10	Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky	Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
10	Jai-Ming Lin, Yao-Wen Chang	TCG-S: orthogonal coupling of P*-admissible representations for general floorplans.	DAC	2002	DBLP DOI BibTeX RDF
10	Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh	Fast floorplanning for effective prediction and construction.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe	Constraint-based watermarking techniques for design IP protection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
10	Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky	Provably good global buffering by multi-terminal multicommodity flow approximation.	ASP-DAC	2001	DBLP DOI BibTeX RDF
10	Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje	Overcoming wireload model uncertainty during physical design.	ISPD	2001	DBLP DOI BibTeX RDF
10	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov	Optimal partitioners and end-case placers for standard-cell layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	Jason Cong, Xin Yuan 0005	Routing tree construction under fixed buffer locations.	DAC	2000	DBLP DOI BibTeX RDF
10	Yao-Wen Chang, Yu-Tsang Chang	An architecture-driven metric for simultaneous placement and global routing for FPGAs.	DAC	2000	DBLP DOI BibTeX RDF
10	Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov	Function Smoothing with Applications to VLSI Layout.	ASP-DAC	1999	DBLP DOI BibTeX RDF
10	Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai	A Timing-Driven Block Placer Based on Sequence Pair Model.	ASP-DAC	1999	DBLP DOI BibTeX RDF	timing-driven, building block placement, sequence pair, simulated annealing algorithm
10	Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong	Relaxed Simulated Tempering for VLSI Floorplan Designs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
10	Sergei L. Bezrukov, Sajal K. Das 0001, Robert Elsässer	Optimal Cuts for Powers of the Petersen Graph.	WG	1999	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe	Robust IP Watermarking Methodologies for Physical Design.	DAC	1998	DBLP DOI BibTeX RDF	system-on-chip test, testing embedded core, intellectual property test
10	Majid Sarrafzadeh, Maogang Wang	NRG: global and detailed placement.	ICCAD	1997	DBLP DOI BibTeX RDF	NRG, Global Placement, Placement, Detailed Placement
10	Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan	Quadratic Placement Revisited.	DAC	1997	DBLP DOI BibTeX RDF
10	Michael J. Alexander, Gabriel Robins	New performance-driven FPGA routing algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
10	Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger	Prim-Dijkstra tradeoffs for improved performance-driven routing tree design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
10	Bernard A. McCoy, Gabriel Robins	Non-tree routing [VLSI layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
10	Stephen T. Frezza, Steven P. Levitan	SPAR: a schematic place and route system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
10	Mark Hirsch, Daniel P. Siewiorek	The effect of placement of automatically extracted structure.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
10	Raffaele Costa, Francesco Curatelli, Daniele D. Caviglia, Giacomo M. Bisio	Symbolic generation of constrained random logic cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
10	Michael A. B. Jackson, Ernest S. Kuh	Performance-driven Placement of Cell Based IC's.	DAC	1989	DBLP DOI BibTeX RDF