|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 405 occurrences of 176 keywords
|
|
|
Results
Found 457 publication records. Showing 457 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
10 | Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali |
Multiobjective VLSI cell placement using distributed simulated evolution algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 6226-6229, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh |
3D module placement for congestion and power noise reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 458-461, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
3D module placement, power noise reduction, congestion, system-on-package |
10 | Ulrich Brenner, Markus Struzyna |
Faster and better global placement by a new transportation algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 591-596, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI-placement, global placement, transportation problem |
10 | Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar |
Net weighting to reduce repeater counts during placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 503-508, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnect, placement, scaling, buffering, repeater, force-directed placement, net weighting |
10 | Paul D. Kundarewich, Jonathan Rose |
Synthetic circuit generation using clustering and iteration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6), pp. 869-887, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Jai-Ming Lin, Yao-Wen Chang |
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6), pp. 968-980, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Chris C. N. Chu, Evangeline F. Y. Young |
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 71-79, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu |
Nontree routing for reliability and yield improvement [IC layout]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 148-156, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Andrew B. Kahng, Xu Xu 0001 |
Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4), pp. 464-471, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Jason Cong, Sung Kyu Lim |
Retiming-based timing analysis with an application to mincut-based global placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1684-1692, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Jacob R. Minz, Mohit Pathak, Sung Kyu Lim |
Net and Pin Distribution for 3D Package Global Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1410-1411, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Zion Cien Shen, Chris C. N. Chu |
Accurate and efficient flow based congestion estimation in floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 671-676, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Ulrich Brenner, Anna Pauli, Jens Vygen |
Almost optimum placement legalization by minimum cost flow and dynamic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 2-9, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
placement, legalization, minimum-cost flow, detailed placement |
10 | Jason Cong, Jie Wei, Yan Zhang |
A thermal-driven floorplanning algorithm for 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 306-313, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Chen Li 0004, Min Xie 0004, Cheng-Kok Koh, Jason Cong, Patrick H. Madden |
Routability-driven placement and white space allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 394-401, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang |
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 562-567, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Meng-Chen Wu, Yao-Wen Chang |
Placement with Alignment and Performance Constraints Using the B*-Tree Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 568-571, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | PariVallal Kannan, Dinesh Bhatia |
Estimating Pre-Placement FPGA Interconnection Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 869-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar |
Large-scale placement by grid-warping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 351-356, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
algorithms, placement |
10 | Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout |
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 24-34, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Michael G. Wrighton, André DeHon |
Hardware-assisted simulated annealing with application for fast FPGA placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 33-42, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, simulated annealing, placement, reconfigurable computing, design automation |
10 | Paul D. Kundarewich, Jonathan Rose |
Synthetic circuit generation using clustering and iteration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 245, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Bing Lu, Jiang Hu, Gary Ellis, Haihua Su |
Process variation aware clock tree routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 174-181, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, physical design, clock tree synthesis |
10 | Saurabh N. Adya, Igor L. Markov, Paul Villarrubia |
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 311-319, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma |
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 754-759, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Brent Goplen, Sachin S. Sapatnekar |
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 86-90, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Joachim Pistorius, Mike Hutton |
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 31-38, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA architecture, interconnect prediction, SLIP, rent |
10 | Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang |
Multilevel floorplanning/placement for large-scale modules using B*-trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 812-817, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multilevel framework, floorplanning, lagrangian relaxation |
10 | Yih-Chih Chou, Youn-Long Lin |
Effective enforcement of path-delay constraints inperformance-driven placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1), pp. 15-22, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh |
Congestion estimation during top-down placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1), pp. 72-80, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Andrew B. Kahng, Stefanus Mantik, Igor L. Markov |
Min-max placement for large-scale timing optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 143-148, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh |
Routability driven white space allocation for fixed-die standard-cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 42-47, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
placement, physical design, routability |
10 | Saurabh N. Adya, Igor L. Markov |
Consistent placement of macro-blocks using floorplanning and standard-cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 12-17, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Jingcao Hu, Yangdong Deng, Radu Marculescu |
System-Level Point-to-Point Communication Synthesis using Floorplanning Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 573-579, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
System-leve design, low-power, floorplanning, Communication synthesis, point-to-point communication |
10 | Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky |
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 580-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Jai-Ming Lin, Yao-Wen Chang |
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 842-847, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh |
Fast floorplanning for effective prediction and construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 341-351, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe |
Constraint-based watermarking techniques for design IP protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(10), pp. 1236-1252, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky |
Provably good global buffering by multi-terminal multicommodity flow approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 120-125, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje |
Overcoming wireload model uncertainty during physical design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 182-189, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
Optimal partitioners and end-case placers for standard-cell layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1304-1313, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Jason Cong, Xin Yuan 0005 |
Routing tree construction under fixed buffer locations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 379-384, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Yao-Wen Chang, Yu-Tsang Chang |
An architecture-driven metric for simultaneous placement and global routing for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 567-572, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov |
Function Smoothing with Applications to VLSI Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 225-, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai |
A Timing-Driven Block Placer Based on Sequence Pair Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 249-252, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
timing-driven, building block placement, sequence pair, simulated annealing algorithm |
10 | Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong |
Relaxed Simulated Tempering for VLSI Floorplan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 13-16, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Sergei L. Bezrukov, Sajal K. Das 0001, Robert Elsässer |
Optimal Cuts for Powers of the Petersen Graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WG ![In: Graph-Theoretic Concepts in Computer Science, 25th International Workshop, WG '99, Ascona, Switzerland, June 17-19, 1999, Proceedings, pp. 228-239, 1999, Springer, 3-540-66731-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
10 | Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe |
Robust IP Watermarking Methodologies for Physical Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 782-787, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
system-on-chip test, testing embedded core, intellectual property test |
10 | Majid Sarrafzadeh, Maogang Wang |
NRG: global and detailed placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 532-537, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
NRG, Global Placement, Placement, Detailed Placement |
10 | Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan |
Quadratic Placement Revisited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 752-757, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
10 | Michael J. Alexander, Gabriel Robins |
New performance-driven FPGA routing algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12), pp. 1505-1517, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
10 | Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger |
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7), pp. 890-896, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
10 | Bernard A. McCoy, Gabriel Robins |
Non-tree routing [VLSI layout]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6), pp. 780-784, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
10 | Stephen T. Frezza, Steven P. Levitan |
SPAR: a schematic place and route system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7), pp. 956-973, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
10 | Mark Hirsch, Daniel P. Siewiorek |
The effect of placement of automatically extracted structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(9), pp. 1140-1152, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
10 | Raffaele Costa, Francesco Curatelli, Daniele D. Caviglia, Giacomo M. Bisio |
Symbolic generation of constrained random logic cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(2), pp. 220-231, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
10 | Michael A. B. Jackson, Ernest S. Kuh |
Performance-driven Placement of Cell Based IC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 370-375, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
Displaying result #401 - #457 of 457 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5] |
|