Search results for "A-SSCC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta	Range pre-selection sampling technique to reduce input drive energy for SAR ADCs.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn 0003, Elad Alon, Borivoje Nikolic	A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	M. Sultan M. Siddiqui, Zhao Chuan Lee, Tony Tae-Hyoung Kim	A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Myungguk Lee, Seungho Han, Jae-Yoon Sim, Hong-June Park, Byungsub Kim	A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Long Xu, Johan H. Huijsing, Kofi A. A. Makinwa	A 10kHz-BW 93.7dB-SNR chopped ΔΣ ADC with 30V input CM range and 115dB CMRR at 10kHz.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Zhichao Tan, Khiem Nguyen, Jeff Yan, Howard Samuels, Shane Keating, Paul Crocker, Bill Clark	A dual-axis MEMS vibratory gyroscope ASIC with 0.0061°/s/VHz noise floor over 480 Hz bandwidth.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chun-Yuan Chiu, Zhen-Cheng Zhang, Tsung-Hsien Lin	A 0.6-V 200-kbps 429-MHz ultra-low-power FSK transceiver in 90-nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Tong Fang, Zhao-yang Liu, Liyuan Liu, Yuan-Yuan Li, Jun-qi Liu, Jian Liu 0021, Nanjian Wu	Detection of 3.0 THz wave with a detector in 65 nm standard CMOS process.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Sun-a Kim, Kyoung-Yong Choi, Dae-Woong Park, Joo-Myoung Kim, Seok-Kyun Han, Sang-Gug Lee 0001	0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processing.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Wei-Sung Chang, Dai-En Jhou, Yu-Hong Yang, Tai-Cheng Lee	An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique.	A-SSCC	2017	DBLP DOI BibTeX RDF
1	Chun-Ping Wang, Tai-Cheng Lee	A technique for in-band phase noise reduction in fractional-N frequency synthesizers.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Daniel DeDorigo, Yiannos Manoli	An OTA-C signal processing FPAA with 305 MHz GBW and integrated frequency-independent filter tuning.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chang-Hung Tsai, Wan-Ju Yu, Wing Hung Wong, Chen-Yi Lee	A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applications.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chih-Chan Tu, Yu-Kai Wang, Tsung-Hsien Lin	A 40-nV/VHz 0.0145-mm2 sensor readout circuit with chopped VCO-based CTDSM in 40-nm CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Jun Liu 0038, Troy Bryant, Nima Maghari, Jeffery Morroni	A 90nA quiescent current 1.5V-5V 50mA asynchronous folding LDO using dual loop control.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Hidehiro Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, Dar Sun, Shin-Rung Wu, Hung-Jen Liao, Jonathan Chang	A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Shang-Hsien Yang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai	Lossless inductor current control in envelope tracking supply modulator with self-allocation of energy for optimzation of efficiency and EVM.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Teruki Someya, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya	56-Level programmable voltage detector in steps of 50mV for battery management.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chi-Huan Chen, Hung-Chen Chen, Yu-Shyang Huang, Ping-Hsuan Hsieh, Ping-Hsien Wu, Yi-Chung Shu	A series-SSHI-Phi interface circuit for piezoelectric energy harvesting with 163% improvement in extracted power at off-resonance.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Toru Tanzawa, T. Murakoshi, T. Kamijo, Tomoharu Tanaka, J. J. McNeil, K. Duesman	Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Haikun Jia, Clarissa C. Prawoto, Baoyong Chi, Zhihua Wang 0001, C. Patrick Yue	A 32.9% PAE, 15.3 dBm, 21.6-41.6 GHz power amplifier in 65nm CMOS using coupled resonators.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Judyta Tillak, Sina Akhbari, Nimesh Shah, Ljubomir Radakovic, Liwei Lin, Jerald Yoo	A 2.34μJ/scan acoustic power scalable charge-redistribution pMUT interface system with on-chip aberration compensation for portable ultrasonic applications.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Fan Yang 0077, Hangyan Guo, Runhua Wang, Zherui Zhang, Junhua Liu, Huailin Liao	A low-power calibration-free fractional-N digital PLL with high linear phase interpolator.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Zhijie Chen, Masaya Miyahara, Akira Matsuzawa	A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Yuan Ren, Sai-Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins	A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders 0001, Gregory K. Chen, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001, Vivek De	A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Yosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura	20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada	A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Sung-Geun Kim, Tongsung Kim, Dae Hyun Kwon, Woo-Young Choi	A 5-8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Masayoshi Oshiro, Tatsuhiko Maruyama, Takashi Tokairin, Yuki Tuda, Tong Wang 0018, Naotaka Koide, Yosuke Ogasawara, Tuan Thanh Ta, Hiroshi Yoshida, Kenichi Sami	A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, Mingoo Seok	Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Kyoungjin Lee, Haneul Kim, Jehyung Yoon, Hyoung-Seok Oh, Byeong-Ha Park, Ho-Jin Park, Yoonmyung Lee	A high efficiency wide-load-range asynchronous boost converter with time-based dual-mode control for SSD applications.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Lilan Yu, Masaya Miyahara, Akira Matsuzawa	A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Wei Jin 0004, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok	A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Seongrim Choi, Jaemin Hwang, Suhwan Cho, Ara Kim, Byeong-Gyu Nam	A low-power real-time hidden Markov model accelerator for gesture user interface on wearable devices.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Zhe Chen, Hao Gao 0001, Domine M. W. Leenaerts, Dusan M. Milosevic, Peter G. M. Baltus	A 16-43 GHz low-noise amplifer with 2.5-4.0 dB noise figure.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Xiaolong Liu, Chixiao Chen, Junyan Ren, Howard C. Luong	Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Daniel Bankman, Boris Murmann	An 8-bit, 16 input, 3.2 pJ/op switched-capacitor dot product circuit in 28-nm FDSOI CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Rui Wu 0001, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa	An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chen-Fan Tang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai	Ultra-low voltage ripple in DC-DC boost converter by the pumping capacitor and wire inductance technique.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Majid Jalalifar, Gyung-Su Byun	A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Yao-Sheng Hu, Po-Chao Huang, Mi-Ti Yang, Shih-Wei Wu, Hsin-Shu Chen	A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chi-Hang Chan, Yan Zhu 0001, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, Seng-Pan U, Rui Paulo Martins	A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa	A 0.38-μW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery management.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Young-Ho Choi, Kihwan Seong, Byungsub Kim, Jae-Yoon Sim, Hong-June Park	All-synthesizable 6Gbps voltage-mode transmitter for serial link.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Xuqiang Zheng, Chun Zhang, Shuai Yuan 0005, Feng Zhao 0004, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang 0001	An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Masum Hossain, Amlan Nag, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb	Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Hyuk Sun, Jason Muhlestein, Spencer Leuenberger, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon	A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Si Chen, Boris Murmann	An 8-bit 1.25GS/s CMOS IF-sampling ADC with background calibration for dynamic distortion.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Junichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda	An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Martin Cochet, Alberto Puggelli, Ben Keller, Brian Zimmer, Milovan Blagojevic, Sylvain Clerc, Philippe Roche, Jean-Luc Autran, Borivoje Nikolic	On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Lei Yao, I. Made Darmayuda, Yuan Gao 0011	A 83% peak efficiency 1.65 V to 11.4V dynamic voltage scaling supply for electrical stimulation applications in standard 0.18μm CMOS process.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, André Bourdoux, Piet Wambacq, Wim Van Thillo	A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou	A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Yanxiang Huang, Chunshu Li, Khaled Khalaf, André Bourdoux, Julien Verschueren, Qixian Shi, Piet Wambacq, Sofie Pollin, Wim Dehaene, Liesbet Van der Perre	A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Yining Zhang, Ranran Zhou, Woogeun Rhee, Zhihua Wang 0001	A 1.9mW 750kb/s 2.4GHz F-OOK transmitter with symmetric FM template and high-point modulation PLL.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Hugo Cruz, Shuenn-Yuh Lee, Ching-Hsing Luo	A 13.56 MHz, 162 mW magnetically coupled digital rectifier with 94% VCR, 96% PCE over 50-to-5k Ω load range, and embedded 80 kbps DBPSK demodulator for biomedical applications.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Sungpill Choi, Seongwook Park, Hoi-Jun Yoo	A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interface.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Beichen Zhang, Runjiang Dou, Liyuan Liu, Nanjian Wu	A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolic, Krste Asanovic	Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Jongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim	Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Unsoo Ha, Hoi-Jun Yoo	An EEG-NIRS ear-module SoC for wearable drowsiness monitoring system.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Abhik Das, Yuan Gao 0011, Tony T. Kim	An isolated PoR based pulse generator for TEG energy harvesting with minimum startup of 150 mV and maximum series resistance of 600 Ω.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Babak Mohammadi, Oskar Andersson, Xiao Luo, Masoud Nouripayam, Joachim Neves Rodrigues	An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Takuji Miki, Toshiaki Ozeki, Jun-ichi Naka	A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Yao-Sheng Hu, Kai-Yue Lin, Hsin-Shu Chen	A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii	A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee	A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chao Wang 0016, Jianmin Zhang, Jun Zhou 0017, Xin Liu 0015, Ru San Tan, Liang Zhong, Kevin T. C. Chai	A 65-nm 0.35-V 7.1-μW memory-less adaptive PCG processor for wearable long-term cardiac monitoring.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun 0001	A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Kwuang-Han Chang, Chih-Cheng Hsieh	A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Shao-Wei Chiu, Chun-Chieh Kuo, Kai-Cheng Chuang, Wen-Hau Yang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai, Jui-Lung Chen	93% Efficiency and 0.99 power factor in pseudo-linear LED driver.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Pi-Feng Chiu, Brian Zimmer, Borivoje Nikolic	A double-tail sense amplifier for low-voltage SRAM in 28nm technology.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Daisuke Miyashita, Shouhei Kousai, Tomoya Suzuki, Jun Deguchi	Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Giacomo Pini, Danilo Manstretta, Rinaldo Castello	Highly linear TIA for SAW-less FDD receivers.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Mark Maddox, Baozhen Chen, Michael C. W. Coln, Ron Kapusta, Junhua Shen, Lalinda Fernando	A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Vishal Vinayak Kulkarni, Wei Yi Lim, Bin Zhao, Dan Lei Yan, Yu-Shun Wang, Jun Zhou 0017, Muthukumaraswamy Annamalai Arasu	A 5.1Gb/s 60.3fJ/bit/mm PVT tolerant NoC transceiver.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Waleed El-Halwagy, Pedram Mousavi, Masum Hossain	A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDC.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Manabu Yamada, Nam Binh Tran, Takayuki Miyazaki, Yoshiaki Yoshihara, Ryuichi Fujimoto	All-digital single-inductor multiple-output DC-DC converter with over 65.3% efficiency in 1 uW to 50 mW load range and 86.3% peak efficiency.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Dong-Soo Lee, SeongJin Oh, Sung-Jin Kim, CheolHo Lee, ChangHun Song, Jungyeon Kim, WooSeob Kim, HongJin Kim, Sang-Sun Yoo, Sukkyun Hong, Jeong-Woo Lee, YoungGun Pu, Kang-Yoon Lee	Low power FSK transceiver using ADPLL with direct modulation and integrated SPDT for BLE application.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chun-Yu Lin 0002, Tsung-Hsien Lin	A 4-GHz ΔΣ fractional-N frequency synthesizer with 2-dimensional quantization noise pushing and fractional spur elimination techniques.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Lei Qiu 0002, Kai Tang 0002, Yan Zhu 0001, Liter Siek, Yuanjin Zheng, Seng-Pan U	A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Jeffrey Prinzie, Michiel Steyaert, Paul Leroux, Jorgen Christiansen, Paulo Moreira	A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Taehwan Kim, Pavan Bhargava, Vladimir Stojanovic	A model predictive control equalization transmitter for asymmetric interfaces in 28nm FDSOI.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Tsung-Chih Hung, Tai-Haur Kuo	A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ken Chang	A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan	Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chih-Chan Tu, Kuan-Chung Chen, Tsung-Yu Wu, Tsung-Hsien Lin	An area-efficient wideband CMOS hall sensor system for camera autofocus systems.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Masato Tamura, Makoto Ikeda	1.68μJ/signature-generation 256-bit ECDSA over GF(p) signature generator for IoT devices.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Quoc-Hoang Duong, Jeong-Woon Kong, Hyeon-Seok Shin, Huy-Hieu Nguyen, Pan-Jong Kim, Yu-Seok Ko, Hwa-Yeoul Yu, Ho-Jin Park	Multiple-loop design technique for high-performance low dropout regulator.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Hyunui Lee, Sukyong Kang, Hye-Seung Yu, Won-Joo Yun, Jae-Hun Jung, Sungoh Ahn, Wang-Soo Kim, Beomyong Kil, Yoo-Chang Sung, Sang-Hoon Shin, Yong-Sik Park, Yong-Hwan Kim, Kyung-Woo Nam, Indal Song, Kyomin Sohn, Yong-Cheol Bae, Jung-Hwan Choi, Seong-Jin Jang, Gyo-Young Jin	Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim	A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Yin-Jyun Hu, I-Chou Chen, Tsung-Heng Tsai	A piezoelectric vibration energy harvesting system with improved power extraction capability.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Hui-Hsuan Lee, Po-Hung Chen	A single-inductor dual-input dual-output (SIDIDO) power management with sequential pulse-skip modulation for battery/PV hybrid systems.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Kuan-Lin Liu, Chih-Cheng Hsieh, Sheng-Yeh Lai, Chin-Fong Chiu	A time delay multiple integration linear CMOS image sensor for multispectral satellite telemetry.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Woo-Rham Bae, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong	A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Bingwei Jiang, Chixiao Chen, Junyan Ren, Howard C. Luong	A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Chi-Huan Chiang, Chang-Cheng Huang, Ting-Kuei Kuan, Shen-Iuan Liu	A digital MDLL using switched biasing technique to reduce low-frequency phase noise.	A-SSCC	2016	DBLP DOI BibTeX RDF
1	Albert Yen-Chih Chiou, Sung-En Hsieh, Yan-Quan Pan, Chia-Chi Kuo, Chih-Cheng Hsieh	An integrated CMOS optical sensing chip for multiple bio-signal detections.	A-SSCC	2016	DBLP DOI BibTeX RDF
1		IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016	A-SSCC	2016	DBLP BibTeX RDF

Publications at "A-SSCC"( http://dblp.L3S.de/Venues/A-SSCC )