Search results for "ASICs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi	Exploring Logic Block Granularity for Regular Fabrics.	DATE	2004	DBLP DOI BibTeX RDF
10	Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey	Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor.	DATE	2004	DBLP DOI BibTeX RDF
10	Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai	A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications.	DATE	2004	DBLP DOI BibTeX RDF
10	Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel	High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells.	ASYNC	2004	DBLP DOI BibTeX RDF
10	Michael Ullmann, Michael Hübner 0001, Björn Grimm, Jürgen Becker 0001	On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.	FPL	2004	DBLP DOI BibTeX RDF
10	Mike Hutton	Advances and trends in FPGA design.	SBCCI	2004	DBLP DOI BibTeX RDF
10	Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda	Design methodology and tools for NEC electronics' structured ASIC ISSP.	ISPD	2004	DBLP DOI BibTeX RDF	ISSP, placement, structured ASIC, regular fabric
10	Ulrich Brenner, Anna Pauli, Jens Vygen	Almost optimum placement legalization by minimum cost flow and dynamic programming.	ISPD	2004	DBLP DOI BibTeX RDF	placement, legalization, minimum-cost flow, detailed placement
10	Erland Nilsson, Johnny Öberg	Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	hot-potato, pseudochronous, network on chip, mesh, clocking, GALS, GPLS
10	Abraham Duarte, Felipe Fernández, Ángel Sánchez 0001, Antonio S. Montemayor	A Hierarchical Social Metaheuristic for the Max-Cut Problem.	EvoCOP	2004	DBLP DOI BibTeX RDF
10	Jie Guo 0007, Michael Hosemann, Gerhard P. Fettweis	Employing Compilers for Determining Architectural Features of Application-Specific DSPs.	PARELEC	2004	DBLP DOI BibTeX RDF
10	Bin Wu, Jianwen Zhu, Farid N. Najm	Dynamic range estimation for nonlinear systems.	ICCAD	2004	DBLP DOI BibTeX RDF
10	Lei Cheng 0001, Martin D. F. Wong	Floorplan design for multi-million gate FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
10	Steve Carr 0001, Philip H. Sweany	Automatic data partitioning for the agere payload plus network processor.	CASES	2004	DBLP DOI BibTeX RDF	scheduling, partitioning, network processors
10	Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini	A comparison between mask- and field-programmable routing structures on industrial FPGA architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	mask-programmable, FPGA, routing, interconnect architectures
10	Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat	Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications.	ITCC (2)	2004	DBLP DOI BibTeX RDF	compact encryption/decryption implementation, FPGA, Cryptography, AES, DES
10	Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware	Detection of Temperature Sensitive Defects Using ZTC.	VTS	2004	DBLP DOI BibTeX RDF
10	Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu	34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System.	ITC	2004	DBLP DOI BibTeX RDF
10	Robert Madge	ATE Value Add through Open Data Collection.	ITC	2004	DBLP DOI BibTeX RDF
10	Lin Yuan, Pushkin R. Pari, Gang Qu 0001	Soft IP Protection: Watermarking HDL Codes.	Information Hiding	2004	DBLP DOI BibTeX RDF
10	Aman Kokrady, C. P. Ravikumar	Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures.	VLSI Design	2004	DBLP DOI BibTeX RDF	Timing Failure, Test Validation, Crosstalk, At Speed Testing, IR Drop
10	Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto	A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong	Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.	ISCA	2004	DBLP DOI BibTeX RDF
10	Bin Wu, Jianwen Zhu, Farid N. Najm	An analytical approach for dynamic range estimation.	DAC	2004	DBLP DOI BibTeX RDF	Karhunen-Loeve Expansion (KLE), correlation, dynamic range, bitwidth
10	Mark Hopkins	Nomadic platform approach for wireless mobile multimedia.	DAC	2004	DBLP DOI BibTeX RDF
10	Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, Gerhard Tröster	The case for reconfigurable hardware in wearable computing.	Pers. Ubiquitous Comput.	2003	DBLP DOI BibTeX RDF	Body area computing system, Field-programmable gate arrays, Embedded systems, Wearable computing, Reconfigurable hardware
10	Kerem Karadayi, Vishal Markandey, Jeremiah Golston, Robert J. Gove, Yongmin Kim 0001	Strategies for Mapping Algorithms to Mediaprocessors for High Performance.	IEEE Micro	2003	DBLP DOI BibTeX RDF
10	Amit Singh 0001, Arindam Mukherjee 0001, Luca Macchiarulo, Malgorzata Marek-Sadowska	PITIA: an FPGA for throughput-intensive applications.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Saurabh N. Adya, Igor L. Markov	Fixed-outline floorplanning: enabling hierarchical design.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	M. A. Azadpour, T. S. Kalkur	A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Seonil Choi, Ju-wook Jang, Sumit Mohanty, Viktor K. Prasanna	Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	FPGA, energy optimization, domain-specific modeling, energy estimation
10	Nikil D. Dutt, Kiyoung Choi	Configurable Processors for Embedded Computing.	Computer	2003	DBLP DOI BibTeX RDF
10	Qin Zhao, Bart Mesman, Twan Basten	Static resource models for code-size efficient embedded processors.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	Static resource models, phase coupling, scheduling, convex hull, constraint analysis
10	Lijun Gao, Keshab K. Parhi, Jun Ma	Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	relaxed weight-update, relaxed annihilation-reordering look-ahead, hardware mapping, QRD-RLS adaptive filter, filtering approximation, low area, low power, high-speed, beamformer, CORDIC, Givens rotation
10	Aditya Agrawal, Ákos Lédeczi	Multigranular Simulation of Heterogeneous Embedded Systems.	ECBS	2003	DBLP DOI BibTeX RDF
10	Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou	Energy Recovering ASIC Design.	ISVLSI	2003	DBLP DOI BibTeX RDF
10	Katarzyna Leijten-Nowak, Jef L. van Meerbergen	An FPGA architecture with enhanced datapath functionality.	FPGA	2003	DBLP DOI BibTeX RDF	adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry
10	Gregor Papa, Jurij Silc	Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique.	DSD	2003	DBLP DOI BibTeX RDF
10	Andrew Royal, Peter Y. K. Cheung	Globally Asynchronous Locally Synchronous FPGA Architectures.	FPL	2003	DBLP DOI BibTeX RDF
10	Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit	Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.	FPL	2003	DBLP DOI BibTeX RDF
10	Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011	Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.	FPL	2003	DBLP DOI BibTeX RDF
10	Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer 0003	An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF	re-configurable architecture, hardware testbenches, acceleration of functional simulation, coarse-granular, fine-granular
10	Patrick Murphy, J. Patrick Frantz, Erik Welsh, Ricky Hardy, Tinoosh Mohsenin, Joseph R. Cavallaro	VALID: Custom ASIC Verification and FPGA Education Platform.	MSE	2003	DBLP DOI BibTeX RDF
10	Rolf Drechsler, Nicole Drechsler	GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages.	EvoWorkshops	2003	DBLP DOI BibTeX RDF
10	Krishna Sekar, Kanishka Lahiri, Sujit Dey	Dynamic Platform Management for Configurable Platform-Based System-on-Chips.	ICCAD	2003	DBLP DOI BibTeX RDF	ASIC
10	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.	ICCAD	2003	DBLP DOI BibTeX RDF
10	David Goodwin, Darin Petkov	Automatic generation of application specific processors.	CASES	2003	DBLP DOI BibTeX RDF	automatic instruction-set generation, ASIPs, configurable processors, extensible processors
10	Matthias Frey, Hans-Andrea Loeliger, Felix Lustenberger, Patrick R. Merkli, Patrik Strebel	Analog-decoder experiments with subthreshold CMOS soft-gates.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Gleb A. Chuvpilo, Saman P. Amarasinghe	High-Bandwidth Packet Switching on the Raw General-Purpose Architecture.	ICPP	2003	DBLP DOI BibTeX RDF
10	Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger	A Case Study of IR-Drop in Structured At-Speed Testing.	ITC	2003	DBLP DOI BibTeX RDF
10	Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar	Extending Platform-Based Design to Network on Chip Systems.	VLSI Design	2003	DBLP DOI BibTeX RDF
10	M. Josie Ammer, Michael Sheets, Tufan C. Karalar, Mika Kuulusa, Jan M. Rabaey	A low-energy chip-set for wireless intercom.	DAC	2003	DBLP DOI BibTeX RDF	low power, wireless communication, design methodology
10	Murali Kudlugi, Russell Tessier	Static scheduling of multidomain circuits for fast functional verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Chunhong Chen, Majid Sarrafzadeh	Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis.	DATE	2002	DBLP DOI BibTeX RDF
10	Sudhakar Yalamanchili	The Customization Landscape for Embedded Systems.	HiPC	2002	DBLP DOI BibTeX RDF
10	Aneesh Koorapaty, Lawrence T. Pileggi	Modular, Fabric-Specific Synthesis for Programmable Architectures.	FPL	2002	DBLP DOI BibTeX RDF
10	Hooman Parizi, Afshin Niktash, Nader Bagherzadeh, Fadi J. Kurdahi	MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
10	M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha	A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.	ISSS	2002	DBLP DOI BibTeX RDF	Trimaran, performance, design space exploration, VLIW, ASIP
10	Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu	Validation in a Component-Based Design Flow for Multicore SoCs.	ISSS	2002	DBLP DOI BibTeX RDF	validation, SoC, abstraction levels, component-based design, cosimulation
10	Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh	Design Tools for Application Specific Embedded Processors.	EMSOFT	2002	DBLP DOI BibTeX RDF
10	Pasquale Cocchini	Concurrent flip-flop and repeater insertion for high performance integrated circuits.	ICCAD	2002	DBLP DOI BibTeX RDF
10	Akashi Satoh, Sumio Morioka	Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI.	ISC	2002	DBLP DOI BibTeX RDF
10	Christophe Bobda, Nils Steenbock	A Rapid Prototyping Environment for Distributed Reconfigurable Systems.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
10	Kurt Keutzer, Sharad Malik, A. Richard Newton	From ASIC to ASIP: The Next Design Discontinuity.	ICCD	2002	DBLP DOI BibTeX RDF	Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP
10	Dae Woon Kang, Yong-Bin Kim	Design flow of robust routed power distribution for low power ASIC.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
10	Keith S. Vallerio, Niraj K. Jha	Task graph transformation to aid system synthesis.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
10	Xiaojuan Hu, Linda DeBrunner, Victor E. DeBrunner	An efficient design for FIR filters with variable precision.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
10	Holger Blume, H. Hübert, H. T. Feldkämper, Tobias G. Noll	Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip.	ASAP	2002	DBLP DOI BibTeX RDF
10	Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele	Reconfigurable Hardware in Wearable Computing Nodes.	ISWC	2002	DBLP DOI BibTeX RDF
10	Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur	Integrating DFT in the Physical Synthesis Flow.	ITC	2002	DBLP DOI BibTeX RDF
10	Timothe Litt	Support for Debugging in the Alpha 21364 Microprocessor.	ITC	2002	DBLP DOI BibTeX RDF
10	Felix Schürmann, Steffen G. Hohmann, Johannes Schemmel, Karlheinz Meier	Towards an Artificial Neural Network Framework.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
10	Rahul Kumar, C. P. Ravikumar	Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Power Estimation, Leakage Power, Linear Regression, Deep Submicron
10	Jiong Luo, Niraj K. Jha	Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	scheduling, real-time systems, embedded systems, low-power
10	Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri	Improvement of ASIC Design Processes.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
10	Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia	On Routing Demand and Congestion Estimation for FPGAs.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
10	Adrian K. Lutz, Jürg Treichler, Frank K. Gürkaynak, Hubert Kaeslin, Gérard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner	2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis.	CHES	2002	DBLP DOI BibTeX RDF
10	Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta	A physical design tool for built-in self-repairable RAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
10	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO: regular expression-based register-transfer level testability analysis and optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
10	Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl	Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
10	Pawel Chodowiec, Po Khuon, Kris Gaj	Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining.	FPGA	2001	DBLP DOI BibTeX RDF	fast architectures, secret-key ciphers, pipelining, AES
10	Steven J. E. Wilton	A crosstalk-aware timing-driven router for FPGAs.	FPGA	2001	DBLP DOI BibTeX RDF	field-programmable gate arrays, routing algorithms, crosstalk
10	PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia	fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits.	FPL	2001	DBLP DOI BibTeX RDF
10	Rajeev Jayaraman	Physical design for FPGAs.	ISPD	2001	DBLP DOI BibTeX RDF	FPGA, routing, placement, physical design
10	Richard E. Haskell, Darrin M. Hanna	FPGA Integrated Co-Design.	MSE	2001	DBLP DOI BibTeX RDF
10	Kostas Marinis, Nikos K. Moshopoulos, Fotis Karoubalis, Kiamal Z. Pekmestzi	On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms.	ISC	2001	DBLP DOI BibTeX RDF
10	Christophe Bobda, Nils Steenbock	Singular Value Decomposition on Distributed Reconfigurable Systems.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
10	Sebastian Meine	A Holarchical Organized Design Assistant for Hierarchical Decompositions.	EUROCAST	2001	DBLP DOI BibTeX RDF
10	Michael Affenzeller, Franz Pichler, Rudolf Mittelmann	On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata.	EUROCAST	2001	DBLP DOI BibTeX RDF
10	Tom Egan, Samiha Mourad	Verification of Embedded Phase-Locked Loops.	ISQED	2001	DBLP DOI BibTeX RDF
10	Josef Schmid, Timo Schüring, Christoph Smalla	Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow.	ISQED	2001	DBLP DOI BibTeX RDF
10	Aravind Dasu, Sethuraman Panchanathan	Reconfigurable Media Processing.	ITCC	2001	DBLP DOI BibTeX RDF
10	Chris Basoglu, Woobin Lee, John Setel O'Donnell	The MAP1000A VLIW Mediaprocessor.	IEEE Micro	2000	DBLP DOI BibTeX RDF
10	Akio Koyama, Makio Uchida, Tatsuhiro Aida, Jun'ya Kudo, Masatoshi Tsuge	Switching well noise modeling and minimization strategy for digitalcircuits with a controllable threshold voltage scheme.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	Shantanu Tarafdar, Miriam Leeser	A data-centric approach to high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess	A code-motion pruning technique for global scheduling.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	high-level synthesis, code generation, speculative execution, code motion, global scheduling
10	Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pegatoquet	A codesign back-end approach for embedded system design.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	HW/SW integration, template architecture, codesign, communications synthesis
10	S. Ramanathan, S. K. Nandy 0001, V. Visvanathan	Reconfigurable Filter Coprocessor Architecture for DSP Applications.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures
10	Amit Singh 0001, Luca Macchiarulo, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	A novel high throughput reconfigurable FPGA architecture.	FPGA	2000	DBLP DOI BibTeX RDF
10	Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam	The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches.	HPCA	2000	DBLP DOI BibTeX RDF	texture mapping, Cache memories, parallel rendering, multiprocessing, application specific architecture