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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 618 occurrences of 392 keywords
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Results
Found 665 publication records. Showing 665 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
10 | Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi |
Exploring Logic Block Granularity for Regular Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 468-473, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey |
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 162-167, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai |
A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 280-285, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel |
High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 95-105, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Michael Ullmann, Michael Hübner 0001, Björn Grimm, Jürgen Becker 0001 |
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 454-463, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Mike Hutton |
Advances and trends in FPGA design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 8, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda |
Design methodology and tools for NEC electronics' structured ASIC ISSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 90-96, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ISSP, placement, structured ASIC, regular fabric |
10 | Ulrich Brenner, Anna Pauli, Jens Vygen |
Almost optimum placement legalization by minimum cost flow and dynamic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 2-9, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
placement, legalization, minimum-cost flow, detailed placement |
10 | Erland Nilsson, Johnny Öberg |
Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 176-181, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hot-potato, pseudochronous, network on chip, mesh, clocking, GALS, GPLS |
10 | Abraham Duarte, Felipe Fernández, Ángel Sánchez 0001, Antonio S. Montemayor |
A Hierarchical Social Metaheuristic for the Max-Cut Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoCOP ![In: Evolutionary Computation in Combinatorial Optimization, 4th European Conference, EvoCOP 2004, Coimbra, Portugal, April 5-7, 2004, Proceedings, pp. 84-94, 2004, Springer, 3-540-21367-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Jie Guo 0007, Michael Hosemann, Gerhard P. Fettweis |
Employing Compilers for Determining Architectural Features of Application-Specific DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 7-10 September 2004, Dresden, Germany, pp. 39-44, 2004, IEEE Computer Society, 0-7695-2080-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Bin Wu, Jianwen Zhu, Farid N. Najm |
Dynamic range estimation for nonlinear systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 660-667, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Lei Cheng 0001, Martin D. F. Wong |
Floorplan design for multi-million gate FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 292-299, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Steve Carr 0001, Philip H. Sweany |
Automatic data partitioning for the agere payload plus network processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 238-247, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
scheduling, partitioning, network processors |
10 | Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini |
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 436-439, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
mask-programmable, FPGA, routing, interconnect architectures |
10 | Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat |
Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (2) ![In: International Conference on Information Technology: Coding and Computing (ITCC'04), Volume 2, April 5-7, 2004, Las Vegas, Nevada, USA, pp. 583-587, 2004, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
compact encryption/decryption implementation, FPGA, Cryptography, AES, DES |
10 | Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware |
Detection of Temperature Sensitive Defects Using ZTC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 185-192, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu |
34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1255-1262, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Robert Madge |
ATE Value Add through Open Data Collection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1430, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Lin Yuan, Pushkin R. Pari, Gang Qu 0001 |
Soft IP Protection: Watermarking HDL Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Information Hiding ![In: Information Hiding, 6th International Workshop, IH 2004, Toronto, Canada, May 23-25, 2004, Revised Selected Papers, pp. 224-238, 2004, Springer, 3-540-24207-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Aman Kokrady, C. P. Ravikumar |
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 597-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Timing Failure, Test Validation, Crosstalk, At Speed Testing, IR Drop |
10 | Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto |
A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 1083-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong |
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 150-161, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Bin Wu, Jianwen Zhu, Farid N. Najm |
An analytical approach for dynamic range estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 472-477, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Karhunen-Loeve Expansion (KLE), correlation, dynamic range, bitwidth |
10 | Mark Hopkins |
Nomadic platform approach for wireless mobile multimedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 408, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, Gerhard Tröster |
The case for reconfigurable hardware in wearable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pers. Ubiquitous Comput. ![In: Pers. Ubiquitous Comput. 7(5), pp. 299-308, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Body area computing system, Field-programmable gate arrays, Embedded systems, Wearable computing, Reconfigurable hardware |
10 | Kerem Karadayi, Vishal Markandey, Jeremiah Golston, Robert J. Gove, Yongmin Kim 0001 |
Strategies for Mapping Algorithms to Mediaprocessors for High Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 23(4), pp. 58-70, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Amit Singh 0001, Arindam Mukherjee 0001, Luca Macchiarulo, Malgorzata Marek-Sadowska |
PITIA: an FPGA for throughput-intensive applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 354-363, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Saurabh N. Adya, Igor L. Markov |
Fixed-outline floorplanning: enabling hierarchical design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 1120-1135, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | M. A. Azadpour, T. S. Kalkur |
A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 1143-1146, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Seonil Choi, Ju-wook Jang, Sumit Mohanty, Viktor K. Prasanna |
Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 26(3), pp. 259-281, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA, energy optimization, domain-specific modeling, energy estimation |
10 | Nikil D. Dutt, Kiyoung Choi |
Configurable Processors for Embedded Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 36(1), pp. 120-123, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Qin Zhao, Bart Mesman, Twan Basten |
Static resource models for code-size efficient embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 2(2), pp. 219-250, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Static resource models, phase coupling, scheduling, convex hull, constraint analysis |
10 | Lijun Gao, Keshab K. Parhi, Jun Ma |
Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 35(2), pp. 119-135, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
relaxed weight-update, relaxed annihilation-reordering look-ahead, hardware mapping, QRD-RLS adaptive filter, filtering approximation, low area, low power, high-speed, beamformer, CORDIC, Givens rotation |
10 | Aditya Agrawal, Ákos Lédeczi |
Multigranular Simulation of Heterogeneous Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 10th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2003), 7-10 April 2003, Huntsville, AL, USA, pp. 3-10, 2003, IEEE Computer Society, 0-7695-1917-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou |
Energy Recovering ASIC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 133-138, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Katarzyna Leijten-Nowak, Jef L. van Meerbergen |
An FPGA architecture with enhanced datapath functionality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 195-204, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry |
10 | Gregor Papa, Jurij Silc |
Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 430-433, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Andrew Royal, Peter Y. K. Cheung |
Globally Asynchronous Locally Synchronous FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 355-364, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit |
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 426-436, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011 |
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 21-30, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer 0003 |
An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 187, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
re-configurable architecture, hardware testbenches, acceleration of functional simulation, coarse-granular, fine-granular |
10 | Patrick Murphy, J. Patrick Frantz, Erik Welsh, Ricky Hardy, Tinoosh Mohsenin, Joseph R. Cavallaro |
VALID: Custom ASIC Verification and FPGA Education Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 64-65, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Rolf Drechsler, Nicole Drechsler |
GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshop 2003: EvoBIO, EvoCOP, EvoIASP, EvoMUSART, EvoROB, and EvoSTIM, Essex, UK, April 14-16, 2003, Proceedings, pp. 378-387, 2003, Springer, 3-540-00976-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
Dynamic Platform Management for Configurable Platform-Based System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 641-649, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ASIC |
10 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 46-53, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | David Goodwin, Darin Petkov |
Automatic generation of application specific processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 137-147, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
automatic instruction-set generation, ASIPs, configurable processors, extensible processors |
10 | Matthias Frey, Hans-Andrea Loeliger, Felix Lustenberger, Patrick R. Merkli, Patrik Strebel |
Analog-decoder experiments with subthreshold CMOS soft-gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 85-88, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Gleb A. Chuvpilo, Saman P. Amarasinghe |
High-Bandwidth Packet Switching on the Raw General-Purpose Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 32nd International Conference on Parallel Processing (ICPP 2003), 6-9 October 2003, Kaohsiung, Taiwan, pp. 3-10, 2003, IEEE Computer Society, 0-7695-2017-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger |
A Case Study of IR-Drop in Structured At-Speed Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1098-1104, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar |
Extending Platform-Based Design to Network on Chip Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 401-, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | M. Josie Ammer, Michael Sheets, Tufan C. Karalar, Mika Kuulusa, Jan M. Rabaey |
A low-energy chip-set for wireless intercom. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 916-919, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low power, wireless communication, design methodology |
10 | Murali Kudlugi, Russell Tessier |
Static scheduling of multidomain circuits for fast functional verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11), pp. 1253-1268, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Chunhong Chen, Majid Sarrafzadeh |
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1016-1020, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Sudhakar Yalamanchili |
The Customization Landscape for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 693-696, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Aneesh Koorapaty, Lawrence T. Pileggi |
Modular, Fabric-Specific Synthesis for Programmable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 132-141, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Hooman Parizi, Afshin Niktash, Nader Bagherzadeh, Fadi J. Kurdahi |
MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2002, Parallel Processing, 8th International Euro-Par Conference Paderborn, Germany, August 27-30, 2002, Proceedings, pp. 844-848, 2002, Springer, 3-540-44049-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha |
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 2-7, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Trimaran, performance, design space exploration, VLIW, ASIP |
10 | Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu |
Validation in a Component-Based Design Flow for Multicore SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 162-167, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
validation, SoC, abstraction levels, component-based design, cosimulation |
10 | Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh |
Design Tools for Application Specific Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Embedded Software, Second International Conference, EMSOFT 2002, Grenoble, France, October 7-9, 2002, Proceedings, pp. 319-333, 2002, Springer, 3-540-44307-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Pasquale Cocchini |
Concurrent flip-flop and repeater insertion for high performance integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 268-273, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Akashi Satoh, Sumio Morioka |
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Information Security, 5th International Conference, ISC 2002 Sao Paulo, Brazil, September 30 - October 2, 2002, Proceedings, pp. 48-62, 2002, Springer, 3-540-44270-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Christophe Bobda, Nils Steenbock |
A Rapid Prototyping Environment for Distributed Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 1-3 July 2002, Darmstadt, Germany, pp. 153-158, 2002, IEEE Computer Society, 0-7695-1703-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Kurt Keutzer, Sharad Malik, A. Richard Newton |
From ASIC to ASIP: The Next Design Discontinuity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 84-90, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP |
10 | Dae Woon Kang, Yong-Bin Kim |
Design flow of robust routed power distribution for low power ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 181-184, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Keith S. Vallerio, Niraj K. Jha |
Task graph transformation to aid system synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 695-698, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Xiaojuan Hu, Linda DeBrunner, Victor E. DeBrunner |
An efficient design for FIR filters with variable precision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 365-368, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Holger Blume, H. Hübert, H. T. Feldkämper, Tobias G. Noll |
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 29-40, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele |
Reconfigurable Hardware in Wearable Computing Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISWC ![In: 6th International Symposium on Wearable Computers (ISWC 2002), 7-10 October 2002, Seattle, WA, USA, pp. 215-222, 2002, IEEE Computer Society, 0-7695-1816-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur |
Integrating DFT in the Physical Synthesis Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 788-795, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Timothe Litt |
Support for Debugging in the Alpha 21364 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 584-589, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Felix Schürmann, Steffen G. Hohmann, Johannes Schemmel, Karlheinz Meier |
Towards an Artificial Neural Network Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 15-18 July 2002, Alexandria, VA, USA, pp. 266-273, 2002, IEEE Computer Society, 0-7695-1718-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Rahul Kumar, C. P. Ravikumar |
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 45-50, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Power Estimation, Leakage Power, Linear Regression, Deep Submicron |
10 | Jiong Luo, Niraj K. Jha |
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 719-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scheduling, real-time systems, embedded systems, low-power |
10 | Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri |
Improvement of ASIC Design Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 105-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia |
On Routing Demand and Congestion Estimation for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 639-646, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Adrian K. Lutz, Jürg Treichler, Frank K. Gürkaynak, Hubert Kaeslin, Gérard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner |
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers, pp. 144-158, 2002, Springer, 3-540-00409-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta |
A physical design tool for built-in self-repairable RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 352-364, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO: regular expression-based register-transfer level testability analysis and optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 824-832, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl |
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 899-912, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Pawel Chodowiec, Po Khuon, Kris Gaj |
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 94-102, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fast architectures, secret-key ciphers, pipelining, AES |
10 | Steven J. E. Wilton |
A crosstalk-aware timing-driven router for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 21-28, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, routing algorithms, crosstalk |
10 | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia |
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 37-47, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Rajeev Jayaraman |
Physical design for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 214-221, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGA, routing, placement, physical design |
10 | Richard E. Haskell, Darrin M. Hanna |
FPGA Integrated Co-Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2001 International Conference on Microelectronics Systems Education, MSE 2001, Las Vegas, NV, USA, July 17-18, 2001, pp. 30-31, 2001, IEEE Computer Society, 0-7695-1156-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Kostas Marinis, Nikos K. Moshopoulos, Fotis Karoubalis, Kiamal Z. Pekmestzi |
On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Information Security, 4th International Conference, ISC 2001, Malaga, Spain, October 1-3, 2001, Proceedings, pp. 248-265, 2001, Springer, 3-540-42662-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Christophe Bobda, Nils Steenbock |
Singular Value Decomposition on Distributed Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 25-27 June 2001, Monterey, CA, USA, pp. 38-43, 2001, IEEE Computer Society, 0-7695-1206-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Sebastian Meine |
A Holarchical Organized Design Assistant for Hierarchical Decompositions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2001, Las Palmas de Gran Canaria, Spain, February 19-23, 2001, Revised Papers, pp. 45-51, 2001, Springer, 3-540-42959-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Michael Affenzeller, Franz Pichler, Rudolf Mittelmann |
On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2001, Las Palmas de Gran Canaria, Spain, February 19-23, 2001, Revised Papers, pp. 36-44, 2001, Springer, 3-540-42959-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Tom Egan, Samiha Mourad |
Verification of Embedded Phase-Locked Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 290-295, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Josef Schmid, Timo Schüring, Christoph Smalla |
Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 337-342, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Aravind Dasu, Sethuraman Panchanathan |
Reconfigurable Media Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC ![In: 2001 International Symposium on Information Technology (ITCC 2001), 2-4 April 2001, Las Vegas, NV, USA, pp. 300-, 2001, IEEE Computer Society, 0-7695-1062-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Chris Basoglu, Woobin Lee, John Setel O'Donnell |
The MAP1000A VLIW Mediaprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(2), pp. 48-59, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Akio Koyama, Makio Uchida, Tatsuhiro Aida, Jun'ya Kudo, Masatoshi Tsuge |
Switching well noise modeling and minimization strategy for digitalcircuits with a controllable threshold voltage scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6), pp. 654-670, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Shantanu Tarafdar, Miriam Leeser |
A data-centric approach to high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1251-1267, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess |
A code-motion pruning technique for global scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(1), pp. 1-38, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
high-level synthesis, code generation, speculative execution, code motion, global scheduling |
10 | Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pegatoquet |
A codesign back-end approach for embedded system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 492-509, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
HW/SW integration, template architecture, codesign, communications synthesis |
10 | S. Ramanathan, S. K. Nandy 0001, V. Visvanathan |
Reconfigurable Filter Coprocessor Architecture for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 26(3), pp. 333-359, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures |
10 | Amit Singh 0001, Luca Macchiarulo, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska |
A novel high throughput reconfigurable FPGA architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 22-29, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam |
The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 399-408, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
texture mapping, Cache memories, parallel rendering, multiprocessing, application specific architecture |
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